Test board combination for chip test and new function development and test method thereof
Through the combination of test boards, including test boards and bottom plates, the problems of single functions and limited use scenarios of traditional chip test boards are solved, and functional expansion and efficiency improvement are achieved.
Patent Information
- Application Number
- CN202411573746.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-03-14
AI Technical Summary
The traditional chip test board has a single function and is limited in use scenarios, so it cannot be tested and switched quickly, resulting in high labor and time costs.
It provides a test board combination, including a test board and a bottom plate. The test board has independent testing functions and is connected to the bottom plate through a plug-in and a gold finger. The bottom plate is equipped with a test board slot, a high-speed signal expansion interface and a power interface, which supports the plug-in and high-speed signal transmission of multiple test boards.
It effectively expands the testing functions and usage scenarios, improves testing efficiency, reduces R&D costs and cycles, and supports rapid testing and switching.
Smart Images
Figure CN119619794A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip testing technology, and in particular to a test board combination and a test method thereof for chip testing and new function development. Background Art
[0002] Currently, the functional applications of test boards used for post-silicon testing of chips are generally relatively simple, and their usage scenarios are subject to certain limitations. It is necessary to separately develop multiple forms of products to verify the development of new functions.
[0003] In addition, the traditional method of relying on a single test board for testing is not conducive to fast testing and fast switching. It can only be performed once through passive power on and off, which greatly wastes manpower and time costs. Summary of the invention
[0004] The embodiments of the present application provide a test board combination and a test method thereof for chip testing and new function development, which can solve at least one technical problem in the background technology.
[0005] In view of this, on the first aspect, an embodiment of the present application provides a test board combination for chip testing and new function development, comprising at least one test board and a base plate, the test board having an independent testing function, a plug-in portion formed on one side of the test board, a plurality of gold fingers formed on the plug-in portion, wherein at least some of the gold fingers are used to transmit high-speed signals, the base plate comprises a test board slot, a plurality of high-speed signal expansion interfaces and a first power interface, the plug-in portion is used to be plugged into the test board slot and electrically connected through the gold fingers, the high-speed signal expansion interface is used to insert peripherals for extended testing, and the first power interface is used to supply power to the base plate.
[0006] Compared with the traditional method of using a test board alone to perform post-silicon testing of chips, the test board combination of the embodiment of the present application includes not only a test board but also a base plate, which is formed with a test board slot, multiple high-speed signal expansion interfaces and a first power supply interface, and a plug-in portion is additionally provided on the test board, which is formed with a gold finger for transmitting high-speed signals, so that the test board can be inserted into the base plate to perform extended testing using the base plate, which solves the technical problem that when a test board is used alone to perform post-silicon testing of chips, the test function is relatively single and the usage scenarios are limited. It can effectively expand the test function and usage scenarios, improve test efficiency and reduce R&D costs.
[0007] Optionally, some of the gold fingers are used to transmit current signals, and the base plate can supply power to the test board through the part of the gold fingers.
[0008] Optionally, the test board further includes a second power interface and multiple types of transmission interfaces, and the second power interface is used to supply power to the test board.
[0009] Optionally, the test board is provided with a hot-swappable power supply protection circuit, and the hot-swappable power supply protection circuit is configured to enable the test board to be inserted into different types of baseboards for testing.
[0010] Optionally, a BMC chip is provided on the test board, and the BMC chip supports remote debugging and monitoring of the state of the test board and remote control of power on and off testing of the test board.
[0011] Optionally, the high-speed signal expansion interface includes a PCIe slot.
[0012] Optionally, the base plate further includes a plurality of auxiliary power interfaces, and the auxiliary power interfaces are used to supply power to peripheral devices inserted into the high-speed signal expansion interface.
[0013] Optionally, the base plate includes a plurality of the test board slots, and each of the test board slots is configured with at least one dedicated high-speed signal expansion interface.
[0014] Optionally, the base plate includes a plurality of the test board slots, and when a plurality of the test boards of the same type or different types are respectively inserted into different test board slots, an interconnection structure is formed through the base plate.
[0015] In a second aspect, the embodiment of the present application further provides a testing method of the test board combination as described above, comprising:
[0016] Inserting the plurality of test boards into different test board slots of the base plate respectively;
[0017] High-speed cables are connected between the plurality of test boards so that the test boards can communicate with each other.
[0018] Compared with the traditional method of using a test board alone for post-silicon chip testing, the test method of the embodiment of the present application inserts multiple test boards into different test board slots of the base board, so that multiple test boards can be used at the same time, thereby improving test efficiency and reducing R&D costs. Moreover, by connecting the test boards with high-speed cables, interconnection communication between the test boards can be achieved, and then interconnection and collaborative verification between multiple test boards can be performed. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 The figure is a schematic diagram of the structure of an existing test board.
[0020] Figure 2 The present invention is a schematic block diagram of the circuit functions of an existing test board.
[0021] Figure 3 It is a schematic diagram of the structure of the test board of the embodiment of the present application.
[0022] Figure 4 It is a schematic diagram of the structure of a test board according to another embodiment of the present application.
[0023] Figure 5 It is a structural schematic diagram of the base plate of an embodiment of the present application.
[0024] Figure 6 It is a structural schematic diagram of a base plate of another embodiment of the present application.
[0025] Figure 7 It is a structural schematic diagram of the test board combination of the embodiment of the present application.
[0026] Figure 8 It is a schematic diagram of the structure of a test board combination according to another embodiment of the present application, wherein each test board is interconnected by a high-speed cable.
[0027] Fig. 9 It is a structural schematic diagram of another test board combination of an embodiment of the present application. DETAILED DESCRIPTION
[0028] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0029] Currently, the functional applications of test boards used for post-silicon testing of chips are generally relatively simple, and their usage scenarios are subject to certain limitations. It is necessary to separately develop multiple forms of products to verify the development of new functions.
[0030] like Figure 1 and Figure 2 As shown, it provides a form and circuit function block diagram of a conventional test board. The test board 1 includes a CPU (central processing unit), a power interface P (Power) and multiple signal interfaces, wherein the power interface P supplies power to the test board 1, and the signal interface can test the chip. The signal interface may include a JTAG interface, an SPI interface, an I2C interface, a UART interface, a GPIO interface, a memory interface I1 (which may be an interface in the form of DDR DIMMs), a PCIe signal interface I2, an M.2 interface, and a PCIe slot I3.
[0031] The function and form of the test board 1 are relatively simple and pure. It is only suitable for centralized screening and debugging testing in factories and laboratories. It is not suitable for use as an internal EVB (evaluation board), and is even less suitable for supplementary verification of new function development. If multiple architecture platforms need to be verified, new test boards or new test platforms need to be developed.
[0032] Moreover, traditional test boards do not support fast testing and fast switching, and can only be executed once through passive power on and off, which greatly wastes manpower and time costs. It is also very easy to cause the risk of damaging the test board when disassembling and assembling, resulting in a waste of resources and not in line with the trend of green environmental protection.
[0033] Since the test board used for screen testing and the test board for the development platform will be developed and designed at different stages, a certain development cycle is bound to be required in between. This will cause the development department to suffer from the lack of debugging boards in the early stages and the inability to debug early, which will extend the overall development cycle.
[0034] See also Figures 3 to 9 An embodiment of the present application discloses a test board combination for chip testing and new function development, including at least one test board 2 and a base board 3.
[0035] The test board 2 has an independent test function, that is, the test board 2 does not need to be combined with the base plate 3, and can test certain functions of the chip separately. A plug-in portion 21 is formed on one side of the test board 2, and a plurality of gold fingers 22 are formed on the plug-in portion 21, wherein at least some of the gold fingers 22 are used to transmit high-speed signals. Specifically, an edge portion of the substrate of the test board 2 forms the main body of the plug-in portion 21, and the gold fingers 22 are distributed on the main body. It can be understood that the gold fingers 22 can be distributed on both sides of the main body at the same time, or can be set on only one side of the main body.
[0036] The base board 3 includes a test board slot 31 , a plurality of high-speed signal expansion interfaces 32 and a first power interface 33 .
[0037] The plug-in portion 21 is used to be plugged into the test board slot 31 and electrically connected through the gold fingers 22. That is, when the plug-in portion 21 is plugged into the test board slot 31, the gold fingers 22 will respectively contact the corresponding conductive terminals of the test board slot 31 to form an electrical connection.
[0038] The high-speed signal expansion interface 32 is used to insert a peripheral device for expansion testing. When the high-speed signal expansion interface 32 is inserted into a peripheral device, high-speed signal transmission can be performed between the peripheral device and the test board 2 through the gold finger 22 to implement expansion testing.
[0039] The first power interface 33 is used to supply power to the base plate 3. That is, when the first power interface 33 is connected to an external power supply device, power can be input to the base plate 3 so that the base plate 3 obtains power required for operation.
[0040] Compared with the traditional method of using the test board 2 alone for post-silicon testing of chips, the test board combination of the embodiment of the present application includes not only the test board 2, but also a base plate 3, on which a test board slot 31, multiple high-speed signal expansion interfaces 32 and a first power supply interface 33 are formed, and the test board 2 is additionally provided with a plug-in portion 21, and the plug-in portion 21 is formed with a gold finger 22 for transmitting high-speed signals, so that the test board 2 can be inserted into the base plate 3 to use the base plate 3 for extended testing, which solves the technical problem that when the test board 2 is used alone for post-silicon testing of chips in the traditional way, the test function is relatively single and the usage scenarios are limited. It can effectively expand the test function and usage scenarios, can be used to develop and verify new functions, increase the utilization rate of the test board 2, and can improve the test efficiency and reduce the R&D cost and cycle.
[0041] In specific use, the baseboard 3 can support different types and versions of test boards 2, and different baseboards 3 can be provided to support different application scenarios.
[0042] In a specific example, the plug-in portion 21 includes two spaced-apart parts, each of which is provided with a set of 140-pin GenZ (high-speed interface specification) gold fingers.
[0043] In some embodiments, some of the gold fingers 22 are used to transmit current signals, and the base plate 3 can supply power to the test board 2 through the part of the gold fingers 22. After the base plate 3 obtains power from the first power interface 33, the base plate 3 can also provide power to the test board 2 through the gold fingers 22, so that the test board 2 obtains the power required for work. It can be understood that in order for the base plate 3 to smoothly supply power to the test board 2, a corresponding power conversion circuit can be set.
[0044] In some embodiments, the test board 2 also includes a second power interface 23 and multiple types of transmission interfaces, and the second power interface 23 is used to supply power to the test board 2. Through the setting of the second power interface 23, the test board 2 can be powered separately, so that the test board 2 can be used alone for chip testing, or it can be plugged with the base plate 3 for chip testing. When plugged into the base plate 3 for chip testing, if the base plate 3 can provide power to the test board 2, the test board 2 can use the power provided by the base plate 3, or it can not use the power of the base plate 3, and use the second power interface 23 to independently power on and off, which will not cause the system to crash due to a power failure of the base plate 3.
[0045] Specifically, the transmission interface may include a memory interface T1, a PCIe signal interface T2, an SMP interface T3, an M.2 interface T4, and an I / O interface T5, etc.
[0046] The I / O interface T5 may include an SFP+ interface, a USB interface (specifically Type A), a UART interface, a VGA interface, an RJ45 interface, and the like.
[0047] Specifically, the second power supply interface 23 can be used to supply power to the test board 2 to independently test some interface functions in the test board 2, such as the memory interface T1, part of the PCIe signal interface T2, the SMP interface T3 (for testing Serdes high-speed signals), the M.2 interface T4 and the I / O interface T5.
[0048] Specifically, the test board 2 may be provided with a hot-swap power protection circuit (not shown), and the hot-swap power protection circuit is configured to enable the test board 2 to be inserted into different types of baseboards 3 for testing. As to how to set the hot-swap power protection circuit, it is known to those skilled in the art and will not be described in detail here. By supporting the hot-swap technology, hot-swap can be used during the test process without affecting the test of other chip test cards, which significantly improves the test efficiency, shortens the factory test time, and saves test manpower and costs.
[0049] Specifically, the test board 2 is provided with a BMC chip 24 , which supports remote debugging and monitoring of the state of the test board 2 and remote control of power-on and power-off testing of the test board 2 , thereby facilitating R&D personnel to perform remote testing.
[0050] Specifically, the test board 2 includes a CPU 25 for testing, etc. The specific structure of the test board 2 is not the focus of this application and will not be described here one by one.
[0051] Specifically, the test board 2 is used for chip screening test and debugging test. When the test board 2 can independently complete the test items, the test board 2 can be used alone for testing, and of course, the test board 2 and the base plate 3 can also be plugged together for testing.
[0052] Figure 3 and Figure 4 Two examples of test board 2 are given respectively. The main differences are: Figure 3 The plug-in portion 21 of the middle test board 2 is extended from the long side of the test board 2. Figure 4 The plug-in portion 21 of the middle test board 2 is extended from the short side of the test board 2 .
[0053] During the screening test phase, all or most of the signal test points can be placed on the test board 2, including high-speed signals through high-speed connectors for loopback testing and low-speed signals through card logic verification testing. As those skilled in the art know, how to set up the test is not described here. Of course, some test points can also be placed on the base plate 3.
[0054] During the laboratory function verification and development stage, the high-speed signal can be led to the baseboard 3 through the gold finger 22 for extended testing (the baseboard 3 is auxiliary designed with a high-speed signal extension interface 32 for extended testing). In addition, the high-speed signal on the test board 2 can be led out to the baseboard 3 through a connector for more expansion and verification development.
[0055] Specifically, several groups of PCIe physical links of the CPU 25 of the test board 2 are led out to the base board 3 through the gold fingers 22, and the base board 3 is auxiliary designed with PCIe slots for extended testing.
[0056] In some embodiments, the high-speed signal expansion interface 32 includes a PCIe slot 321, specifically a standard PCIe slot 321. Of course, the high-speed signal expansion interface 32 is not limited to the PCIe slot 321, but can also be other types of interfaces, and can also include different types of interfaces at the same time.
[0057] In some embodiments, the base plate 3 further includes a plurality of auxiliary power interfaces 34 , and the auxiliary power interfaces 34 are used to supply power to peripheral devices inserted into the high-speed signal expansion interface 32 .
[0058] In some embodiments, the base plate 3 includes a plurality of test board slots 31, and the plurality of test board slots 31 are used to insert test boards 2 of the same type or different types (including different versions of the test board 2). During specific tests, different numbers of test boards 2 can be inserted as needed. By inserting at least two test boards 2 into different test board slots 31 of the base plate 3, at least two test boards 2 can be used at the same time, thereby improving test efficiency and reducing R&D costs. Moreover, functional testing, electrical testing, screen testing, etc. can be flexibly implemented through different combinations,
[0059] Please combine Figure 7 Specifically, when multiple test boards 2 are respectively inserted into different test board slots 31, an interconnection structure is formed through the base plate 3, which can support cluster parallel processing of test boards 2 of the same type, and also support different types of test boards 2, such as the interconnection of a main control board and an acceleration board or a storage board to form a cluster application of a master-slave interface.
[0060] In some embodiments, the base plate 3 includes a plurality of test board slots 31, and each test board slot 31 is configured with at least one dedicated high-speed signal expansion interface 32. That is, when the high-speed signal expansion interface 32 is connected to an external device, the high-speed signal expansion interface 32 transmits high-speed signals to the test board 2 through the corresponding test board slot 31 and the gold finger 22.
[0061] Figure 5 and Figure 6 Two different base plates 3 are disclosed respectively, and the two base plates 3 can be used in different test scenarios.
[0062] exist Figure 5 In the example, the base plate 3 includes four test board slots 31 arranged side by side and at intervals, and three dedicated standard PCIe slots 321 are set for the test board slot 31 on one side of each test board slot 31, and a group of auxiliary power interfaces 34 is respectively provided corresponding to each group of standard PCIe slots 321 (three), that is, a total of 4 groups of auxiliary power interfaces 34 are set.
[0063] The baseboard 3 in this example can support cluster function applications, that is, multiple test boards 2 can be Figure 7 The mode is used for interconnection, which can support cluster parallel processing of the same type of test boards 2, and also support different types of test boards 2, such as the interconnection of the main control board and the acceleration board or storage board to form a cluster application of the master-slave interface.
[0064] exist Figure 6 In the example, the base plate 3 includes three test board slots 31 arranged in a row, and three dedicated standard PCIe slots 321 are set for the test board slot 31 on one side of each test board slot 31, and a group of auxiliary power interfaces 34 is respectively provided corresponding to each group of standard PCIe slots 321 (three), that is, a total of 3 groups of auxiliary power interfaces 34 are set.
[0065] The base plate 3 in this example can support chip screening test, that is, multiple test boards 2 are plugged into the base plate 3 to form an interconnection structure (such as Fig. 9 As shown), the interconnection structure can be used in an automated testing machine.
[0066] Understandably, Figure 5 and Figure 6 What is shown is only an example of the bottom plate 3 , and the bottom plate 3 can have various different designs.
[0067] Please combine Figure 8 The present application also discloses a test method for a test board combination, including:
[0068] (1) inserting a plurality of test boards 2 into different test board slots 31 of the base plate 3 respectively;
[0069] (2) High-speed cables 4 are connected between the multiple test boards 2 so that the test boards 2 can communicate with each other.
[0070] By connecting multiple test boards 2 to each other through high-speed cables 4 for interconnection and communication, collaborative verification of multiple test cards can be achieved.
[0071] In a specific example, each test board 2 includes two SFP+ interfaces, and the two SFP+ interfaces of each test board 2 are connected to an SFP+ interface of a different test board 2 through a high-speed cable 4, so that each test board 2 is connected to form a loop. In addition, two groups of PCIe signal interfaces T2 of two test boards 2 are connected through a high-speed cable 4, and two groups of PCIe signal interfaces T2 of another two test boards 2 are also connected through a high-speed cable 4.
[0072] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.
Claims
1. A test board combination for chip testing and new function development, characterized in that: It includes at least one test board and a base plate, the test board has an independent test function, a plug-in portion is formed on one side of the test board, and a plurality of gold fingers are formed on the plug-in portion, wherein at least some of the gold fingers are used to transmit high-speed signals, the base plate includes a test board slot, multiple high-speed signal expansion interfaces and a first power interface, the plug-in portion is used to be plugged into the test board slot and electrically connected through the gold fingers, the high-speed signal expansion interface is used to insert peripherals for extended testing, and the first power interface is used to supply power to the base plate.
2. The test board assembly according to claim 1, characterized in that: Some of the gold fingers are used to transmit current signals, and the base plate can supply power to the test board through the gold fingers.
3. The test board assembly according to claim 1, characterized in that: The test board also includes a second power interface and multiple types of transmission interfaces, and the second power interface is used to supply power to the test board.
4. The test board assembly according to claim 1, characterized in that: The test board is provided with a hot-swap power protection circuit, and the hot-swap power protection circuit is configured to enable the test board to be inserted into different types of baseboards for testing.
5. The test board assembly according to claim 1, characterized in that: The test board is provided with a BMC chip, and the BMC chip supports remote debugging and monitoring of the state of the test board and remote control of the power on and off test of the test board.
6. The test board assembly according to claim 1, characterized in that: The high-speed signal expansion interface includes a PCIe slot.
7. The test board assembly according to claim 1, characterized in that: The base plate also includes a plurality of auxiliary power interfaces, and the auxiliary power interfaces are used to supply power to peripheral devices inserted into the high-speed signal expansion interface.
8. The test board assembly according to claim 1, characterized in that: The base plate includes a plurality of the test board slots, and each of the test board slots is configured with at least one dedicated high-speed signal expansion interface.
9. The test board assembly according to claim 1, characterized in that: The bottom plate comprises a plurality of the test board slots, and when a plurality of the test boards of the same type or different types are respectively inserted into different test board slots, an interconnection structure is formed through the bottom plate.
10. The testing method of the test board assembly according to claim 9, characterized in that: include: Inserting the plurality of test boards into different test board slots of the base plate respectively; High-speed cables are connected between the plurality of test boards so that the test boards can communicate with each other.