Wafer test method and device, test machine and storage medium

Abstract

The invention relates to the technical field of wafer testing, and provides a wafer testing method and device, a testing machine and a storage medium. Each probe in the probe card of the testing machine is provided with a probe group to which the probe belongs, and each probe and the probe at the adjacent position belong to different probe groups. The method comprises the following steps: firstly, obtaining a corresponding target signal sampling time point set according to a wafer model of a to-be-detected wafer; sequentially controlling each probe group to test the bare chip in the wafer to be tested in each test period to obtain a test result of each probe group; and finally, taking the test results of all the probe groups as the test result of one test period. By grouping the probes, the distance between the probes during testing is enlarged, and signal interference between different probes is reduced. Moreover, the influence of the performance difference of different testing machines on the wafer testing is reduced, and the stability and accuracy of the wafer testing are improved.

Description

Technical Field

[0001] The present invention relates to the field of wafer testing technology, and in particular to a wafer testing method, device, testing machine and storage medium. Background Art

[0002] CP (Chip Probing) testing is wafer testing, which uses the probe card on the tester to test each die in the wafer. The probe card performs the test by touching the wafer. There are multiple probes, or sites, on the probe card, and one probe is used to contact one die for testing.

[0003] When performing CP testing, there is signal interference between different probes. Especially when the test frequency is high, the signal transmission between different probes may be unstable, or the signal strength of some probes may be too strong, affecting other probes, resulting in inaccurate test results. And because the performance and specifications of different testers are different, the strobes or signal sampling time points used are also different, which will also affect the stability of the test signal. At present, signal interference is generally reduced by adding coaxial cables to the probe card, but this method can only reduce signal interference to a certain extent and cannot meet certain scenarios with high requirements for test accuracy. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a wafer testing method, device, testing machine and storage medium.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a wafer testing method, which is applied to a tester, wherein each probe in a probe card of the tester has a probe group to which it belongs, and each probe and a probe at an adjacent position belong to a different probe group, and the tester pre-stores a signal sampling time point set corresponding to a plurality of wafer models or different testers pre-store a signal sampling time point set corresponding to the same wafer model, and the wafer testing method comprises:

[0007] According to the wafer model of the wafer to be tested, a corresponding signal sampling time point set is obtained from all signal sampling time point sets to obtain a target signal sampling time point set;

[0008] In any test cycle, each of the probe groups is used as a target probe group in turn;

[0009] Based on the target signal sampling time point set, each probe in the target probe group is controlled to test the bare die at the corresponding position in the wafer to be tested to obtain the test result of the target probe group; each probe group is traversed to obtain the test result of each probe group, and the test results of all probe groups are used as the test results of a test cycle.

[0010] In an optional implementation, each of the signal sampling time point sets includes an initial signal sampling time point and at least one backup signal sampling time point;

[0011] The step of controlling each probe in the target probe group based on the target signal sampling time point set to test the die at the corresponding position in the wafer to be tested and obtaining the test result of the target probe group includes:

[0012] Controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtaining an initial test result of each probe in the target probe group;

[0013] For each probe in the target probe group, if the initial test result of the probe is pass, the probe is used as the first probe and pass is used as the final test result of the first probe, or, if the initial test result of the probe is fail, the probe is used as the second probe;

[0014] Controlling each of the second probes to retest the bare die at a corresponding position in the wafer to be tested, and obtaining a final test result of each of the second probes;

[0015] The final test results of all the first probes and the final test results of all the second probes in the target probe group are taken together as the test result of the target probe group.

[0016] In an optional embodiment, the step of controlling each of the second probes to retest the die at a corresponding position in the wafer to be tested to obtain a final test result of each of the second probes includes:

[0017] During the first retest, the initial signal sampling time point in the target signal sampling time point set is used as the target signal sampling time point, and each of the second probes is used as a probe to be processed;

[0018] Controlling each of the probes to be processed to retest the bare die at the corresponding position in the wafer to be tested according to the target signal sampling time point, and obtaining a retest result of each of the probes to be processed;

[0019] For each of the probes to be processed, if the retest result of the probe to be processed is passed, pass is used as the final test result of the second probe represented by the probe to be processed;

[0020] If the retest result of the probe to be processed is failure and the current retest times have not reached the preset times, the probe to be processed continues to be used as the probe to be processed, and each of the probes to be processed is obtained, and a spare signal sampling time point is obtained from the target signal sampling time point set as a new target signal sampling time point, and then the step of controlling each probe to be processed is re-executed, and the bare die at the corresponding position in the wafer to be tested is retested according to the target signal sampling time point to obtain the retest result of each probe to be processed;

[0021] If the retest result of the probe to be processed is failed and the current retest times reach the preset times, the failed is used as the final test result of the second probe represented by the probe to be processed, and the final test result of each second probe is obtained; wherein the preset times is greater than 1.

[0022] In an optional implementation manner, a signal sampling time point set corresponding to any wafer model is obtained in the following manner:

[0023] For any wafer model, determining a candidate range of signal sampling time points corresponding to the wafer model;

[0024] An initial signal sampling time point and at least one spare signal sampling time point are selected from the candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and the at least one spare signal sampling time point, thereby obtaining a signal sampling time point set corresponding to the wafer model.

[0025] In an optional implementation, the step of determining a candidate range of signal sampling time points corresponding to the wafer model includes:

[0026] The original range of signal sampling time points corresponding to the wafer model pre-stored in multiple testers is obtained, and the intersection is calculated based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

[0027] In an optional implementation, the step of determining a candidate range of signal sampling time points corresponding to the wafer model includes:

[0028] The original ranges of signal sampling time points corresponding to the wafer model and multiple other wafer models pre-stored in the tester are obtained, and the intersection is calculated based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

[0029] In an optional implementation, the step of selecting an initial signal sampling time point and at least one spare signal sampling time point from the candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and the at least one spare signal sampling time point includes:

[0030] Calculate an average value based on the lower limit value and the upper limit value of the candidate range of the signal sampling time point, and use the average value as the initial signal sampling time point;

[0031] From the candidate range of signal sampling time points, a time point other than the initial signal sampling time point is selected as a backup signal sampling time point, and a set including the initial signal sampling time point and at least one backup signal sampling time point is obtained.

[0032] In a second aspect, the present invention provides a wafer testing device, which is applied to a tester, wherein each probe in a probe card of the tester has a probe group to which it belongs, and each probe and a probe at an adjacent position belong to a different probe group, and the tester pre-stores a signal sampling time point set corresponding to a plurality of wafer models or different testers pre-store a signal sampling time point set corresponding to the same wafer model, and the wafer testing device comprises:

[0033] An acquisition module is used to acquire a corresponding signal sampling time point set from all signal sampling time point sets according to the wafer model of the wafer to be tested, so as to obtain a target signal sampling time point set;

[0034] A testing module, used for sequentially using each of the probe groups as a target probe group in any test cycle;

[0035] Based on the target signal sampling time point set, control each probe in the target probe group to test the die at the corresponding position in the wafer to be tested, and obtain the test result of the target probe group;

[0036] Each of the probe groups is traversed to obtain a test result of each probe group, and the test results of all the probe groups are used as the test results of a test cycle.

[0037] In an optional implementation manner, each of the signal sampling time point sets includes an initial signal sampling time point and at least one spare signal sampling time point, and the test module is further used to:

[0038] Controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtaining an initial test result of each probe in the target probe group;

[0039] For each probe in the target probe group, if the initial test result of the probe is pass, the probe is used as the first probe and pass is used as the final test result of the first probe, or, if the initial test result of the probe is fail, the probe is used as the second probe;

[0040] Controlling each of the second probes to retest the bare die at a corresponding position in the wafer to be tested, and obtaining a final test result of each of the second probes;

[0041] The final test results of all the first probes and the final test results of all the second probes in the target probe group are taken together as the test result of the target probe group.

[0042] In a third aspect, the present invention provides a storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the wafer testing method described in any one of the aforementioned embodiments is implemented.

[0043] The wafer testing method, device, test machine and storage medium provided by the present invention are applied to the test machine, and each probe in the probe card of the test machine has a probe group to which it belongs, and each probe belongs to a different probe group from the probe at the adjacent position. The method comprises: first, according to the wafer model of the wafer to be tested, the corresponding signal sampling time point set is obtained from all signal sampling time point sets to obtain the target signal sampling time point set; then, in any test cycle, each probe group is sequentially used as the target probe group; and based on the target signal sampling time point set, each probe in the target probe group is controlled to test the bare die at the corresponding position in the wafer to be tested, and the test result of the target probe group is obtained; then, each probe group is traversed to obtain the test result of each probe group, and the test results of all probe groups are used as the test result of a test cycle. By testing the wafer by grouping the probes, the distance between the probes tested at the same time is expanded, and the signal interference between different probes is reduced. And each test machine uses the same signal sampling time point set to test the wafer of the same model, which reduces the influence of the performance difference between different test machines on the wafer test, thereby improving the stability and accuracy of the wafer test.

[0044] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A block diagram of a testing machine provided by an embodiment of the present invention is shown;

[0047] Figure 2 A schematic diagram of a process flow of a wafer testing method provided by an embodiment of the present invention is shown;

[0048] Figure 3 An example diagram of probe grouping provided by an embodiment of the present invention is shown;

[0049] Figure 4 A functional module diagram of a wafer testing device provided by an embodiment of the present invention is shown.

[0050] Icons: 100 - test machine; 110 - processor; 120 - memory; 130 - communication module; 300 - wafer test device; 310 - acquisition module; 330 - test module. DETAILED DESCRIPTION

[0051] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0052] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0053] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0054] See also Figure 1 , is a block diagram of a test machine provided by an embodiment of the present invention. The test machine 100 includes a processor 110, a memory 120, and a communication module 130, and each component is directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0055] The processor 110 is used to read / write data or programs stored in the memory 120 and execute corresponding functions. It can be a general-purpose processor, including a CPU (Central Processing Unit), NP (Network Processor), etc.; it can also be a DSP digital signal processor, an ASIC application-specific integrated circuit, an FPGA off-the-shelf programmable gate array or other programmable logic devices, discrete gates or transistor logic devices, and discrete hardware components.

[0056] The memory 120 is used to store programs or data. The memory 120 can be a RAM (Random Access Memory), a ROM (Read Only Memory), a PROM (Programmable Read-Only Memory), an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electric Erasable Programmable Read-Only Memory), etc.

[0057] The communication module 130 is used to perform signaling or data communications with other devices.

[0058] Understandably, Figure 1 The structure shown is only a schematic diagram of the structure of the test machine 100. The test machine 100 may also include Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown. Figure 1 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0059] The above-mentioned test machine 100 will be used as an execution subject to execute each step in each method provided by the embodiment of the present invention and achieve corresponding technical effects.

[0060] See also Figure 2 , is a flow chart of a wafer testing method provided in an embodiment of the present invention.

[0061] Step S202 , according to the wafer model of the wafer to be tested, a corresponding signal sampling time point set is acquired from all signal sampling time point sets to obtain a target signal sampling time point set.

[0062] Step S204: In any test cycle, each probe group is used as a target probe group in turn.

[0063] Step S206 , based on the target signal sampling time point set, controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested, and obtaining the test result of the target probe group.

[0064] Step S208, traverse each probe group, obtain the test result of each probe group, and use the test results of all probe groups as the test results of a test cycle.

[0065] It should be noted that a wafer can have multiple operating frequencies, which determines the time required for the wafer to perform a complete operation, that is, the length of a working cycle. When testing the wafer, an operating frequency will be selected as the test frequency so that the wafer runs at the test frequency and collects signals in each working cycle. The signal sampling time point can be understood as the time point at which the signal is collected in a working cycle, which is usually expressed as a percentage or fraction. For example, assuming that the length of a working cycle of the wafer is 100ns and the signal sampling time point is 50%, it means that the signal is collected at the 50ns of the working cycle.

[0066] It can be understood that, in the embodiment of the present invention, for the same test machine, the test machine pre-stores a signal sampling time point set corresponding to multiple wafer models, so that the impact of the same test machine testing different wafers can be reduced. For different test machines, these test machines pre-store a signal sampling time point set corresponding to the same wafer model, so that the impact of different test machines testing the same wafer can be reduced.

[0067] In this embodiment, each probe in the probe card of the tester has a probe group to which it belongs, and each probe belongs to a different probe group from the probes at adjacent positions. For ease of understanding, the embodiment of the present invention takes 256 probes on the probe card as an example and provides an example diagram of probe grouping.

[0068] See also Figure 3 , which includes two probe groups, namely probe group A and probe group B. Probe group A includes 128 probes, namely a1 to a128; probe group B also includes 128 probes, namely b1 to b128. Figure 3 The white squares in the figure represent probes in probe group A, and the gray squares represent probes in probe group B. And any probe and the probes at adjacent positions, i.e., the probes located above, below, left, and right thereof, belong to different probe groups. It should be understood that the number of probe groups, the total number of probes in each probe group, and the grouping method of the probes can be set according to actual conditions, and the present invention is not limited to this.

[0069] It is understandable that there are two ways to use each probe group to test the wafer to be tested in one test cycle. The first test method is to use each probe group to test the wafer to be tested one by one in one test cycle. That is, the next probe group is used to test the wafer to be tested only after the previous probe group has finished testing the wafer to be tested. For example, when the probe card is in the first position, probe group A is used to test the wafer to be tested, and then the probe card is controlled to move to the second position, and probe group A is used again to test the wafer to be tested, until the probe card traverses all positions, that is, after completing the test of the wafer to be tested by probe group A, probe group B is used to test the wafer to be tested in a similar manner.

[0070] The second test method is to use multiple probe groups to alternately test the wafer to be tested in one test cycle. For example, when the probe card is in the first position, the wafer to be tested is first tested using probe group A, and then the wafer to be tested is tested using probe B. Then the probe card is controlled to move to the second position, and the wafer to be tested is first tested using probe group A, and then the wafer to be tested is tested using probe B. That is, when the probe card is in each position, each probe group is used alternately to test the wafer to be tested. One test cycle in this test method is a TouchDown.

[0071] It should be understood that the above two test methods are merely examples, and the test cycle and test method may be set according to actual conditions, which is not limited in the embodiment of the present invention.

[0072] The following will Figure 3The probe grouping method shown in the figure and the second test method are used as examples for explanation. First, the test machine pre-stores a signal sampling time point set corresponding to a variety of wafer models, so the signal sampling time point set corresponding to the wafer model of the wafer to be tested can be obtained from all the signal sampling time point sets, and the target signal sampling time point set is obtained. Then, in each test cycle, the test machine will control each probe group in turn to test the wafer to be tested to obtain the test results of each probe group. Since the method of controlling each probe group for testing is similar, for the sake of simplicity, the target probe group is probe group A as an example for explanation below.

[0073] In any test cycle, the tester controls each probe in probe group A, i.e., a1 to a128, based on the target signal sampling time point set to test the dies at the corresponding positions in the wafer to be tested, i.e., 128 dies, and obtains the test results of a group of dies in the wafer to be tested, i.e., the test results of probe group A. In a similar manner, the tester controls each probe in probe group B, i.e., b1 to b128, to test, and obtains the test results of another group of dies in the wafer to be tested, i.e., the test results of probe group B. And the test results of probe group A and probe group B are taken as the test results of a test cycle, i.e., the test results of a test cycle include the test results of 256 dies in the wafer to be tested.

[0074] It is understandable that, since the positions of the probes in a probe group are not adjacent, and one probe is used to contact a bare die for testing, the positions of the bare die tested by the probes in a probe group are also not adjacent, thus expanding the distance between the probes tested at the same time, and thus reducing the signal interference between different probes. In addition, since different testers use the same signal sampling time point set to test the same model of wafer, the impact of performance differences between different testers on wafer testing can be reduced, thereby improving the stability and accuracy of wafer testing.

[0075] It can be seen that based on the above steps, first, according to the wafer model of the wafer to be tested, the corresponding signal sampling time point set is obtained from all signal sampling time point sets to obtain the target signal sampling time point set; then, in any test cycle, each probe group is used as the target probe group in turn; and based on the target signal sampling time point set, each probe in the target probe group is controlled to test the bare die at the corresponding position in the wafer to be tested, and the test result of the target probe group is obtained; then, each probe group is traversed to obtain the test result of each probe group, and the test results of all probe groups are used as the test result of a test cycle. By testing the wafer by grouping the probes, the distance between the probes tested at the same time is expanded, and the signal interference between different probes is reduced. In addition, each tester uses the same signal sampling time point set to test the wafer of the same model, which reduces the impact of the performance differences between different testers on the wafer test, thereby improving the stability and accuracy of the wafer test.

[0076] Optionally, for step S206, an embodiment of the present invention provides a possible implementation method.

[0077] Step S206 - 1 , controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtaining the initial test result of each probe in the target probe group.

[0078] Step S206-3, for each probe in the target probe group, if the initial test result of the probe is pass, the probe is used as the first probe and pass is used as the final test result of the first probe, or if the initial test result of the probe is fail, the probe is used as the second probe.

[0079] Step S206 - 5 , controlling each second probe to retest the bare die at the corresponding position in the wafer to be tested, and obtaining the final test result of each second probe.

[0080] Step S206 - 7 , taking the final test results of all the first probes and the final test results of all the second probes in the target probe group as the test result of the target probe group.

[0081] In this embodiment, each signal sampling time point set includes at least two signal sampling time points, one of which is an initial signal sampling time point, and the others are backup signal sampling time points. The initial signal sampling time point can be understood as the signal sampling time point used in the initial test. The backup signal sampling time point can be understood as the signal sampling time point that can be selected for retesting.

[0082] For ease of understanding, the above-mentioned probe group A is continued to be explained as an example. During the initial test, each probe in the probe group A is controlled to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set. That is, through the test signal, a pre-set test program is executed to measure the functional state of the bare die, such as executing test steps such as voltage measurement, current reading, and logic comparison, and the initial test results are collected according to the initial signal sampling time point to obtain the initial test results of each probe in the probe group A.

[0083] Then, determine whether each probe needs to be retested based on the initial test result of each probe in probe group A. If the initial test result of the probe is pass, it means that the die tested by the probe is qualified, then the probe is classified as the first probe that does not need to be retested, and pass is used as the final test result of the first probe to obtain the final test result of each first probe in probe group A.

[0084] If the initial test result of the probe is failure, it means that the die tested by the probe is unqualified, and the probe is classified as a second probe that needs to be retested to obtain each second probe in probe group A. And each second probe is controlled to retest the die at the corresponding position in the wafer to be tested to obtain the final test result of each second probe in probe group A.

[0085] Finally, the final test results of all the first probes in probe group A and the final test results of all the second probes are taken as the test result of probe group A.

[0086] Optionally, for step S206-5, an embodiment of the present invention provides a possible implementation method.

[0087] Step S206-5-1, during the first retest, the initial signal sampling time point in the target signal sampling time point set is used as the target signal sampling time point, and each second probe is used as a probe to be processed.

[0088] Step S206-5-3, controlling each probe to be processed to retest the bare die at the corresponding position in the wafer to be tested according to the target signal sampling time point, and obtaining the retest result of each probe to be processed.

[0089] Step S206-5-5: for each probe to be processed, if the retest result of the probe to be processed is pass, pass is used as the final test result of the second probe represented by the probe to be processed.

[0090] Step S206-5-7, if the retest result of the probe to be processed is failed and the current number of retests has not reached the preset number, the probe to be processed will continue to be used as the probe to be processed, and each probe to be processed will be obtained, and the backup signal sampling time point will be obtained from the target signal sampling time point set as the new target signal sampling time point, and then step S206-5-3 will be re-executed.

[0091] Step S206-5-9, if the retest result of the probe to be processed is failed and the current retest times reach the preset times, then take failed as the final test result of the second probe represented by the probe to be processed, and obtain the final test result of each second probe; wherein the preset times is greater than 1.

[0092] For ease of understanding, the above-mentioned probe group A is continued to be explained as an example. Based on the fact that some probes in probe group A passed the test during the initial test, only some of the probes in probe group A will be retested, and the distribution of these probes that need to be retested will be sparser and the spacing will be larger, so that the signal interference between different probes can be further reduced to improve the accuracy of wafer testing. At the same time, when the embodiment of the present invention is retested for the first time, the same signal sampling time point as the initial test will be used to analyze whether the probe failed the initial test due to the influence of other probes during the initial test.

[0093] For example, the preset number of times is 2, that is, the total number of retests is set to 2. In the first retest, the initial signal sampling time point is used as the target signal sampling time point, that is, the initial signal sampling time point is used as the signal sampling time point used in the first retest, and each second probe in probe group A is used as a probe to be processed.

[0094] Each probe to be processed is controlled to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point, and the first retest result of each probe to be processed is obtained. And according to the first retest result of each probe to be processed, it is determined whether each probe to be processed needs to be retested.

[0095] If the first retest result of the probe to be processed is passed, that is, the retest result of the bare chip tested by the probe to be processed is qualified, then it means that the second probe represented by the probe to be processed may have failed the initial test due to the influence of other probes during the initial test, that is, the initial test result of the second probe is inaccurate, then the retest result of this time, that is, passed, is used as the final test result of the second needle.

[0096] If the first retest result of the probe to be processed is not passed, that is, the retest result of the bare chip tested by the probe to be processed is unqualified, then the current retest times are compared with the preset times. Since the current retest times, i.e., 1 times, do not reach the preset times, i.e., 2 times, the probe to be processed will continue to be used as the probe to be processed in the next retest process, i.e., the second retest process, for retesting.

[0097] It is understandable that the same tester may have different performance when using different signal sampling time points for testing. Therefore, when the embodiment of the present invention is not the first retest, a signal sampling time point different from the initial test is used to analyze whether the probe fails the retest due to the incompatibility of the selected signal sampling time point.

[0098] After obtaining each probe to be processed in the second retest process, obtain the spare signal sampling time point from the target signal sampling time point set as the signal sampling time point used for the second retest. Then control each probe to be processed, test the bare die at the corresponding position in the wafer to be tested according to the spare signal sampling time point, and obtain the second retest result of each probe to be processed. And according to the second retest result of each probe to be processed, determine whether each probe to be processed needs to be retested.

[0099] If the second retest result of the probe to be processed is passed, that is, the retest result of the bare chip tested by the probe to be processed is qualified, then it means that the second probe represented by the probe to be processed may have failed the retest due to the incompatibility of the signal sampling time point selected in the previous retest, that is, the previous retest result of the second probe was inaccurate, then the current retest result, i.e., passed, is used as the final test result of the second probe.

[0100] If the second retest result of the probe to be processed is not passed, that is, the retest result of the bare chip tested by the probe to be processed is unqualified, then the current retest number is compared with the preset number. Since the current retest number reaches the preset number, that is, 2 times, it means that after excluding the influence of other probes during the initial test and the incompatibility of the signal sampling time point selected during the retest, the bare chip tested by the second probe is still unqualified, so the failure is used as the final test result of the second detection. By performing multiple retests, the final test result of each second probe in probe group A can be obtained.

[0101] It should be understood that the total number of retests can be set according to actual conditions, and the embodiments of the present invention do not limit this. For example, in order to improve the accuracy and stability of the retest, the relationship between the total number of retests and the number of spare signal sampling time points in the signal sampling time point set can be preset. That is, the total number of retests is less than or equal to the number of spare signal sampling time points in the signal sampling time point set.

[0102] When the number of spare signal sampling time points in the signal sampling time point set is more than one, a corresponding priority can be set for each spare signal sampling time point, so that when it is not the first retest, the candidate signal sampling time point whose priority matches the current retest number, such as k, can be selected as the signal sampling time point used for the k+1th retest. And the larger the current retest number, the lower the priority matching it.

[0103] Optionally, for a signal sampling time point set corresponding to any of the above-mentioned wafer models, an embodiment of the present invention provides a method for obtaining the signal sampling time point set.

[0104] Step S212: for any wafer model, determine a candidate range of signal sampling time points corresponding to the wafer model.

[0105] Step S214, selecting an initial signal sampling time point and at least one spare signal sampling time point from the candidate range of signal sampling time points, obtaining a set including the initial signal sampling time point and at least one spare signal sampling time point, and obtaining a signal sampling time point set corresponding to the wafer model.

[0106] It can be understood that the method for determining the signal sampling time point set corresponding to each wafer model is similar. For the sake of simplicity, one wafer model is used as an example for explanation below.

[0107] In this embodiment, the candidate range of signal sampling time points corresponding to the wafer model is first determined. This candidate range of signal sampling time points can be understood as the empirical value range of the signal sampling time points for testing the wafer of the wafer model. Then, from the candidate range of signal sampling time points, an initial signal sampling time point and at least one spare signal sampling time point are selected, so that a set including the initial signal sampling time point and at least one spare signal sampling time point can be obtained, that is, a set of signal sampling time points corresponding to the wafer model is obtained.

[0108] It should be understood that in some embodiments, an initial signal sampling time point and multiple spare signal sampling time points may be selected from the candidate range of signal sampling time points to form a signal sampling time point set. For a signal sampling time point set including multiple spare signal sampling time points, a corresponding priority may be set for each spare signal sampling time point, so that during the retesting process, different spare signal sampling time points may be selected according to the priority for testing.

[0109] Optionally, for step S212, an embodiment of the present invention provides a possible implementation method, namely: obtaining the original range of signal sampling time points corresponding to wafer models pre-stored in multiple testers, and calculating the intersection based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer models.

[0110] It is understandable that in the related art, each tester will store the signal sampling time point range for testing the wafer of the wafer model, that is, the original range of the signal sampling time points. Then, when performing wafer testing, each tester selects a signal sampling time point from the original range of the signal sampling time points stored in itself for testing. This will cause different testers to use different signal sampling time points to test the same model of wafer, which will affect the accuracy of wafer testing.

[0111] Therefore, the embodiment of the present invention obtains the signal sampling time point range of the wafer originally used to test the wafer model in multiple test machines on the basis of the relevant technology to obtain multiple original ranges of signal sampling time points. Then, the intersection of these multiple original ranges of signal sampling time points is calculated to obtain the candidate range of signal sampling frequencies corresponding to the wafer model. Obtaining the candidate range of signal sampling time points in this way not only takes into account the performance characteristics of different test machines, but also ensures that the candidate range of signal sampling time points matches the test capabilities of each test machine, thereby providing data support for improving the accuracy of wafer testing.

[0112] Optionally, for step S212, an embodiment of the present invention provides another possible implementation method, namely: obtaining the original range of signal sampling time points corresponding to the wafer model pre-stored in the tester and multiple other wafer models, and calculating the intersection based on all the original ranges of the signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

[0113] In this embodiment, in order to reduce the impact of the same tester on testing different types of wafers, the signal sampling time point ranges corresponding to the wafer model and multiple other wafer models originally stored in the tester can also be obtained to obtain multiple original ranges of signal sampling time points. Then, the intersection of these multiple original ranges of signal sampling time points is calculated to obtain the candidate range of signal sampling frequencies corresponding to the wafer model. Obtaining the candidate range of signal sampling time points in this way not only takes into account the performance characteristics of different wafer models, but also ensures that the candidate range of signal sampling time points is compatible with multiple wafer models, thereby providing data support for improving the accuracy of wafer testing.

[0114] Optionally, for step S214, an embodiment of the present invention provides a possible implementation method.

[0115] Step S214 - 1 , calculating an average value based on the lower limit value and the upper limit value of the candidate range of the signal sampling time point, and taking the average value as the initial signal sampling time point.

[0116] Step S214-3: Select a time point other than the initial signal sampling time point from the candidate range of signal sampling time points as a backup signal sampling time point, and obtain a set including the initial signal sampling time point and at least one backup signal sampling time point.

[0117] In this embodiment, based on the obtained candidate range of signal sampling time points, the lower limit value and the upper limit value of the candidate range of signal sampling time points can be obtained, then the average value can be calculated based on the lower limit value and the upper limit value, and the average value is used as the initial signal sampling time point, that is, the optimal signal sampling time point for testing the wafer is obtained. Then, from the remaining time points in the candidate range of signal sampling time points, a time point is selected as a backup signal sampling time point. In this way, a set including the initial signal sampling time point and at least one backup signal sampling time point is obtained.

[0118] Regarding the method of selecting the backup signal sampling time point, the embodiment of the present invention provides two implementation methods. One is to randomly select a time point from the remaining time points as the backup signal sampling time point. The other is to calculate half of the absolute value of the difference between the lower limit value and the upper limit value based on the lower limit value and the upper limit value to obtain the adjustment parameter, and use the sum of the initial signal sampling time point plus the adjustment parameter as the backup signal sampling time point, or use the difference between the initial signal sampling time point and the adjustment parameter as the backup signal sampling time point. It should be understood that the method of selecting the backup signal sampling time point can also be set according to actual conditions, and the embodiment of the present invention does not limit this.

[0119] Optionally, multiple backup signal sampling time points may be selected and combined with the initial signal sampling time point to form a signal sampling time point set. Then, multiple backup signal sampling time points may be randomly selected from the remaining time points in the candidate range of signal sampling time points, and then the priorities corresponding to each of these backup signal sampling time points may be set according to the difference between these backup signal sampling time points and the initial signal sampling time point. Furthermore, the smaller the difference between the backup signal sampling time point and the initial signal sampling time point, the greater its priority.

[0120] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing a wafer testing device is provided below. Figure 4 , is a functional module diagram of a wafer testing device provided in an embodiment of the present invention. It should be noted that the basic principle and technical effects of the wafer testing device 300 provided in this embodiment are the same as those in the above embodiment. For the sake of brief description, for matters not mentioned in this embodiment, reference may be made to the corresponding contents in the above embodiment. The wafer testing device 300 includes:

[0121] The acquisition module 310 is used to acquire a corresponding signal sampling time point set from all signal sampling time point sets according to the wafer model of the wafer to be tested, so as to obtain a target signal sampling time point set.

[0122] The test module 330 is used to take each probe group as the target probe group in turn in any test cycle; based on the target signal sampling time point set, control each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested, and obtain the test result of the target probe group; traverse each probe group to obtain the test result of each probe group, and take the test results of all probe groups as the test result of a test cycle.

[0123] Optionally, the test module 330 is also used to: control each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtain the initial test result of each probe in the target probe group; for each probe in the target probe group, if the initial test result of the probe is passed, the probe is used as the first probe, and the pass is used as the final test result of the first probe, or, if the initial test result of the probe is failed, the probe is used as the second probe; control each second probe to retest the bare die at the corresponding position in the wafer to be tested, and obtain the final test result of each second probe; and use the final test results of all the first probes and the final test results of all the second probes in the target probe group as the test result of the target probe group.

[0124] Optionally, the test module 330 is also used to: during the first retest, use the initial signal sampling time point in the target signal sampling time point set as the target signal sampling time point, and use each second probe as a probe to be processed; control each probe to be processed, and retest the bare die at the corresponding position in the wafer to be tested according to the target signal sampling time point to obtain the retest result of each probe to be processed; for each probe to be processed, if the retest result of the probe to be processed is passed, then pass is used as the final test result of the second probe represented by the probe to be processed; if the retest result of the probe to be processed is failed and the current number of retests has not reached the preset number of times , then the probe to be processed continues to be the probe to be processed, and each probe to be processed is obtained, and the spare signal sampling time point is obtained from the target signal sampling time point set as the new target signal sampling time point, and then the control of each probe to be processed is re-executed, and the bare die at the corresponding position in the wafer to be tested is retested according to the target signal sampling time point to obtain the retest result of each probe to be processed; if the retest result of the probe to be processed is failed and the current retest number reaches the preset number, then the failed test result is used as the final test result of the second probe represented by the probe to be processed, and the final test result of each second probe is obtained; wherein the preset number is greater than 1.

[0125] Optionally, the signal sampling time point set corresponding to any wafer model is obtained in the following manner: for any wafer model, determine the candidate range of signal sampling time points corresponding to the wafer model; select an initial signal sampling time point and at least one backup signal sampling time point from the candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and at least one backup signal sampling time point, and obtain the signal sampling time point set corresponding to the wafer model.

[0126] Optionally, the process of determining the candidate range of signal sampling time points corresponding to the wafer model is implemented in the following manner: obtaining the original range of signal sampling time points corresponding to the wafer models pre-stored in multiple testing machines, and calculating the intersection based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

[0127] Optionally, the process of determining the candidate range of signal sampling time points corresponding to the wafer model can also be implemented in the following manner: obtain the original range of signal sampling time points corresponding to the wafer model pre-stored in the tester and multiple other wafer models, and calculate the intersection based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

[0128] Optionally, the process of selecting an initial signal sampling time point and at least one backup signal sampling time point from a candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and at least one backup signal sampling time point is implemented in the following manner: calculating an average value based on the lower limit value and the upper limit value of the candidate range of signal sampling time points, and taking the average value as the initial signal sampling time point; selecting a time point other than the initial signal sampling time point from the candidate range of signal sampling time points as a backup signal sampling time point to obtain a set including the initial signal sampling time point and at least one backup signal sampling time point.

[0129] An embodiment of the present invention further provides a testing machine, including a processor and a memory, wherein the memory stores a computer program, and when the processor executes the computer program, the wafer testing method disclosed in the embodiment of the present invention is implemented.

[0130] An embodiment of the present invention further provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the wafer testing method disclosed in the embodiment of the present invention is implemented.

[0131] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0132] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0133] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0134] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A wafer testing method, characterized in that: Applied to a tester, each probe in a probe card of the tester has a probe group to which it belongs, each probe and a probe at an adjacent position belong to a different probe group, the tester pre-stores a signal sampling time point set corresponding to a plurality of wafer models or different testers pre-store a signal sampling time point set corresponding to the same wafer model, and the wafer testing method comprises: According to the wafer model of the wafer to be tested, a corresponding signal sampling time point set is obtained from all signal sampling time point sets to obtain a target signal sampling time point set; In any test cycle, each of the probe groups is used as a target probe group in turn; Based on the target signal sampling time point set, control each probe in the target probe group to test the die at the corresponding position in the wafer to be tested, and obtain the test result of the target probe group; Each of the probe groups is traversed to obtain a test result of each probe group, and the test results of all the probe groups are used as the test results of a test cycle.

2. The wafer testing method according to claim 1, characterized in that: Each of the signal sampling time point sets includes an initial signal sampling time point and at least one backup signal sampling time point; The step of controlling each probe in the target probe group based on the target signal sampling time point set to test the die at the corresponding position in the wafer to be tested and obtaining the test result of the target probe group includes: Controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtaining an initial test result of each probe in the target probe group; For each probe in the target probe group, if the initial test result of the probe is pass, the probe is used as the first probe and pass is used as the final test result of the first probe, or, if the initial test result of the probe is fail, the probe is used as the second probe; Controlling each of the second probes to retest the bare die at a corresponding position in the wafer to be tested, and obtaining a final test result of each of the second probes; The final test results of all the first probes and the final test results of all the second probes in the target probe group are taken together as the test result of the target probe group.

3. The wafer testing method according to claim 2, characterized in that: The step of controlling each of the second probes to retest the die at the corresponding position in the wafer to be tested to obtain the final test result of each of the second probes includes: During the first retest, the initial signal sampling time point in the target signal sampling time point set is used as the target signal sampling time point, and each of the second probes is used as a probe to be processed; Controlling each of the probes to be processed to retest the bare die at the corresponding position in the wafer to be tested according to the target signal sampling time point, and obtaining a retest result of each of the probes to be processed; For each of the probes to be processed, if the retest result of the probe to be processed is passed, pass is used as the final test result of the second probe represented by the probe to be processed; If the retest result of the probe to be processed is failure and the current retest times have not reached the preset times, the probe to be processed continues to be used as the probe to be processed, and each of the probes to be processed is obtained, and a spare signal sampling time point is obtained from the target signal sampling time point set as a new target signal sampling time point, and then the step of controlling each probe to be processed is re-executed, and the bare die at the corresponding position in the wafer to be tested is retested according to the target signal sampling time point to obtain the retest result of each probe to be processed; If the retest result of the probe to be processed is failed and the current retest times reach the preset times, the failed is used as the final test result of the second probe represented by the probe to be processed, and the final test result of each second probe is obtained; wherein the preset times is greater than 1.

4. The wafer testing method according to claim 1, characterized in that: The signal sampling time point set corresponding to any wafer model is obtained in the following way: For any wafer model, determining a candidate range of signal sampling time points corresponding to the wafer model; An initial signal sampling time point and at least one spare signal sampling time point are selected from the candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and the at least one spare signal sampling time point, thereby obtaining a signal sampling time point set corresponding to the wafer model.

5. The wafer testing method according to claim 4, characterized in that: The step of determining a candidate range of signal sampling time points corresponding to the wafer model includes: The original range of signal sampling time points corresponding to the wafer model pre-stored in multiple testers is obtained, and the intersection is calculated based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

6. The wafer testing method according to claim 4, characterized in that: The step of determining a candidate range of signal sampling time points corresponding to the wafer model includes: The original ranges of signal sampling time points corresponding to the wafer model and multiple other wafer models pre-stored in the tester are obtained, and the intersection is calculated based on all the original ranges of signal sampling time points to obtain the candidate range of signal sampling time points corresponding to the wafer model.

7. The wafer testing method according to claim 4, characterized in that: The step of selecting an initial signal sampling time point and at least one spare signal sampling time point from the candidate range of signal sampling time points to obtain a set including the initial signal sampling time point and the at least one spare signal sampling time point comprises: Calculate an average value based on the lower limit value and the upper limit value of the candidate range of the signal sampling time point, and use the average value as the initial signal sampling time point; From the candidate range of signal sampling time points, a time point other than the initial signal sampling time point is selected as a backup signal sampling time point, and a set including the initial signal sampling time point and at least one backup signal sampling time point is obtained.

8. A wafer testing device, characterized in that: Applied to a tester, each probe in a probe card of the tester has a probe group to which it belongs, each probe and a probe at an adjacent position belong to a different probe group, the tester pre-stores a signal sampling time point set corresponding to a plurality of wafer models or different testers pre-store a signal sampling time point set corresponding to the same wafer model, and the wafer testing device comprises: An acquisition module is used to acquire a corresponding signal sampling time point set from all signal sampling time point sets according to the wafer model of the wafer to be tested, so as to obtain a target signal sampling time point set; A testing module, used for sequentially using each of the probe groups as a target probe group in any test cycle; Based on the target signal sampling time point set, control each probe in the target probe group to test the die at the corresponding position in the wafer to be tested, and obtain the test result of the target probe group; Each of the probe groups is traversed to obtain a test result of each probe group, and the test results of all the probe groups are used as the test results of a test cycle.

9. The wafer testing device according to claim 8, characterized in that: Each of the signal sampling time point sets includes an initial signal sampling time point and at least one spare signal sampling time point, and the test module is further used for: Controlling each probe in the target probe group to test the bare die at the corresponding position in the wafer to be tested according to the initial signal sampling time point in the target signal sampling time point set, and obtaining an initial test result of each probe in the target probe group; For each probe in the target probe group, if the initial test result of the probe is pass, the probe is used as the first probe and pass is used as the final test result of the first probe, or, if the initial test result of the probe is fail, the probe is used as the second probe; Controlling each of the second probes to retest the bare die at a corresponding position in the wafer to be tested, and obtaining a final test result of each of the second probes; The final test results of all the first probes and the final test results of all the second probes in the target probe group are taken together as the test result of the target probe group.

10. A storage medium, characterized in that: The storage medium stores a computer program, which, when executed by a processor, implements the wafer testing method according to any one of claims 1 to 7.

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