Microarchitecture performance analysis method and device, readable storage medium and program product

Abstract

The embodiment of the invention provides a micro-architecture performance analysis method and device, a readable storage medium and a program product, and relates to the technical field of computers, the method comprises the following steps: respectively collecting micro-architecture events generated when a micro-architecture executes each function of a predetermined application program; determining each predetermined performance index corresponding to each function based on a preset index evaluation model of the micro-architecture and the micro-architecture event corresponding to each function; and performing performance analysis according to each predetermined performance index to obtain a performance analysis result of each function running on the micro-architecture. According to the performance analysis method provided by the embodiment of the invention, the accuracy of a performance analysis result can be improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a micro-architecture performance analysis method, device, readable storage medium and program product. Background Art

[0002] Cloud computing service is a service model that provides computing resources through the Internet. Cloud servers are used to provide efficient, scalable, pay-as-you-go computing services based on cloud computing technology. Users expect to choose high-performance cloud servers, and the performance of cloud servers depends largely on their underlying hardware, especially the microarchitecture of the processor. Although the performance evaluation tools in the relevant technology can evaluate the overall running performance of the program in the microarchitecture, they are insufficient in accuracy, which affects the accuracy of the performance evaluation results of the microarchitecture. Summary of the invention

[0003] Embodiments of the present application provide a micro-architecture performance analysis method, device, readable storage medium, and program product to alleviate or solve one or more technical problems existing in the prior art.

[0004] In a first aspect, an embodiment of the present application provides a performance analysis method for a microarchitecture, comprising: separately collecting microarchitecture events generated by each function of a predetermined application executed by the microarchitecture; determining each predetermined performance indicator corresponding to each function based on a preset indicator evaluation model of the microarchitecture and the microarchitecture events corresponding to each function; performing performance analysis according to the predetermined performance indicators to obtain performance analysis results of each function running on the microarchitecture.

[0005] In a second aspect, an embodiment of the present application provides a performance analysis method for a microarchitecture, comprising: obtaining microarchitecture events generated by a first microarchitecture executing each function of a predetermined application, and using the method of the first aspect above to process the microarchitecture events generated by each function corresponding to the first microarchitecture to obtain a first result, wherein the first result is a performance analysis result of the functions running on the first microarchitecture; obtaining microarchitecture events generated by a second microarchitecture executing each function of the predetermined application, and using the performance analysis method of the first aspect above to process the microarchitecture events generated by each function corresponding to the second microarchitecture to obtain a second result, wherein the second result is a performance analysis result of the functions running on the second microarchitecture; wherein the first microarchitecture and the second microarchitecture are different types of processor microarchitectures; and determining a performance comparison result of the first microarchitecture and the second microarchitecture based on the first result and the second result.

[0006] In a third aspect, an embodiment of the present application provides an electronic device, including a memory, a processor, and a computer program stored in the memory, and the processor implements any method of the embodiment of the present application when executing the computer program.

[0007] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of any one of the embodiments of the present application is implemented.

[0008] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method of the embodiments of the present application when executed by a processor.

[0009] According to the performance analysis method of the microarchitecture of the embodiment of the present application, the microarchitecture events generated by the microarchitecture executing each function of the predetermined application program can be collected, and then based on the preset indicator evaluation model of the microarchitecture and the microarchitecture events corresponding to each function, the predetermined performance indicators corresponding to each function can be determined; thereby, performance analysis is performed according to each predetermined performance indicator to obtain performance analysis results of each function running on the microarchitecture.

[0010] The method of the present application collects micro-architecture events generated by each function of the predetermined application executed by the micro-architecture, and determines the predetermined performance indicators corresponding to each function based on the preset indicator evaluation model, which avoids the complexity of using multiple tools to collect events and evaluate performance indicators respectively. In addition, according to the method, performance analysis can be performed according to the predetermined performance indicators corresponding to each function, and the performance analysis results of each function running on the micro-architecture can be obtained, so as to realize the micro-architecture performance analysis at the function level, so that the performance analysis results can be refined to the granularity of the function level. In addition, the method of the present application can collect micro-architecture events corresponding to each specific function executed based on the execution of the predetermined application by the micro-architecture, instead of simply acquiring event-related information when a specific micro-architecture event occurs. Considering that each function is often called multiple times during the execution of the application, the method of the present application can obtain the micro-architecture events of each function more completely, and obtain more complete function execution information, which is conducive to better evaluating the execution of the function and improving the accuracy of the performance analysis results.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present application and should not be regarded as limiting the scope of the present application.

[0013] Figure 1 A flow chart of a micro-architecture performance analysis method according to an embodiment of the present application is shown.

[0014] Figure 2 A detailed flow chart of a micro-architecture performance analysis method according to an exemplary embodiment of the present application is shown.

[0015] Figure 3 A flowchart of a micro-architecture performance analysis method according to another embodiment of the present application is shown.

[0016] Figure 4 A schematic diagram of the structure of a performance analysis device for a micro-architecture shown in an embodiment of the present application is shown.

[0017] Figure 5 A schematic diagram of the structure of a micro-architecture performance analysis device shown in another embodiment of the present application is shown.

[0018] Figure 6 A block diagram of an electronic device provided by an embodiment of the present application is shown. DETAILED DESCRIPTION

[0019] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the concept or scope of the present application. Therefore, the drawings and descriptions are considered to be exemplary in nature and not restrictive.

[0020] To facilitate understanding of the technical solutions of the embodiments of the present application, the following describes the related technologies of the embodiments of the present application. The following related technologies can be combined with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application.

[0021] In cloud computing services, cloud service providers can integrate resources through pooling technology to centrally manage and dynamically allocate resources. Specifically, physical resources (such as servers, storage devices, network devices, etc.) are centralized through virtualization technology to form a shared resource pool to improve resource utilization and scalability and reduce the overhead of resource allocation and release. In addition, after integrating resources through pooling technology, cloud service providers can flexibly sell resources of different specifications to users. Resources of different specifications refer to computing resources of various configurations provided by cloud service providers based on parameters such as computing power, memory size, storage space, and network bandwidth. Elastic selling is a sales model that dynamically adjusts resource allocation and billing according to user needs. This model allows users to use and pay for the above computing power, storage space, and other resources on demand, thereby optimizing costs and improving flexibility. The elastic sale of these resources of different specifications to users can meet the resource usage needs in different scenarios. In other words, users usually expect to choose a cloud server that can run a certain application with higher performance. To achieve this goal, users are often required to have the ability to comprehensively evaluate the execution efficiency of programs on different cloud servers, select cloud servers with great optimization potential, and perform corresponding customized optimization.

[0022] In actual scenarios, the performance of cloud servers depends largely on their underlying hardware, especially the microarchitecture of the processor. Therefore, evaluating the execution efficiency of applications on different cloud servers also depends on the performance evaluation results of the microarchitecture. For most developers, the performance evaluation of microarchitectures needs to be completed based on existing performance tools. In related technologies, from the two dimensions of professionalism and versatility, the more professional the tool, the poorer the versatility, which makes it impossible to use it uniformly across multiple platforms, making it difficult to unify the analysis across platforms. Universal tools that can be evaluated and compared horizontally on multiple platforms can often only cover some macro indicators, and such indicators are difficult to provide specific guidance for the performance evaluation and optimization of microarchitectures. Therefore, developers usually need to rely on their personal understanding to seek multiple tools to help with microarchitecture performance evaluation, which makes the performance evaluation process complicated and lengthy, and the applicability of different performance evaluation tools is unclear. If developers do not understand the scope of application of the tool, they may use the tool incorrectly, thereby obtaining inaccurate or irrelevant performance data, which easily leads to poor reliability of the evaluation results.

[0023] In the related art, a performance analysis tool (linuxperf) of a performance counter can be used in an open source system (Linux) to perform performance analysis of a microframework. The performance counter is a kernel-based subsystem that can provide a performance analysis framework and use a performance monitoring unit (PMU), a tracing tool, and counters in the kernel to perform performance analysis. The performance monitoring unit contains a set of event counters that are used to track and count low-level hardware events in the system, the tracing tool is used to capture microarchitecture events, and the counters are used to count microarchitecture events.

[0024] The performance analysis tool can read the hardware events detected by the performance detection unit in two ways. One way is to read the microarchitecture event count at the moment of program start and end, and record the difference in the number of occurrences of the microarchitecture event during this period. The other way is to read the microarchitecture event count at regular intervals, and the reading timing depends on the timing of the overflow interrupt generated by the microarchitecture event count, which is issued after the microarchitecture event count reaches a fixed threshold.

[0025] It can be seen that the performance analysis tool can only determine the performance bottleneck at the program level, and cannot collect statistics on the execution information at the function level, so it cannot determine the performance bottleneck at the function level, and it is difficult to guide developers to optimize the program more deeply. In addition, the performance analysis tool can only focus on a single performance evaluation indicator, and cannot jointly process multiple performance evaluation indicators. It is difficult for developers to understand the specific execution efficiency of the function through the micro-architecture analysis method.

[0026] In the related art, a specific microarchitecture can provide multiple microarchitecture events that can be collected through a performance detection unit. However, it is very difficult to select truly useful events from these numerous events for analysis. This usually requires a deep understanding of the microarchitecture design and the usage specifications of the performance detection unit to obtain useful information from the numerous original collected microarchitecture event data.

[0027] It should be noted that the above application scenarios or application examples provided in the embodiments of the present application are for ease of understanding, and the embodiments of the present application do not specifically limit the application of the technical solution. In addition, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0028] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The several specific embodiments listed can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0029] Figure 1 A flow chart of a method for analyzing the performance of a micro-architecture according to an embodiment of the present application is shown. Figure 1 As shown, the method may include the following steps S101-S103.

[0030] S101 , respectively collecting micro-architecture events generated by the micro-architecture executing each function of a predetermined application program.

[0031] S102, determining predetermined performance indicators corresponding to each function based on a preset indicator evaluation model of the micro-architecture and micro-architecture events corresponding to each function.

[0032] S103, performing performance analysis according to each predetermined performance indicator to obtain a performance analysis result of each function running on the micro-architecture.

[0033] According to the performance analysis method of the micro-architecture of the embodiment of the present application, the micro-architecture events generated by the micro-architecture executing each function of the predetermined application can be collected, and then the predetermined performance indicators corresponding to each function can be determined based on the preset indicator evaluation model of the micro-architecture and the micro-architecture events corresponding to each function; thereby, the performance analysis is performed according to each predetermined performance indicator, and the performance analysis results of each function running on the micro-architecture are obtained. Compared with the need to use a variety of performance evaluation tools in the related art, the method of the present application can directly collect the micro-architecture events generated by the micro-architecture executing each function of the predetermined application, and determine the predetermined performance indicators corresponding to each function based on the preset indicator evaluation model, which avoids the complexity of using multiple tools to collect events and evaluate performance indicators respectively. In addition, according to this method, performance analysis can be performed according to the predetermined performance indicators corresponding to each function, and the performance analysis results of each function running on the micro-architecture can be obtained, so as to realize the micro-architecture performance analysis at the function level, so that the performance analysis results can be refined to the granularity of the function level. Furthermore, the method of the present application can collect microarchitecture events corresponding to each specific executed function based on the execution of a predetermined application by the microarchitecture, rather than simply obtaining event-related information when a specific microarchitecture event occurs. Considering that each function is often called multiple times during the execution of the application, the method of the present application can more completely obtain the microarchitecture events of each function and obtain more complete function execution information, which is conducive to better evaluating the execution of the function and improving the accuracy of the performance analysis results.

[0034] In step S101, microarchitecture events are hardware events defined and tracked by a performance detection unit. These events are used to detect and analyze various performance indicators and behaviors of the processor when executing various functions included in a predetermined application. In some scenarios, the performance detection unit can also be called a hardware performance counter.

[0035] Exemplarily, microarchitecture events include, but are not limited to, at least one of the following hardware events: instruction-related events, cache-related events, clock cycle-related events, and floating-point operation-related events. Specifically, instruction-related events may include, for example, events such as the total number of instructions executed and the number of branch instructions. Cache-related events may include, for example, events such as the number of cache accesses, the number of cache hits and misses. Clock cycle-related events may include, for example, events such as the number of processor clock cycles and the number of instruction execution cycles. Floating-point operation-related events may include, for example, events such as the number of executions of floating-point operation instructions and the throughput of floating-point operations.

[0036] From the above specific examples of micro-architecture events, it can be seen that micro-architecture events are dynamically generated and reflect the usage of hardware resources by the corresponding functions during execution. Therefore, micro-architecture events can be collected during the execution of each function of a predetermined application.

[0037] In the above step S101, the micro-architecture events may include multiple collection methods. For example, the micro-architecture events corresponding to each function may be periodically collected according to a predetermined collection period. For example, the micro-architecture events corresponding to each function may be collected within a specific time period. For another example, these micro-architecture events may be continuously collected during the operation of a predetermined application.

[0038] In some embodiments, step S101 may specifically include the following steps: identifying the microarchitecture that executes the predetermined application based on the operating environment information of the predetermined application; collecting microarchitecture events according to a predetermined collection period to obtain at least one set of call stack information, any set of call stack information containing at least one piece of collection information, and any piece of collection information is used to indicate: any function executed by the microarchitecture and the microarchitecture event generated by the execution function; wherein the microarchitecture events collected corresponding to different microarchitectures are at least partially different.

[0039] Specifically, the operating environment information refers to the various conditions required for the operation of the predetermined application, such as hardware environment information and software environment information. Microarchitecture, also known as processor architecture or microprocessor architecture, is the specific implementation method and structural design inside the processor. Microarchitecture can be used to define how the processor executes instructions, processes data, and interacts with other system components.

[0040] Exemplarily, when the micro-architecture is identified, it mainly depends on the hardware environment information required for the predetermined application to run. The hardware environment information includes, for example, the model and specification of the processor. The micro-architecture identification process includes, for example, the following steps: obtaining the model and specification of the processor through a system command or a third-party tool, and determining the corresponding micro-architecture through the obtained model and specification of the processor.

[0041] For example, in an open source operating system (Linux system), detailed information about the processor can be displayed by using a command (lscpu command) for displaying processor-related information. For another example, detailed information about the processor can be obtained by calling a third-party hardware detection tool. The detailed information about the processor includes at least information such as the model and specifications of the processor.

[0042] It should be understood that the above-mentioned system commands and third-party tools are merely schematic illustrations. When identifying a micro-architecture, the specific system commands or third-party tools used can be selected according to actual needs, and the embodiments of the present application are not specifically limited. In the embodiments of the present application, the predetermined application (system or software) can be compatible and run on a variety of different micro-architectures, with high flexibility and compatibility. Different micro-architectures can be understood as different types of micro-architectures or different types of processor architectures. In some scenarios, the micro-architectures provided by different micro-architecture manufacturers are also referred to as micro-architectures for different platforms. The types of these processors differ in instruction sets, performance characteristics, power consumption, etc. Exemplarily, different server chip manufacturers can provide different micro-architectures. Alternatively, the same server chip manufacturer can provide different micro-architectures.

[0043] In step S101, illustratively, the predetermined acquisition period may be a predetermined time interval or a predetermined number of events. For example, an acquisition is performed when a certain time interval is reached, or an acquisition is performed after a certain number of events are reached. The acquisition performed at the predetermined time interval is simple to operate and easy to implement. The acquisition performed according to the predetermined number of events is conducive to more accurately capturing the frequency of occurrence of specific events, so that the impact of the detected specific events on the performance of the micro-architecture can be better understood.

[0044] In actual application scenarios, the implementation method of the predetermined collection period can be selected according to specific detection requirements, and the embodiments of the present application do not make specific limitations.

[0045] Exemplarily, a call stack is a data structure used to store function call information during program execution. In an embodiment of the present application, the call stack information is used to record the collection information of micro-architecture events. The collection information can not only record the functions executed by the micro-architecture, but also include the micro-architecture events generated by the executed functions.

[0046] In this embodiment, the micro-architecture can be automatically identified and the corresponding performance analysis can be performed based on the operating environment information of the application, so that the performance analysis method can be applicable to different micro-architectures. Compared with the need to use multiple performance evaluation tools in the related art, the method of the present application is conducive to providing corresponding performance analysis methods for different micro-architectures, improving the compatibility of the performance analysis method between different micro-architectures, and reducing the complexity of the performance evaluation method. In addition, a micro-architecture event is collected once according to a predetermined collection cycle, and a group of call stack information can be obtained. Each group of call stack information is saved as metadata, that is, each group of call stack information can be saved in a file or database in a structured format. The collection information in each group of call stack information is used as metadata to achieve structured storage, which is convenient for the management and query of each group of call stack information after the collection cycle ends, so as to meet the performance analysis requirements of the micro-architecture.

[0047] In some embodiments, the above-mentioned step S102 may specifically include: based on each group of call stack information, counting the micro-architecture events corresponding to each function, and obtaining the number of occurrences of the micro-architecture events corresponding to each function; based on a preset indicator evaluation model and the number of occurrences of the micro-architecture events corresponding to each function, determining each predetermined performance indicator corresponding to each function.

[0048] Exemplarily, for any set of call stack information, any piece of collection information in the set of call stack information is obtained, and according to the function indicated by the collection information and the micro-architecture event generated by executing the corresponding function, the micro-architecture event count is accumulated to the corresponding function. After the above-mentioned micro-architecture event count accumulation process is performed on each set of call stack information, the number of occurrences of the micro-architecture events corresponding to each function of the predetermined application can be obtained.

[0049] For example, since different micro-architectures have different structural designs and optimization goals in actual application scenarios, when performing performance analysis on different micro-architectures, the preset indicator evaluation models and the collected micro-architecture events are also different.

[0050] Among them, the preset indicator evaluation model is used to indicate: the correspondence between each predetermined performance indicator and the number of occurrences of the micro-architecture event corresponding to each function. The preset indicator evaluation model may include multiple sub-models. Any sub-model may correspond to a predetermined performance indicator. Specifically, any sub-model may be used to indicate: the correlation between a predetermined performance indicator and the number of occurrences of the corresponding micro-architecture event.

[0051] For example, for any sub-model, the association relationship can be expressed as a calculation expression or an algorithm model. The calculation expression is an indicator calculation formula, and the algorithm model can be a nonlinear association relationship between the predetermined performance indicator and the number of occurrences of the corresponding micro-architecture event learned in advance through training data.

[0052] Specifically, for any predetermined performance indicator, when the correlation relationship indicated by the corresponding sub-model is an expression, the expression includes at least the following components: output, input and weight. Among them, the output is: the indicator value of the predetermined performance indicator. The input is: the number of occurrences of at least one micro-architecture event that needs to be collected corresponding to the preset predetermined performance indicator, and the weight is: the corresponding weight coefficient of each micro-architecture event, and each weight system is used to indicate the degree of influence of the corresponding micro-architecture event on the predetermined performance indicator. For example, the larger the coefficient value, the higher the degree of influence. The weight coefficient can be obtained, for example, through experience or experiment.

[0053] In some scenarios, the expression may also include a constant term to represent the baseline performance when no microarchitectural event occurs. For example, a constant term of zero indicates that when no microarchitectural event occurs, the index value of the predetermined performance index is zero. When the constant term is a non-zero value, it indicates that even if no microarchitectural event occurs, the microarchitecture has a certain basic performance.

[0054] Specifically, for any predetermined performance indicator, when the association relationship indicated by the corresponding sub-model is an algorithm model, the model can be trained in the following manner. First, training data collection is performed. Specifically, data samples containing the index value of the predetermined performance indicator and related micro-architecture events are collected. These data can be generated by actually running an application or a simulator. For the index value of the micro-architecture event and the predetermined performance indicator, for example, it can be collected by at least one method such as a performance monitoring interface provided by the operating system, kernel programming, etc., which is not specifically limited here. Secondly, a model type is selected. The model type can be, for example, a polynomial regression model, a neural network model, a support vector machine, etc., which can be set according to actual needs, and the embodiment of the present application is not specifically limited. Then, model training is performed. Specifically, the training data is used to fit the nonlinear model, and the model parameters are adjusted by an optimization algorithm (such as gradient descent) to minimize the prediction error. The prediction error is the difference between the model prediction value and the actual value. By adjusting the model parameters, the difference value is gradually reduced. When the difference value is less than or equal to the predetermined difference threshold, or the number of model training times reaches the preset number threshold, the model training is stopped to obtain the trained model.

[0055] In an embodiment of the present application, the sub-model of each predetermined performance indicator can be a calculation expression or a pre-trained algorithm model. The calculation expression or algorithm model can help quantify the impact of micro-architecture events on performance indicators, thereby providing a basis for performance evaluation.

[0056] Exemplarily, each predetermined performance indicator includes at least one of the following performance indicators: frontend bound, backend bound, bad speculation, and retiring.

[0057] Specifically, the predetermined application can be understood as software consisting of a series of instructions. The performance indicator "front-end limited" is used to describe the situation in which the performance is limited due to insufficient performance of the processor front end (ie, instruction fetch and decoding stage) during the processing of the predetermined application.

[0058] The performance metric "backend limited" is used to describe the performance bottleneck caused by insufficient resources on the back end of the processor.

[0059] The performance metric "misprediction" is used to describe the performance loss caused by the processor making an incorrect prediction. For example, when the processor encounters a conditional branch, it will try to predict the direction of the branch. If the prediction is wrong, the processor needs to discard the instructions on the wrong branch and start again from the correct branch. This will cause the processing flow to pause, which can easily cause a waste of the processor's execution resources.

[0060] The performance indicator "commit" is used to describe the result of the processor's instruction execution being written to the register or memory, which means that the instruction execution of the processor has entered the final completion stage. If most of the instructions of an application (the number of corresponding instructions in the total number of instructions contained in the application exceeds the predetermined ratio threshold) can smoothly enter the submission stage, it means that the execution efficiency of the application is high.

[0061] In some embodiments, the above-mentioned predetermined performance indicators are microarchitecture performance indicators based on the top-down microarchitecture analysis method. This analysis method uses a top-down analysis framework, which can selectively analyze the performance bottlenecks of the microframework. In this top-down analysis framework, the microarchitecture performance indicators are divided into levels. In each level, the first level includes the four performance indicators of front-end limitation, back-end limitation, misprediction and submission described in the above embodiment. The performance indicators of the first level can be further divided. Taking the performance indicator "front-end limitation" as an example, this indicator can be divided into two sub-performance indicators: delay (Fetch Latency) and bandwidth (Fetch Bandwidth).

[0062] In an embodiment of the present application, different types of microarchitectures can be used for performance analysis based on a top-down microarchitecture analysis method. The difference is that, for the same performance indicator, each sub-model in the preset indicator evaluation model used and each sub-model corresponding to the microarchitecture events that need to be collected are at least partially different. For example, the same performance indicator can correspond to different calculation expressions in different microarchitectures, and the calculation expressions are supported by different microarchitecture events.

[0063] For example, any sub-model may correspond to a predetermined performance indicator. Assume that a certain performance indicator of the first layer can be represented as Y1. Among the multiple sub-models included in the preset indicator evaluation model, the sub-model corresponding to the performance indicator Y1 can be represented as: Y1=K1*A1+K2*A2+…+Kn*An, where n is an integer greater than or equal to 1.

[0064] In this expression, A1, A2, ..., An can represent the collected microarchitecture events, and the collected microarchitecture events corresponding to different microarchitectures are at least partially different. K1, K2, ..., Kn are weight coefficients corresponding to each microarchitecture event in the submodel. Even if the same microarchitecture event is used in the submodel of the same predetermined performance indicator between different microarchitectures, the weight coefficients of the same microarchitecture event may be different.

[0065] In the embodiments of the present application, different types of micro-architecture designs have differences in hardware design. The specific implementation of the hardware design includes but is not limited to at least one of the following: cache structure, memory structure, number of execution units, type of execution units, and network structure.

[0066] Taking cache structure as an example, different microarchitectures may use caches with different storage capacities, which will affect the definition of cache-related microarchitecture events. For example, microarchitecture caches can be divided into small cache designs and large cache designs. Small cache design refers to caches with smaller capacity, such as L1 cache. The storage capacity of L1 cache ranges from 128 kilobytes (KB) to 2 megabytes (MB). Cache design refers to caches with larger capacity. For example, L2 cache and L3 cache. The storage capacity of L2 cache ranges from 256 kilobytes to 32 megabytes. The storage capacity of L3 cache ranges from 1 megabyte to 128 megabytes.

[0067] If a microarchitecture cache adopts a small cache design, the cache miss rate may be higher, and the microarchitecture events that need to be collected include cache miss events, which can be used to evaluate the performance evaluation indicator of "front-end limitation". If a microarchitecture cache adopts a large cache design, the cache miss events may be fewer, but the cache access latency has a greater impact on performance. The microarchitecture events that need to be collected include but are not limited to at least one of the following: cache hit rate time, cache line utilization events, these events can be used to evaluate cache efficiency, and these events are usually related to the performance indicator "back-end limitation", and specifically belong to the "memory limitation" category in the performance indicator "back-end limitation".

[0068] Taking the memory structure as an example, the memory structure includes unified memory architecture and heterogeneous memory architecture. Unified memory architecture means that memory resources are managed uniformly and each processing unit shares the same memory. Heterogeneous memory architecture means that different types of processing units have their own memory.

[0069] For a unified memory architecture, since all processing units share the same memory, all memory access latencies are relatively low, but since the bandwidth is shared by all processing units, bandwidth bottlenecks are prone to occur. Therefore, it is necessary to collect micro-architectural events such as memory access latency, memory bandwidth utilization, and the number of memory method conflicts. For a heterogeneous memory architecture, its characteristics are: the access latency of different types of memory varies greatly, and optimization is required to reduce latency. In addition, the bandwidth of different types of memory may be different, and it needs to be reasonably allocated to improve efficiency. Therefore, it is necessary to collect micro-architectural events such as the access latency of different types of memory, the bandwidth utilization of different types of memory, and the number of memory page migrations. The number of memory page migrations is used to record the number of migrations of memory pages between different types of memory.

[0070] It can be seen from the above examples that due to differences in hardware design, different types of microarchitectures require at least partially different microarchitecture events to be collected when evaluating predetermined performance indicators. For example, the microarchitecture events required to be collected by different types of microarchitectures may be completely different (refer to the above description using the cache structure as an example), or may be partially different (refer to the above description using the memory structure as an example), and the embodiments of the present application do not make specific limitations.

[0071] In the embodiment of the present application, for different types of micro-architectures, the preset indicator evaluation model of the micro-architecture and the micro-architecture events that need to be collected can be obtained by looking up the table. However, for any type of micro-architecture, the preset indicator evaluation model and the micro-architecture events that need to be collected in the table are not subjectively set, but are based on objective data and scientific methods.

[0072] Exemplarily, first, the specific characteristics of different types of micro-architecture designs can be obtained by querying the hardware design documents. Secondly, by running the same benchmark program on different micro-architectures, for any micro-architecture, the micro-architecture events and performance index data collected during the running of the benchmark program are collected. According to the experimental results, determine which micro-architecture events are most correlated with specific performance indicators. During the experiment, the performance monitoring interface provided by the operating system, kernel programming, and other methods can be used to collect micro-architecture events and performance index data. The collection method can be selected according to actual needs, and the embodiment of the present application is not specifically limited. Again, regression analysis, machine learning, and other methods are used to fit the corresponding relationship between different sub-models and micro-architecture events (which can be a calculation expression or a model) according to the collected data to ensure the objectivity of the corresponding relationship. Then, methods such as cross-validation are used to verify the accuracy and reliability of the model. Among them, the benchmark program is a special program for testing hardware performance, which can be customized according to actual needs. Cross-validation refers to dividing the data set into a training set and a test set. Train the model or fit the calculation expression on the training set, and verify the accuracy of the model on the test set.

[0073] The embodiments of the present application can ensure the accuracy of the correspondence between performance indicators and micro-architecture events under different micro-architecture designs through specific implementation means, such as hardware document analysis, experimental verification, model fitting, etc. This method is not only based on the characteristics of hardware design, but also verified by experimental data, and more accurately reflects the correspondence between each predetermined performance indicator and micro-architecture event on different types of micro-architectures, and has high objectivity and adaptability.

[0074] It should be noted that the expressions of the sub-models corresponding to the above performance indicators are only schematic illustrations. In actual scenarios, the preset indicator evaluation model and the sub-models it contains can have multiple expressions, which can be linear models, nonlinear models, or hybrid models of linear and nonlinear. Specifically, specific corresponding preset indicator evaluation models and micro-architecture events to be collected can be designed for different micro-architectures according to actual conditions, and the embodiments of the present application do not make specific limitations.

[0075] In the top-down micro-architecture analysis method adopted by the micro-architecture of the embodiment of the present application, different preset index evaluation models can be designed in advance for different micro-architectures, and the micro-architecture includes one or more predetermined performance indicators, and any predetermined performance indicator can correspond to a sub-model in the preset index evaluation model. For the same predetermined performance indicator of different micro-architectures, the sub-models corresponding to the predetermined performance indicator can be different, and the corresponding micro-architecture events that need to be collected in the sub-model can be different. According to the method of the embodiment of the present application, the preset index evaluation model designed for different micro-architectures makes the performance analysis more accurate and targeted, and can fully consider the characteristics and differences of various micro-architectures, avoiding a one-size-fits-all analysis method. And, between different micro-architectures, the sub-models corresponding to the same predetermined performance indicator and the micro-architecture events that need to be collected can be different, and this flexibility is conducive to providing rich data support for the performance analysis of different micro-architectures.

[0076] Specifically, after determining the sub-model corresponding to any predetermined performance indicator in each micro-architecture and the micro-architecture events that need to be collected according to the above-mentioned embodiment, a corresponding relationship set can be established, such as a data table, and the data items in the data table include: a micro-architecture identifier, each predetermined performance indicator, that is, the corresponding sub-model, and a list of micro-architecture events that need to be collected. Among them, the micro-architecture identifier is used to indicate the micro-architecture, which can be a micro-architecture name or a micro-architecture type, and the embodiments of the present application do not make specific limitations. The list of micro-architecture events that need to be collected is a micro-architecture event set, which contains all the micro-architecture events that need to be collected for the corresponding micro-architecture. After identifying the micro-architecture, the table can be looked up to obtain the sub-models corresponding to each predetermined performance indicator of the micro-architecture and the micro-architecture events that need to be collected.

[0077] In some embodiments, the above-mentioned step of counting the microarchitecture events corresponding to each function based on each group of call stack information to obtain the number of occurrences of the microarchitecture events corresponding to each function can specifically include: generating a call relationship tree using the function call relationship of each function, the attribute information of any leaf node in the call relationship tree includes: the function name of any function and the number of occurrences of the corresponding microarchitecture event; for any function indicated by any piece of collection information and the indicated microarchitecture event, the number of occurrences of the microarchitecture event is added to the target leaf node, and the target leaf node is the leaf node where the function is located; summarizing the number of occurrences of the microarchitecture events accumulated at each leaf node to obtain the number of occurrences of the microarchitecture events corresponding to each function.

[0078] Exemplarily, any piece of collected information included in the call stack information can be used to indicate: any function executed by the microarchitecture, the microarchitecture event generated by executing the function, and the function call relationship of the function. The function call relationship is used to indicate: the calling and called relationship between any function and other functions.

[0079] Exemplarily, the call relationship tree is a tree structure used to represent the hierarchical relationship of function calls. The root node of the tree can be the entry function of a predetermined application, and other nodes represent functions that are called in sequence starting from the entry function. In the call relationship tree, each leaf node represents a function, and the edge represents the call relationship between functions, from the caller to the callee. The hierarchical structure of the tree is used to indicate the nested relationship of function calls, for example, a child node represents a function called by its parent node.

[0080] In this embodiment, for each piece of collected information contained in any group of call stack information, the function call relationship of each function is obtained from each piece of collected information, and a complete call relationship tree is established based on the function call relationship of each function, that is, a tree model can be used to model the function call relationship of the entire predetermined application program, and the call relationship tree helps to clearly display the call hierarchy and structure between functions. Accumulating the number of occurrences of micro-architecture events to the target leaf node is conducive to accurately counting the micro-architecture events generated by the execution of each function by the micro-architecture. After summarizing the number of occurrences of micro-architecture events of each leaf node, the number of occurrences of micro-architecture events corresponding to each function can be obtained, and the subsequent calculation of each predetermined performance indicator corresponding to each function provides accurate data support, realizing function-level micro-architecture performance evaluation. In addition, it is possible to combine multiple predetermined performance indicators of a function to dig out more function execution information, such as micro-architecture events during function execution, so as to perform multi-faceted performance evaluation of the micro-architecture.

[0081] In some embodiments, the above-mentioned step of determining each predetermined performance indicator corresponding to each function based on the preset indicator evaluation model and the number of occurrences of the micro-architecture events corresponding to each function may specifically include: obtaining each sub-model in the preset indicator evaluation model, any sub-model is used to indicate the correlation between any performance indicator and the number of occurrences of the corresponding micro-architecture event; for any function, based on the number of occurrences of the micro-architecture event corresponding to the function and the correlation indicated by each sub-model, calculate the predetermined performance indicators corresponding to the function.

[0082] Exemplarily, the attribute information of the leaf node corresponding to the function may also include: at least one predetermined performance indicator corresponding to the function, each predetermined performance indicator corresponding to a sub-model in the preset indicator evaluation model. After the number of occurrences of the micro-architecture event is accumulated to the leaf node of the corresponding function, the number of occurrences of the micro-architecture event corresponding to each function can be obtained.

[0083] In this embodiment, each sub-model can be used to calculate a predetermined performance indicator. Each sub-model can accurately indicate the correlation between each predetermined performance indicator and the corresponding micro-architecture event. For any function, based on the number of occurrences of the corresponding micro-architecture event and the correlation indicated by the sub-model, the index value of each predetermined performance indicator corresponding to the function can be accurately obtained, thereby achieving quantitative evaluation of the function performance.

[0084] In some embodiments, before the above-mentioned step S101, the method also includes: obtaining a preset correspondence set, any correspondence in the correspondence set is used to indicate: the correspondence information between the microarchitecture and the indicator evaluation model and at least one microarchitecture event; taking the identified microarchitecture as the target microarchitecture, and obtaining the indicator evaluation model and at least one corresponding microarchitecture event corresponding to the target microarchitecture from the correspondence set as the preset indicator evaluation model and each microarchitecture event of the target microarchitecture.

[0085] Exemplarily, the correspondence set can be in the form of a data table such as a "micro-architecture indicator set table" or in the form of a knowledge base. By managing the correspondence between different micro-architectures and indicator evaluation models and micro-architecture events through a preset correspondence set, it is helpful to quickly query and obtain the indicator evaluation model and micro-architecture events required to evaluate the performance of the micro-architecture based on the identified micro-architecture, thereby facilitating the provision of corresponding performance analysis methods for different micro-architectures and improving the compatibility of performance analysis methods between different micro-architectures.

[0086] In this embodiment, through automatic identification of the microarchitecture, the corresponding microarchitecture events preset for the microarchitecture and the preset indicator evaluation model of the microarchitecture can be obtained from the corresponding relationship set according to the identified microarchitecture. The preset indicator evaluation model, for example, includes indicator calculation formulas corresponding to each predetermined performance indicator. The calculation of each predetermined performance indicator of the microarchitecture is implemented through these formulas, providing a data basis for subsequent microarchitecture performance analysis.

[0087] In some embodiments, in step S103, according to the predetermined performance indicators corresponding to the functions, a variety of performance analysis methods can be used to obtain performance analysis results of the functions running on the micro-architecture.

[0088] For example, a single indicator anomaly detection may be performed. Specifically, for any function, when any predetermined performance indicator of the function is abnormal, the function performance may be determined to be abnormal. For example, a multi-indicator comprehensive analysis may be performed. Specifically, for any function, when the indicator values ​​of at least two predetermined performance indicators of the function are abnormal, the function performance may be determined to be abnormal. For another example, the predetermined performance indicators of a specified function that are of particular interest may be analyzed. When the indicator value of any predetermined performance indicator of a specified function that is of particular interest is abnormal, the function performance may be determined to be abnormal.

[0089] Among them, the designated functions include but are not limited to: functions that are called multiple times in a predetermined application (exceeding a predetermined call count threshold) or functions with high computational complexity (the number of instruction executions exceeds a number threshold, and / or the function execution time exceeds an execution time threshold, etc.). For functions that are called multiple times, the predetermined performance indicators that are focused on include, for example, execution time and cache hit rate; for functions with high computational complexity, the predetermined performance indicators that are focused on include, for example, the number of instruction executions and branch prediction failure rate. The specific setting can be based on actual needs, and the embodiments of the present application do not make specific limitations.

[0090] After the above performance analysis is performed, a performance analysis result may be generated according to the function with abnormal performance and the corresponding function value. The performance analysis result may include at least one of the following items: the function name of the function, the predetermined performance index with abnormality and the corresponding index value.

[0091] In some embodiments, the above-mentioned step S103 may specifically include the following steps: for any function among the functions, when at least one performance indicator corresponding to the function meets the abnormal condition, it is determined that there is a performance abnormality in the operation of the function, and the abnormal condition is used to indicate: the corresponding performance indicator belongs to the preset value range when there is a performance abnormality; the function judged to have a performance abnormality is regarded as a problem function, and each performance indicator corresponding to the problem function that meets the abnormal condition is regarded as a problem performance indicator; and the performance analysis result corresponding to the function is generated according to the problem function and the problem performance indicator.

[0092] Specifically, the performance analysis results can be generated in the form of display information or document form. The specific content of the performance analysis results includes at least: the function name of the problem function, the specific value of the problem performance indicator. In some scenarios, the specific content of the performance analysis results may also include: the normal range of the indicator value, which is used to indicate the predetermined normal value range or expected value range of the problem performance indicator. In some scenarios, the performance analysis results can be intuitively displayed in the form of charts, tables, etc. The specific implementation form of the performance analysis results can be determined according to the actual situation. The embodiments of the present application are not specifically limited.

[0093] In this embodiment, if a performance indicator of a function of a predetermined application is abnormal, the function and abnormal indicator with performance abnormality can be determined during operation. This is conducive to clearly identifying the problem function and its corresponding problem performance indicator, thereby helping developers to quickly locate the root cause of the problem and perform performance optimization and debugging in a targeted manner.

[0094] In some embodiments, after generating the performance analysis results corresponding to the function according to the problem function and the problem performance indicator, the following steps are also included: obtaining any performance indicator among the problem performance indicators as the current indicator, and obtaining the next layer indicator of the current indicator, the next layer indicator including the sub-performance indicators obtained by pre-dividing the current indicator; determining the sub-performance indicators of the microarchitecture based on the new indicator evaluation model and the new microarchitecture event, the new indicator evaluation model is used to indicate: the correlation between each sub-performance indicator and the number of occurrences of the corresponding new microarchitecture event; when at least one sub-performance indicator meets the abnormal condition, the sub-performance indicators that meet the abnormal condition are used as new problem performance indicators, and any performance indicator among the new problem performance indicators is used as the new current indicator, starting from the step of obtaining the next layer indicator of the current indicator, and executing in a loop until a stop processing instruction is received or the number of sub-performance indicators contained in the next layer indicator of the new current indicator is zero, and the performance analysis processing of the microarchitecture is stopped.

[0095] Exemplarily, the new indicator evaluation model and the corresponding at least one micro-architecture event can be queried from the corresponding relationship set described in the above embodiment. Assuming that the front-end limited performance indicator includes two sub-performance indicators, namely, latency and bandwidth, if the front-end limited performance indicator of a function is abnormal, in order to further locate the problem, the sub-performance indicators can be calculated based on the new indicator evaluation model and the new micro-architecture events corresponding to each function.

[0096] Exemplarily, assuming that the current indicator is already the last level indicator, or, in the process of executing the performance analysis method of the micro-architecture, in response to a received stop processing instruction, the performance analysis processing of the micro-architecture is stopped.

[0097] In this embodiment, by analyzing the micro-architecture performance indicators layer by layer, potential performance problems can be clearly discovered, ensuring the comprehensiveness and depth of the analysis process. The method of performing performance analysis layer by layer makes the performance evaluation more targeted, can quickly locate the key performance bottleneck, and provides a clear direction and basis for performance optimization based on the performance evaluation results.

[0098] According to the performance analysis method of the micro-architecture of the embodiment of the present application, the micro-architecture can be automatically identified and the corresponding performance analysis can be performed according to the operating environment information of the application, so that the performance analysis method can be applied to different micro-architectures. Compared with the need to use multiple performance evaluation tools in the related art, the method of the present application is conducive to providing corresponding performance analysis methods for different micro-architectures, improving the compatibility of the performance analysis method between different micro-architectures, and reducing the complexity of the performance evaluation method. In addition, according to the method, performance analysis can be performed according to each predetermined performance indicator corresponding to each function, and the performance analysis results of each function running on the micro-architecture are obtained, so as to realize the micro-architecture performance analysis at the function level, and refine the performance analysis results to the granularity of the function level, thereby facilitating the improvement of the accuracy and reliability of the performance analysis results.

[0099] Figure 2 FIG. 4 shows a detailed flow chart of a performance analysis method of a micro-architecture according to an exemplary embodiment of the present application. Figure 2 As shown, the method includes the following steps.

[0100] S201, microarchitecture identification.

[0101] In this step, the micro-architecture of the predetermined application may be identified and processed according to the operating environment information of the predetermined application.

[0102] S202, micro-architecture index table lookup.

[0103] In this step, the preset indicator evaluation model of the micro-architecture and the micro-architecture events that need to be collected can be obtained by looking up the table according to the identified micro-architecture. Specifically, the preset indicator evaluation model that can be obtained by looking up the table may include multiple sub-models. The micro-architecture events that need to be collected are a micro-architecture event list, which contains all the micro-architecture events that need to be collected for the corresponding micro-architecture. The data table looked up in this step is the data table established after determining the sub-model corresponding to any predetermined performance indicator in each micro-architecture and the micro-architecture events that need to be collected in the above embodiment. I will not go into details here.

[0104] For example, Figure 2 As shown, step S202 may specifically include the following steps.

[0105] S11, obtaining a micro-architecture indicator set table.

[0106] Exemplarily, the micro-architecture indicator set table is the correspondence set in the above-mentioned embodiments of the present application, which is used to indicate the correspondence between different micro-architectures and indicator evaluation models and micro-architecture events.

[0107] S12, multi-type architecture lookup table.

[0108] In this step, the identified microarchitecture is used to obtain the corresponding indicator evaluation model and the microarchitecture events to be collected from the microarchitecture indicator set table. Different microarchitectures correspond to different indicator evaluation models and at least partially different microarchitecture events. For example, Figure 2 As shown, the indicator evaluation model can be an indicator calculation formula, and different indicator calculation formulas are supported by different micro-architecture events.

[0109] like Figure 2 As shown in the schematic diagram of different types of micro-architectures "Architecture 1, Architecture 2 and Architecture 3" and the "indicator calculation formula" and "micro-architecture events" corresponding to each architecture, the micro-architecture indicator set table stores indicator evaluation models corresponding to different types of micro-architectures and micro-architecture events that need to be collected. The various sub-models included in the indicator evaluation model can be, for example, the indicator calculation formulas corresponding to each sub-model. The micro-architecture events that need to be collected can be all micro-architecture events that need to be collected for the corresponding architecture.

[0110] S13, formula and event output.

[0111] In this step, the index evaluation model and micro-architecture events required by the current micro-architecture obtained by table lookup are obtained. The index evaluation model may include: the index calculation formulas corresponding to each sub-model.

[0112] S203, drive collection.

[0113] In this step, the corresponding micro-architecture events are collected by the driver according to the predetermined collection period to obtain multiple sets of call stack information. The collected call stack information is saved as metadata. Each set of call stack information contains the following collection information: function name, function call relationship and the number of occurrences of the corresponding micro-architecture event.

[0114] S204, metadata processing.

[0115] In this step, the saved metadata is processed. Specifically, a complete call relationship tree can be established based on the call relationship between each function. The number of occurrences of the corresponding micro-architecture event is accumulated to the leaf node of the corresponding function to obtain the number of occurrences of the micro-architecture event corresponding to each function. Subsequently, the function-level micro-architecture indicator is calculated based on the indicator calculation formula obtained by table lookup.

[0116] S205, function-level microarchitecture analysis is completed.

[0117] In this step, for any function among the functions, when at least one performance indicator corresponding to the function meets the abnormal condition, it is determined that there is a performance abnormality in the operation of the function, and the function determined to have a performance abnormality is regarded as a problem function, and each performance indicator corresponding to the problem function that meets the abnormal condition is regarded as a problem performance indicator; a performance analysis result corresponding to the function is generated based on the problem function and the problem performance indicator.

[0118] According to the method of the embodiment of the present application, the micro-architecture executing the predetermined application can be automatically identified, and the micro-architecture events that need to be collected and the preset indicator evaluation model that needs to be used can be obtained through the preset correspondence set query, and the collected micro-architecture events are mapped to the function level, realizing the in-depth analysis of the micro-architecture performance at the function level. In addition, the performance analysis results can be used for the optimization of the predetermined application. According to the performance analysis method, it is helpful to improve the accuracy and efficiency of locating problems related to performance bottlenecks during program optimization, and it is helpful for developers to obtain and gain insight into the differences hidden in the execution details of the function-level code from a new perspective.

[0119] Figure 3 FIG. 1 is a flow chart showing a method for analyzing the performance of a micro-architecture according to another embodiment of the present application. Figure 3 As shown, the method includes the following steps.

[0120] Step S301, obtain micro-architecture events generated by each function of the first micro-architecture executing a predetermined application, and use the performance analysis method in the above embodiment to process the micro-architecture events generated by each function corresponding to the first micro-architecture to obtain a first result, which is a performance analysis result of each function running on the first micro-architecture.

[0121] Step S302, obtaining microarchitecture events generated by each function of the second microarchitecture executing a predetermined application, and using the performance analysis method in the above embodiment to process the microarchitecture events generated by each function corresponding to the second microarchitecture to obtain a second result, which is a performance analysis result of each function running on the second microarchitecture; wherein the first microarchitecture and the second microarchitecture are different types of processor microarchitectures.

[0122] Step S303 , determining a performance comparison result of the first micro-architecture and the second micro-architecture according to the first result and the second result.

[0123] Through the above steps S301-S303, the performance analysis method in the above embodiment is used to perform performance analysis on the first micro-architecture and the second micro-architecture respectively, and the performance analysis results at the function level of each of the two are obtained. The performance analysis results at the function level of the two are compared to obtain the performance comparison results. According to this method, a unified micro-architecture performance analysis can be performed across different micro-architectures, and performance comparison between different micro-architectures is supported. For different micro-architectures provided by different cloud servers, according to this method, function-level performance analysis of different micro-architectures can be completed, helping developers to quickly and comprehensively evaluate the ability of predetermined applications to execute efficiently on different micro-architectures, and select cloud servers with micro-architectures with better performance, discover the performance bottlenecks of specific functions of the application, and help to accurately complete performance optimization work.

[0124] In some embodiments, the above-mentioned step S303 may specifically include: for any performance indicator among the preset predetermined performance indicators, obtaining the indicator value based on the performance indicator of each function from the first result as the first indicator value, and obtaining the indicator value based on the performance indicator of each function from the second result as the second indicator value; comparing the first indicator value and the second indicator value to obtain the performance comparison result based on the performance indicator of each function.

[0125] In this embodiment, the index value of the same performance index of the same function can be obtained from the first result and the second result for comparison, and the performance comparison result of the function based on the same performance index in two different micro-architectures can be obtained. For applications that need to pursue better performance in a diversified computing environment, the performance analysis method according to the embodiment of the present application can provide strong support for selecting a micro-architecture with better performance in terms of efficiency and effectiveness. Through this method, it is conducive to simplifying the workflow of software debugging and tuning based on different micro-architectures, and it is also conducive to exploring the performance analysis of different processor architectures. Provide important data support, so as to achieve efficient identification and in-depth analysis of the function-level performance bottlenecks inside the application on the different micro-architectures provided by the heterogeneous computing platform, help developers find the optimization direction of the application more quickly and accurately, and promote the field of software engineering to a higher level.

[0126] It should be understood that the specific details of the above steps in the embodiment of the present application can be referred to in conjunction with the above embodiment. Figure 1 and Figure 2 The specific details of the performance analysis method described, and the corresponding beneficial effects, are not repeated here.

[0127] Figure 4 A schematic diagram showing the structure of a performance analysis device for a micro-architecture according to an embodiment of the present application is shown, and the device is used to perform the above-mentioned combination Figure 1 and Figure 2 The microarchitecture performance analysis method described in Figure 4 As shown, the performance analysis device includes the following modules.

[0128] The collection module 410 is used to respectively collect micro-architecture events generated by the micro-architecture executing each function of the predetermined application program.

[0129] The determination module 420 is used to determine the predetermined performance indicators corresponding to the functions based on the preset indicator evaluation model of the micro-architecture and the micro-architecture events corresponding to the functions.

[0130] The analysis module 430 is used to perform performance analysis according to the predetermined performance indicators to obtain performance analysis results of the functions running on the micro-architecture.

[0131] In some embodiments, the performance analysis device also includes: an identification module, used to identify the micro-architecture executing the predetermined application according to the operating environment information of the predetermined application; the collection module 410 is specifically used to: collect micro-architecture events according to a predetermined collection period to obtain at least one set of call stack information, any set of call stack information contains at least one collection information, and any collection information is used to indicate: any function executed by the micro-architecture and the micro-architecture event generated by the execution function; wherein the micro-architecture events collected corresponding to different micro-architectures are at least partially different.

[0132] In some embodiments, the determination module 420 is specifically used to: count the microarchitecture events corresponding to each function based on each group of call stack information to obtain the number of occurrences of the microarchitecture events corresponding to each function; determine the predetermined performance indicators corresponding to each function based on a preset indicator evaluation model and the number of occurrences of the microarchitecture events corresponding to each function.

[0133] In some embodiments, any piece of collection information is also used to indicate: the function call relationship of any function; when the determination module 420 is used to count the micro-architecture events corresponding to each function based on each group of call stack information, and obtain the number of occurrences of the micro-architecture events corresponding to each function, it is specifically used to: generate a call relationship tree using the function call relationship of each function, and the attribute information of any leaf node in the call relationship tree includes: the function name of any function and the number of occurrences of the corresponding micro-architecture event; for the function indicated by any piece of collection information and the indicated micro-architecture event, the number of occurrences of the micro-architecture event is accumulated to the target leaf node, and the target leaf node is the leaf node where the function is located; summarize the number of occurrences of the micro-architecture events accumulated at each leaf node to obtain the number of occurrences of the micro-architecture events corresponding to each function.

[0134] In some embodiments, when the determination module 420 is used to determine the predetermined performance indicators corresponding to each function based on a preset indicator evaluation model and the number of occurrences of the microarchitecture events corresponding to each function, it is specifically used to: obtain each sub-model in the preset indicator evaluation model, any sub-model is used to indicate the correlation between any performance indicator and the number of occurrences of the corresponding microarchitecture event; for any function, based on the number of occurrences of the microarchitecture event corresponding to the function and the correlation indicated by each sub-model, calculate the predetermined performance indicators corresponding to the function.

[0135] In some embodiments, the performance analysis device also includes an acquisition module for acquiring a preset correspondence set before respectively collecting microarchitecture events generated by each function of the microarchitecture executing a predetermined application, wherein any correspondence in the correspondence set is used to indicate: correspondence information between the microarchitecture and the indicator evaluation model and at least one microarchitecture event; taking the identified microarchitecture as the target microarchitecture, and acquiring the indicator evaluation model and at least one corresponding microarchitecture event corresponding to the target microarchitecture from the correspondence set as the preset indicator evaluation model and each microarchitecture event of the target microarchitecture.

[0136] In some embodiments, the analysis module 430 is specifically used to: for any function among the functions, when at least one performance indicator corresponding to the function meets the abnormal condition, determine that there is a performance abnormality in the operation of the function, and the abnormal condition is used to indicate that: the corresponding performance indicator belongs to a preset value range when there is a performance abnormality; the function judged to have a performance abnormality is regarded as a problem function, and each performance indicator corresponding to the problem function that meets the abnormal condition is regarded as a problem performance indicator; and generate a performance analysis result corresponding to the function according to the problem function and the problem performance indicator.

[0137] In some embodiments, the analysis module 430 is also used to: after generating the performance analysis results corresponding to the function according to the problem function and the problem performance indicator, obtain any performance indicator in the problem performance indicator as the current indicator, and obtain the next-level indicator of the current indicator, the next-level indicator includes the sub-performance indicators obtained by pre-dividing the current indicator; based on the new indicator evaluation model and the new micro-architecture event, determine the sub-performance indicators of the micro-architecture, the new indicator evaluation model is used to indicate: the correlation between each sub-performance indicator and the number of occurrences of the corresponding new micro-architecture event; when at least one sub-performance indicator meets the abnormal condition, use the sub-performance indicators that meet the abnormal condition as the new problem performance indicator, and use any performance indicator in the new problem performance indicator as the new current indicator, and start the loop from the step of obtaining the next-level indicator of the current indicator until a stop processing instruction is received or the number of sub-performance indicators contained in the next-level indicator of the new current indicator is zero, and the performance analysis processing of the micro-architecture is stopped.

[0138] The functions of each module in each device in the embodiments of the present application can be found in the corresponding description in the above method, and have corresponding beneficial effects, which will not be repeated here.

[0139] Figure 5 A schematic diagram of a micro-architecture performance analysis device according to another embodiment of the present invention is shown, wherein the device is used to perform the above-mentioned combination Figure 3 The microarchitecture performance analysis method described in Figure 5 As shown, the performance analysis device includes the following modules.

[0140] The first processing module 510 is used to obtain micro-architecture events generated by each function of the first micro-architecture executing a predetermined application, and use the performance analysis method in the above embodiment to process the micro-architecture events generated by each function corresponding to the first micro-architecture to obtain a first result, which is a performance analysis result of each function running on the first micro-architecture.

[0141] The second processing module 520 is used to obtain microarchitecture events generated by each function of the second microarchitecture executing a predetermined application, and use the performance analysis method in the above embodiment to process the microarchitecture events generated by each function corresponding to the second microarchitecture to obtain a second result, which is a performance analysis result of each function running on the second microarchitecture; wherein the first microarchitecture and the second microarchitecture are different types of processor microarchitectures.

[0142] The result comparison module 530 is used to determine a performance comparison result of the first micro-architecture and the second micro-architecture according to the first result and the second result.

[0143] In some embodiments, the result comparison module 530 is specifically used to: for any performance indicator among the preset predetermined performance indicators, obtain the indicator value based on the performance indicator of each function from the first result as the first indicator value, and obtain the indicator value based on the performance indicator of each function from the second result as the second indicator value; compare the first indicator value and the second indicator value to obtain the performance comparison result based on the performance indicator of each function.

[0144] The functions of each module in each device in the embodiments of the present application can be found in the corresponding description in the above method, and have corresponding beneficial effects, which will not be repeated here.

[0145] Figure 6 FIG. 1 is a block diagram of an electronic device used to implement an embodiment of the present application. Figure 6As shown, the electronic device includes: a memory 601 and a processor 602, and the memory 601 stores a computer program that can be run on the processor 602. When the processor 602 executes the computer program, the method in the above embodiment is implemented. The number of the memory 601 and the processor 602 can be one or more. In a specific implementation, the electronic device may also include a communication interface 603 for communicating with external devices and performing data exchange transmission.

[0146] In specific implementation, if the memory 601, the processor 602 and the communication interface 603 are implemented independently, the memory 601, the processor 602 and the communication interface 603 can be connected to each other through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0147] Optionally, in a specific implementation, if the memory 601, the processor 602 and the communication interface 603 are integrated on a chip, the memory 601, the processor 602 and the communication interface 603 can communicate with each other through an internal interface.

[0148] An embodiment of the present application provides a computer-readable storage medium storing a computer program, which implements the method provided in the embodiment of the present application when the program is executed by a processor.

[0149] An embodiment of the present application provides a computer program product, including a computer program, which implements the method provided in the embodiment of the present application when executed by a processor.

[0150] An embodiment of the present application also provides a chip, which includes a processor for calling and executing instructions stored in the memory from the memory, so that a communication device equipped with the chip executes the method provided by the embodiment of the present application.

[0151] An embodiment of the present application also provides a chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected via an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute the method provided in the embodiment of the application.

[0152] It should be understood that the above processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc. It is worth noting that the processor can be a processor that supports the Advanced RISC Machines (ARM) architecture.

[0153] Further, optionally, the above-mentioned memory may include a read-only memory and a random access memory. The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may include a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may include a random access memory (RAM), which is used as an external cache. By way of exemplary but not limiting description, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (DR RAM).

[0154] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium.

[0155] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0156] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0157] Any process or method described in the flow chart or otherwise described herein can be understood as a module, fragment or portion of a code representing one or more executable instructions for implementing the steps of a specific logical function or process. And the scope of the preferred embodiment of the present application includes other implementations, in which the functions may not be performed in the order shown or discussed, including in a substantially simultaneous manner or in a reverse order according to the functions involved.

[0158] The logic and / or steps described in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by an instruction execution system, apparatus or device (such as a computer-based system, a system including a processor or other system that can fetch instructions from an instruction execution system, apparatus or device and execute instructions), or used in combination with these instruction execution systems, apparatuses or devices.

[0159] It should be understood that the various parts of the present application can be implemented with hardware, software, firmware or a combination thereof. In the above embodiments, multiple steps or methods can be implemented with software or firmware stored in a memory and executed by a suitable instruction execution system. All or part of the steps of the above embodiment method can be completed by instructing the relevant hardware through a program, which can be stored in a computer-readable storage medium, and when the program is executed, it includes one of the steps of the method embodiment or a combination thereof.

[0160] In addition, each functional unit in each embodiment of the present application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into one module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. If the above-mentioned integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium can be a read-only memory, a disk or an optical disk, etc.

[0161] The above is only an exemplary embodiment of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope recorded in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A performance analysis method for a microarchitecture, characterized in that: include: respectively collecting micro-architecture events generated by each function of the micro-architecture executing the predetermined application program; Determine the predetermined performance indicators corresponding to the functions based on the preset indicator evaluation model of the micro-architecture and the micro-architecture events corresponding to the functions; Perform performance analysis according to the predetermined performance indicators to obtain performance analysis results of the functions running on the micro-architecture.

2. The method according to claim 1, characterized in that The respectively collecting micro-architecture events generated by the micro-architecture executing each function of the predetermined application program includes: Identifying a micro-architecture for executing a predetermined application program based on the operating environment information of the predetermined application program; The microarchitecture events are collected according to a predetermined collection period to obtain at least one set of call stack information, any set of call stack information contains at least one piece of collection information, and any piece of collection information is used to indicate: any function executed by the microarchitecture and the microarchitecture events generated by the execution of the function; wherein the microarchitecture events collected corresponding to different microarchitectures are at least partially different.

3. The method according to claim 1, characterized in that The step of determining the predetermined performance indicators corresponding to the functions based on the preset indicator evaluation model of the micro-architecture and the micro-architecture events corresponding to the functions includes: Based on each group of call stack information, the micro-architecture events corresponding to each function are counted to obtain the number of occurrences of the micro-architecture events corresponding to each function; Based on the preset indicator evaluation model and the number of occurrences of the micro-architecture events corresponding to the functions, the predetermined performance indicators corresponding to the functions are determined.

4. The method according to claim 3, characterized in that Any of the collected information is also used to indicate: a function call relationship of any of the functions; based on each set of call stack information, the micro-architecture events corresponding to each of the functions are counted to obtain the number of occurrences of the micro-architecture events corresponding to each of the functions, including: Generate a call relationship tree using the function call relationship of each function, wherein the attribute information of any leaf node in the call relationship tree includes: the function name of any function and the number of occurrences of the corresponding micro-architecture event; For any function and micro-architecture event indicated by any piece of collected information, the number of occurrences of the micro-architecture event is accumulated to a target leaf node, where the target leaf node is the leaf node where the function is located; The number of occurrences of the micro-architecture events accumulated at each leaf node is summarized to obtain the number of occurrences of the micro-architecture events corresponding to each function.

5. The method according to claim 3, characterized in that: The determining of the predetermined performance indicators corresponding to the functions based on the preset indicator evaluation model and the number of occurrences of the micro-architecture events corresponding to the functions respectively includes: Obtaining each sub-model in the preset indicator evaluation model, wherein any sub-model is used to indicate the correlation between any performance indicator and the number of occurrences of a corresponding micro-architecture event; For any of the functions, based on the number of occurrences of the micro-architecture event corresponding to the function and the association relationships respectively indicated by the sub-models, the predetermined performance indicators corresponding to the function are calculated.

6. The method according to any one of claims 1 to 5, characterized in that Before respectively collecting micro-architecture events generated by the micro-architecture executing each function of the predetermined application, the method further includes: Obtaining a preset correspondence set, wherein any correspondence in the correspondence set is used to indicate: correspondence information between a micro-architecture and an indicator evaluation model and at least one micro-architecture event; The identified microarchitecture is taken as the target microarchitecture, and an indicator evaluation model and at least one corresponding microarchitecture event corresponding to the target microarchitecture are obtained from the corresponding relationship set as the preset indicator evaluation model and each microarchitecture event of the target microarchitecture.

7. The method according to claim 1, characterized in that The performing performance analysis according to the predetermined performance indicators to obtain performance analysis results of the functions running on the micro-architecture includes: For any function among the functions, when at least one performance indicator corresponding to the function satisfies an abnormal condition, it is determined that the operation of the function has a performance abnormality, and the abnormal condition is used to indicate that: the corresponding performance indicator belongs to a preset value range when there is a performance abnormality; The function determined to have performance anomalies is regarded as a problem function, and each performance index corresponding to the problem function and satisfying the anomaly condition is regarded as a problem performance index; A performance analysis result corresponding to the function is generated according to the problem function and the problem performance indicator.

8. The method according to claim 7, characterized in that After generating the performance analysis result corresponding to the function according to the problem function and the problem performance indicator, the method further includes: Obtain any performance indicator among the problem performance indicators as the current indicator, and obtain a next-layer indicator of the current indicator, wherein the next-layer indicator includes each sub-performance indicator obtained by pre-dividing the current indicator; Determine each sub-performance index of the micro-architecture based on a new index evaluation model and a new micro-architecture event, wherein the new index evaluation model is used to indicate: a correlation relationship between each sub-performance index and the number of occurrences of the corresponding new micro-architecture event; When at least one sub-performance indicator satisfies the abnormal condition, each sub-performance indicator that satisfies the abnormal condition is used as a new problem performance indicator, and any performance indicator among the new problem performance indicators is used as a new current indicator. The process is looped starting from the step of obtaining the next layer indicator of the current indicator until a stop processing instruction is received or the number of sub-performance indicators included in the next layer indicator of the new current indicator is zero, and the performance analysis processing of the microarchitecture is stopped.

9. A performance analysis method for a microarchitecture, characterized in that: The method comprises: Obtaining microarchitecture events generated by each function of a predetermined application program executed by a first microarchitecture, and processing the microarchitecture events generated by each function corresponding to the first microarchitecture using the method described in any one of claims 1 to 8 to obtain a first result, wherein the first result is a performance analysis result of each function running on the first microarchitecture; Obtaining microarchitecture events generated by each function of the predetermined application program executed by the second microarchitecture, and processing the microarchitecture events generated by each function corresponding to the second microarchitecture using the method described in any one of claims 1 to 8 to obtain a second result, wherein the second result is a performance analysis result of each function running on the second microarchitecture; wherein the first microarchitecture and the second microarchitecture are different types of processor microarchitectures; A performance comparison result between the first micro-architecture and the second micro-architecture is determined according to the first result and the second result.

10. The method according to claim 9, characterized in that Determining a performance comparison result between the first micro-architecture and the second micro-architecture according to the first result and the second result includes: For any performance indicator among the preset predetermined performance indicators, obtaining an indicator value of each function based on the performance indicator from the first result as a first indicator value, and obtaining an indicator value of each function based on the performance indicator from the second result as a second indicator value; The first indicator value and the second indicator value are compared to obtain performance comparison results of the functions based on the performance indicators.

11. An electronic device comprising a memory, a processor and a computer program stored in the memory, wherein the processor implements the method according to any one of claims 1 to 8 or any one of claims 9 to 10 when executing the computer program.

12. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 or any one of claims 9 to 10 is implemented.

13. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8 or any one of claims 9-10.

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