UVM-based SMU verification system and method in vehicle-gauge-level chip

Abstract

The invention relates to a UVM-based SMU verification system and a UVM-based SMU verification method in a vehicle-gauge-level chip, and an SMU module-level special verification system is established for verification of an SMU in the vehicle-gauge-level chip based on a UVM verification methodology. A register model component, a to-be-tested design SMU, a platform environment component, a sequence configuration component, a format converter, an environment configuration component, an APB interface, an alarm interface and a response interface are integrated, and the environment configuration component can be used for flexibly coordinating the alarm triggering sequence, triggering time and alarm width of each alarm triggering agent component; according to the method, the dependency of the to-be-tested designed SMU on triggering an alarm signal in an abnormal failure scene of the external module unit is greatly reduced, the defects of low verification efficiency and incomplete and inflexible excitation in a traditional verification technology are overcome, the verification quality is effectively improved, the verification time of the SMU is greatly shortened, and chip production scheduling is accelerated.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip verification, and relates to a UVM-based SMU verification system and method in an automotive-grade chip. Background Art

[0002] Automotive-grade chips are core components in automotive electronics. In order to ensure the safety of people on board, functional safety is crucial. Many safety mechanisms are integrated into automotive-grade chips, including safety mechanisms within functional unit modules and safety mechanisms at the system level. When a fault occurs and is detected by the corresponding safety mechanism, the safety mechanism can generate an alarm signal in time to report the occurrence of the fault. SMU (Safety Management Unit) is the core component of the safety architecture of automotive-grade chips. It collects all alarm signals centrally, responds to the severity of the alarm according to the predefined actions configured by the software, and notifies internal modules or the external environment. SMU can reduce safety risks caused by system design problems or random hardware failures, avoid hidden faults or functional failures directly caused by faults, and ensure safe and reliable execution of chips.

[0003] Verifying the monitoring performance and response strategy of SMU to alarm signals is an important means to ensure the functional safety of its design. However, in traditional verification technology, the triggering of alarm signals depends on the failure scenarios reported by the various safety mechanisms integrated in automotive-grade chips, which results in the inability to flexibly generate alarm signals during the verification process, making it difficult to ensure the verification quality of SMU functional safety verification, such as efficiency, randomness, and completeness. Summary of the invention

[0004] In response to the problems existing in the above-mentioned traditional technologies, the present invention proposes a SMU verification system in an automotive-grade chip based on UVM and a SMU verification method in an automotive-grade chip based on UVM, which can effectively improve the verification quality such as the functional safety verification efficiency, randomness and completeness of the SMU.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a UVM-based SMU verification system for automotive-grade chips is provided, including a top-level file, the top-level file including a test case base class, an instantiated APB bus, an alarm interface, a response interface, and a design SMU to be tested; Based on the test case base class, a platform environment component, an environment configuration component, a register model component, a sequence configuration component and a format converter are deployed. The platform environment component includes a reference model component, a scoreboard, an APB environment component, multiple alarm trigger agent components, a virtual sequence manager and a response agent component. The reference model component is respectively connected to the register model component, the alarm trigger agent component and the scoreboard. The sequence configuration component is respectively connected to the register model component and the format converter. The format converter is respectively connected to the APB environment component and the register model component. The instantiated APB bus, alarm interface and response interface are respectively used to connect the design SMU to be tested and the platform environment component. The APB environment component includes an APB environment configuration component and an APB host agent component. The APB host agent component is composed of a sequence manager, an APB monitor and an excitation driver, and is used to simulate the APB protocol communication function to realize the configuration and access to the design SMU to be tested. The sequence manager of the APB host agent component is connected to the format converter. The APB host agent component is connected to the design SMU to be tested through the APB bus. The number of alarm trigger agent components corresponds to the number of alarm signals that need to be collected and responded to in the design SMU to be tested. Each alarm trigger agent component is composed of a sequence manager and an excitation driver. Each alarm trigger agent component is connected to the design SMU to be tested through an alarm interface. The sequence manager of each alarm trigger agent component is respectively connected to the virtual sequence manager. The response agent component includes a response monitor. The design SMU to be tested is connected to the response agent component through a response interface. The response agent component is connected to the scoreboard. The virtual sequence manager is used to coordinate the alarm trigger agent components to generate alarm combinations of various test scenarios based on the test scenarios derived from the test case base class, according to the test scenario sequence, the configured alarm trigger time and the alarm width. The environment configuration component is used to randomly configure the SMU registers and ensure that each alarm signal covers all response strategies of the SMU to be tested. The reference model component is used to generate the expected response signal and expected register state for the SMU to be tested based on the configuration data of the environment configuration component and the received alarm signal. The scoreboard is used to compare the response signal of the SMU to be tested with the expected response signal after each alarm is triggered, and to compare the register state of the SMU to be tested with the expected register state, so as to determine the functional test results after each alarm is triggered.

[0006] On the other hand, a UVM-based SMU verification method in an automotive-grade chip is also provided, which is applied to the above-mentioned UVM-based SMU verification system in an automotive-grade chip. The UVM-based SMU verification method in an automotive-grade chip comprises the steps of: Power on and initialize the SMU verification system in the UVM-based automotive-grade chip; Randomly configure SMU registers through the environment configuration component; Through the virtual sequence manager, based on each test scenario derived from the test case base class, coordinate each alarm trigger agent component to generate an alarm combination of multiple test scenarios according to the test scenario sequence, the configured alarm trigger time and the alarm width; After each alarm is triggered, the scoreboard compares the response signal of the SMU under test with the expected response signal sent by the reference model component, and compares the register state of the SMU under test with the expected register state sent by the reference model component to determine the functional test result after each alarm is triggered.

[0007] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned UVM-based SMU verification system and method in automotive-grade chips establishes a dedicated verification system at the SMU module level for the verification of SMU in automotive-grade chips based on the UVM verification methodology, and integrates register model components, SMUs to be tested, platform environment components, sequence configuration components, format converters, environment configuration components, APB interfaces, alarm interfaces and response interfaces. The environment configuration components can be used to flexibly coordinate the alarm triggering order, triggering time and alarm width of each alarm triggering agent component, greatly reducing the dependence of the SMU to be tested on the abnormal failure scenario triggering alarm signal of the external module unit, solving the shortcomings of low verification efficiency, incomplete incentives and inflexibility in traditional verification technology, effectively improving the verification quality, and greatly advancing the verification time of the SMU, thereby accelerating chip production. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0009] Figure 1 It is a structural block diagram of an SMU verification system in an automotive-grade chip based on UVM in an embodiment; Figure 2 A schematic diagram of the workflow of an SMU verification system in an automotive-grade chip based on UVM in one embodiment; Figure 3 It is a flowchart of an SMU verification method in an automotive-grade chip based on UVM in an embodiment. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0011] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification of the present invention and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0012] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0013] In one embodiment, Figure 1 As shown, a SMU verification system for a car-grade chip based on UVM is provided, including a top-level file, which includes a test case base class, an instantiated APB bus, an alarm interface, a response interface, and a design SMU to be tested. A platform environment component, an environment configuration component, a register model component, a sequence configuration component, and a format converter are deployed based on the test case base class. The platform environment component includes a reference model component, a scoreboard, an APB environment component, multiple alarm trigger agent components, a virtual sequence manager, and a response agent component. The reference model component is respectively connected to the register model component, the alarm trigger agent component, and the scoreboard. The sequence configuration component is respectively connected to the register model component and the format converter, and the format converter is respectively connected to the APB environment component and the register model component. The instantiated APB bus, the alarm interface, and the response interface are respectively used to connect the design SMU to be tested and the platform environment component. The APB environment component includes an APB environment configuration component and an APB host agent component. The APB host agent component consists of a sequence manager, an APB monitor and an excitation driver, and is used to simulate the APB protocol communication function to realize the configuration and access to the design SMU under test. The sequence manager of the APB host agent component is connected to the format converter, and the APB host agent component is connected to the design SMU under test through the APB bus.

[0014] The number of alarm trigger agent components corresponds to the number of alarm signals that need to be collected and responded to in the design SMU to be tested. Each alarm trigger agent component is composed of a sequence manager and an excitation driver. Each alarm trigger agent component is connected to the design SMU to be tested through an alarm interface. The sequence manager of each alarm trigger agent component is connected to the virtual sequence manager respectively. The response agent component includes a response monitor. The design SMU to be tested is connected to the response agent component through a response interface, and the response agent component is connected to the scoreboard. The virtual sequence manager is used to coordinate each alarm trigger agent component to generate alarm combinations of multiple test scenarios according to the test scenario sequence, the configured alarm trigger time and the alarm width based on each test scenario derived from the test case base class. The environment configuration component is used to randomly configure the SMU register and ensure that each alarm signal covers all response strategies of the design SMU to be tested. The reference model component is used to generate the expected response signal and the expected register state for the design SMU to be tested according to the configuration data of the environment configuration component and the received alarm signal. The scoreboard is used to compare the response signal of the SMU under test with the expected response signal after each alarm is triggered, and to compare the register state of the SMU under test with the expected register state to determine the functional test result after each alarm is triggered.

[0015] It can be understood that the design of each component in the SMU verification system of the above-mentioned UVM-based automotive-grade chip follows the existing UVM verification methodology. According to the randomness and completeness verification of the integrated SMU to be tested, it is necessary to configure the components of the corresponding functions based on the UVM verification platform, and complete the connection between the components, connectivity testing and other basic operations to ensure the normal data flow between the components during the verification process.

[0016] The functions of the SMU under test to collect and respond to alarm signals are fully verified. The platform architecture of the verification system provided in this embodiment is as follows: Figure 1 As shown in the figure, the verification system only integrates the SMU of the design to be tested to be verified, and does not rely on the abnormal failure scenarios of other safety mechanism modules to trigger the alarm signal, which greatly shortens the SMU verification time and improves the verification efficiency and completeness. The top-level file of the entire verification environment of the SMU verification system in the UVM-based automotive-grade chip includes the test case base class, the instantiated APB bus (which can be recorded as the APB interface), the instantiated alarm interface, the response interface and the design SMU to be tested (also known as DUT).

[0017] Based on the test case base class, multiple test cases are derived and platform environment components, environment configuration components, register model components, sequence configuration components and format converters are created. The platform environment components include reference model components, scoreboards, APB environment components, multiple alarm trigger agent components, virtual sequence managers and response agent components. The reference model components are connected to the register model components, alarm trigger agent components and scoreboards respectively. The sequence configuration components are connected to the register model components and the format converter respectively. The format converter is connected to the APB environment component and the register model component respectively. The sequence configuration component is used to configure and distribute read and write operation sequences. The format converter is used to realize the conversion between read and write operation requests in the register model component and bus transactions in the APB environment component.

[0018] The APB environment component includes an APB environment configuration component and an APB host agent component. The APB host agent component is composed of a sequence manager, an APB monitor and an excitation driver. The sequence manager of the APB host agent component is connected to the format converter. The APB host agent component is connected to the design SMU to be tested through the APB interface. The APB environment component implements the register configuration and access functions of the design SMU to be tested through the APB protocol. The number of alarm trigger agent components is determined and instantiated according to the number of alarm signals collected and responded in the design SMU to be tested. Each alarm trigger agent component is composed of a sequence manager and an excitation driver. Each alarm trigger agent component is connected to the design SMU to be tested through the alarm interface. The sequence manager of each alarm trigger agent component is respectively connected to the virtual sequence manager. The response agent component includes a response monitor. The design SMU to be tested is connected to the response agent component through the response interface, and the response agent component is connected to the scoreboard. The communication direction between the above components is indicated by arrows, and double arrows indicate that bidirectional communication is possible.

[0019] Among them, the virtual sequence manager is used to coordinate various alarm trigger agent components based on various test scenarios derived from the test case base class to generate alarm combinations of various test scenarios according to the test scenario sequence, the configured alarm trigger time and the width of the alarm (duration). The sequence manager in each alarm trigger agent component is used to drive the alarm signal to the alarm interface of the SMU under test through the excitation driver in the alarm trigger agent component according to the alarm trigger time and alarm width configured by the sequence model sequence of the virtual sequence manager, and also drive the alarm signal to the reference model component.

[0020] The above-mentioned UVM-based SMU verification system in automotive-grade chips establishes a dedicated verification system at the SMU module level for the verification of SMU in automotive-grade chips based on the UVM verification methodology, and integrates register model components, SMUs to be tested, platform environment components, sequence configuration components, format converters, environment configuration components, APB interfaces, alarm interfaces and response interfaces. The environment configuration components can flexibly coordinate the alarm triggering order, triggering time and alarm width of each alarm triggering agent component, greatly reducing the dependence of the SMU to be tested on the abnormal failure scenario triggering alarm signal of the external module unit, solving the shortcomings of low verification efficiency, incomplete incentives and inflexibility in traditional verification technology, effectively improving the verification quality, and greatly advancing the verification time of the SMU, thereby accelerating chip production.

[0021] In one embodiment, the above alarm combination may include sequential triggering, disordered triggering, parallel triggering, back-to-back triggering, and triggering at different intervals between alarms to solve the defects of incomplete and insufficient incentives in traditional verification technology.

[0022] The environment configuration component is used to randomize the configuration of the SMU under test and implement the configuration of the SMU under test through the register model component. In addition, the existing functional coverage method can be used to collect the response strategies output by the SMU under test when it detects an alarm signal under different configurations to ensure that each alarm signal covers all response strategies.

[0023] The reference model component predicts the response signal and register status of the SMU to be tested based on the configuration data of the environment configuration component and the received alarm signal to produce the corresponding expected results. After each alarm is triggered, the scoreboard compares the response signal of the SMU to be tested with the expected response signal sent by the reference model component, and compares the register status inside the SMU to be tested with the expected register status sent by the reference model component to determine the functional test results of the SMU to be tested after each alarm is triggered.

[0024] In one embodiment, after each alarm is triggered, if the scoreboard determines that the response signal of the SMU under test is consistent with the expected response signal, and the register state of the SMU under test is also consistent with the expected register state, the output functional test result is that the test passed and the test passed simulation log information corresponding to the alarm triggered this time is printed.

[0025] In one embodiment, after each alarm is triggered, if the scoreboard determines that the response signal of the SMU under test is inconsistent with the expected response signal, or the register state of the SMU under test is inconsistent with the expected register state, the output functional test result is test failure and the test failure simulation log information corresponding to the alarm triggered this time is printed.

[0026] Specifically, Figure 2 As shown, for example, after each alarm is triggered, the response signal corresponding to the output of the SMU under test is consistent with the expected response signal sent by the reference model component, and the register state inside the SMU under test is also consistent with the expected register state sent by the reference model component. Then the functional test result is the test passed and the test pass simulation log information corresponding to the alarm triggered this time is printed. On the contrary, if one of the items is inconsistent or both items are inconsistent, then the functional test result is the test failed and the test failed simulation log information corresponding to the alarm triggered this time is printed. The above verification method effectively improves the functional verification efficiency of the SMU under test in monitoring and responding to alarm signals in various failure scenarios.

[0027] Each component in the SMU verification system for the above-mentioned UVM-based automotive-grade chip can be fully or partially implemented by software, hardware, and a combination thereof. The above-mentioned components can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to the above-mentioned modules. The aforementioned device can be, but is not limited to, various types of chip verification computers already available in the art.

[0028] In one embodiment, a UVM-based SMU verification method for automotive-grade chips is provided, which is applied to the above-mentioned UVM-based SMU verification system for automotive-grade chips, such as Figure 3 As shown, the SMU verification method in the automotive-grade chip based on UVM includes the following steps S10 to S16: S10, power on and initialize the SMU verification system in the automotive-grade chip based on UVM; S12, randomly configuring the SMU registers through the environment configuration component; S14, coordinating each alarm trigger agent component to generate an alarm combination of multiple test scenarios according to the test scenario sequence, the configured alarm trigger time and the alarm width based on each test scenario derived from the test case base class through the virtual sequence manager; S16, after each alarm is triggered, the response signal of the SMU under test is compared with the expected response signal sent by the reference model component through the scoreboard, and the register state of the SMU under test is compared with the expected register state sent by the reference model component to determine the functional test result after each alarm is triggered.

[0029] The above-mentioned UVM-based SMU verification method in automotive-grade chips establishes a dedicated verification system at the SMU module level for the verification of SMU in automotive-grade chips based on the UVM verification methodology, and integrates register model components, SMUs to be tested, platform environment components, sequence configuration components, format converters, environment configuration components, APB interfaces, alarm interfaces and response interfaces. The environment configuration components can be used to flexibly coordinate the alarm triggering order, triggering time and alarm width of each alarm triggering agent component, greatly reducing the dependence of the SMU to be tested on the abnormal failure scenario triggering alarm signal of the external module unit, solving the shortcomings of low verification efficiency, incomplete stimulation and inflexibility in traditional verification technology, effectively improving the verification quality, and greatly advancing the verification time of SMU, thereby accelerating chip production.

[0030] For the specific limitations of the SMU verification method in the UVM-based automotive-grade chip, please refer to the corresponding limitations of the SMU verification system in the UVM-based automotive-grade chip above, which will not be repeated here.

[0031] It should be understood that although Figure 3 The steps in the method are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps can be executed in other orders. Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0032] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus dynamic random access memory (RambusDRAM, referred to as RDRAM) and interface dynamic random access memory (DRDRAM).

[0033] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0034] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A UVM-based SMU verification system for automotive-grade chips, characterized in that: The top-level file includes a test case base class, an instantiated APB bus, an alarm interface, a response interface, and a design SMU to be tested; Based on the test case base class, a platform environment component, an environment configuration component, a register model component, a sequence configuration component and a format converter are deployed. The platform environment component includes a reference model component, a scoreboard, an APB environment component, multiple alarm trigger agent components, a virtual sequence manager and a response agent component. The reference model component is respectively connected to the register model component, the alarm trigger agent component and the scoreboard, the sequence configuration component is respectively connected to the register model component and the format converter, the format converter is respectively connected to the APB environment component and the register model component, and the instantiated APB bus, the alarm interface and the response interface are respectively used to connect the design SMU to be tested and the platform environment component; The APB environment component includes an APB environment configuration component and an APB host agent component. The APB host agent component is composed of a sequence manager, an APB monitor and an excitation driver, and is used to simulate the APB protocol communication function to realize the configuration and access to the design SMU under test. The sequence manager of the APB host agent component is connected to the format converter. The APB host agent component is connected to the design SMU under test through the APB bus. The number of the alarm trigger agent components corresponds to the number of alarm signals that need to be collected and responded to in the design SMU under test. Each of the alarm trigger agent components is composed of a sequence manager and an excitation driver. Each of the alarm trigger agent components is connected to the design SMU under test through the alarm interface. The sequence manager of each of the alarm trigger agent components is respectively connected to the virtual sequence manager. The response agent component includes a response monitor. The design SMU under test is connected to the response agent component through the response interface. The response agent component is connected to the scoreboard. The virtual sequence manager is used to coordinate the alarm trigger agent components to generate alarm combinations of multiple test scenarios according to the test scenario sequence, the configured alarm trigger time and the alarm width based on the test scenarios derived from the test case base class. The environment configuration component is used to randomly configure the SMU registers and ensure that each alarm signal covers all response strategies of the SMU to be tested. The reference model component is used to generate an expected response signal and an expected register state for the SMU to be tested based on the configuration data of the environment configuration component and the received alarm signal. The scoreboard is used to compare the response signal of the SMU to be tested with the expected response signal after each alarm is triggered, and to compare the register state of the SMU to be tested with the expected register state, so as to determine the functional test result after each alarm is triggered.

2. The SMU verification system in the automotive-grade chip based on UVM according to claim 1, characterized in that: The alarm combination includes sequential triggering, disordered triggering, parallel triggering, back-to-back triggering and triggering at different time intervals between alarms.

3. The SMU verification system in the automotive-grade chip based on UVM according to claim 1 or 2, characterized in that: After each alarm is triggered, if the scoreboard determines that the response signal of the SMU to be tested is consistent with the expected response signal, and the register state of the SMU to be tested is also consistent with the expected register state, the output functional test result is that the test passed and the test pass simulation log information corresponding to the alarm triggered this time is printed.

4. The SMU verification system in the automotive-grade chip based on UVM according to claim 1 or 2, characterized in that: After each alarm is triggered, if the scoreboard determines that the response signal of the SMU under test is inconsistent with the expected response signal, or the register state of the SMU under test is inconsistent with the expected register state, the functional test result output is test failure and the test failure simulation log information corresponding to the alarm triggered this time is printed.

5. A UVM-based SMU verification method for automotive-grade chips, characterized in that: Applied to the SMU verification system in the automotive-grade chip based on UVM according to any one of claims 1 to 4, the SMU verification method in the automotive-grade chip based on UVM comprises the steps of: Power on and initialize the SMU verification system in the UVM-based automotive-grade chip; Randomly configure SMU registers through the environment configuration component; Based on each test scenario derived from the test case base class, the virtual sequence manager coordinates each alarm trigger agent component to generate an alarm combination of multiple test scenarios according to the test scenario sequence, the configured alarm trigger time and the alarm width; After each alarm is triggered, the scoreboard is used to compare the response signal of the SMU under test with the expected response signal sent by the reference model component, and to compare the register state of the SMU under test with the expected register state sent by the reference model component to determine the functional test result after each alarm is triggered.

Images