Xintf bus interface controller based on field programmable gate array

Abstract

The invention discloses a field programmable gate array-based Xintf bus interface controller, which comprises a dual-port RAM module, a DSP chip assembly, an FPGA chip, an Xintf interface control line management module, an Xintf interface data writing management module and an Xintf interface data reading management module, and is characterized in that the FPGA chip is connected with the Xintf interface control line management module, the FPGA chip is connected with a daughter card through an Xintf bus, and the daughter card is connected with the DSP chip assembly. The FPGA chip is used for releasing the daughter card bus to the authorized DSP chip according to the authority state of the DSP chip assembly to realize daughter card conduction connection; the system has the advantages of being high in flexibility, expandability, reconfigurability and parallel processing capacity, function expansion can be carried out on the Xintf asynchronous bus of the DSP chip through the FPGA chip, external expansion chip access control of various function types is achieved, external expansion interface access diversification is achieved, function expansion of external expansion chip access control logic is achieved through the FPGA, and the system is convenient to use and popularize. And the method has higher flexibility and expandability.

Description

Technical Field

[0001] The invention relates to the technical field of Xintf bus interface controllers, in particular to a Xintf bus interface controller based on a field programmable gate array. Background Art

[0002] With the diversification and complexity of the functions of application equipment in the aerospace field, while the performance requirements for processor operating frequency, core number, computing power, etc. are getting higher and higher, there is an increasing demand for peripheral interfaces and types of peripheral devices, especially in the application of DSP28335 processors in the control field.

[0003] Although the DSP processor has built-in multiple basic peripherals, such as ADC, SCI, SPI, etc., in the application context of dual-redundancy control, large data storage, high-precision acquisition, and complex bus communication, it is necessary to expand the DSP processor with SRAM, Flash, ADC, MIL-1394 communication, and bus authority control logic between dual redundancy. At the same time, in order to meet the equipment information response time requirements, a parallel interface is required to achieve information access to the external chip; although the DSP28335 has a built-in Xintf asynchronous bus (parallel interface), relying solely on the DSP's Xintf bus to achieve the above functional requirements will result in problems such as complex external circuit design, low reliability, and low operating efficiency. Summary of the invention

[0004] The object of the present invention is to provide a Xintf bus interface controller based on a field programmable gate array to solve the problems of complex circuits, low reliability and low operating efficiency proposed in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions: A Xintf bus interface controller based on a field programmable gate array comprises a dual-port RAM module, a DSP chip assembly, an FPGA chip, a Xintf interface control line management module, a Xintf interface write data management module and a Xintf interface read data management module; the DSP chip assembly and the FPGA chip are connected to each other via a parallel asynchronous bus, the FPGA chip is connected to the Xintf interface control line management module, and the FPGA chip is connected to a subcard via the Xintf bus; The output end of the DSP chip assembly is connected to an AD, RAM, and Flash external expansion chip. The daughter card is accessed by the bus of the DSP chip assembly, and AD, RAM, and Flash are all one-to-one bus accesses; the FPGA chip is used to release the daughter card bus to the authorized DSP chip according to the authority status of the DSP chip assembly to realize the daughter card conduction connection; The Xintf interface control line management module controls the operation of the DSP chip component, the FPGA chip, the Xintf interface read data management module and the Xintf interface write data management module respectively. The Xintf interface read data management module is used to control the DSP chip component to read the data signal and write it into the dual-port RAM module, and the Xintf interface write data management module is used to control the DSP chip component's DSP data information to be written into the dual-port RAM module.

[0006] Furthermore, the DSP chip assembly includes a first DSP chip and a second DSP chip, and the Xintf buses of the first DSP chip and the second DSP chip are connected to the AD, RAM, Flash and FPGA chips, and the Xintf bus includes a data bus, an address bus, a read control signal, a write control signal and a chip select signal.

[0007] Furthermore, the daughter card adopts a MIL-1394 daughter card, which is connected to the FPGA chip separately and is interconnected with the DSP chip bus with control authority through the internal logic control of the FPGA chip.

[0008] Furthermore, the chip selection signals of the external expansion chip AD, RAM, Flash, and daughter card are all controlled by the FPGA chip.

[0009] The beneficial effects of the present invention are: 1. The present invention has the characteristics of high flexibility, scalability, reconfigurability, and strong parallel processing capability. It can expand the function of the Xintf asynchronous bus of the DSP chip through the FPGA chip, realize access control of external expansion chips of various functional types, expand the functional requirements of various peripherals, and realize the diversification of external expansion interface access. The external expansion chip access control logic is implemented by FPGA to expand the function, which has higher flexibility and scalability. The types and quantities of peripheral chips can be continuously increased according to the application requirements of the equipment. Only the FPGA software needs to be adaptively adjusted, which reduces the cost and the risk of technical development and application. The bus data processing efficiency is improved through the dual-port RAM, which is conducive to the promotion and use of the FPGA-based Xintf bus interface controller.

[0010] 2. The present invention has the characteristics of simple circuit and reliability. The main functions are realized by FPGA chip. The logic control can be adjusted according to the actual application requirements. It has high flexibility, configurability and portability, and has reference significance for bus expansion of other types of processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a principle block diagram of the signal cross-linking of the Xintf bus interface controller of the present invention; Figure 2It is a principle block diagram of the Xintf bus interface controller of the present invention.

[0012] In the figure: 1 Xintf interface control line management module, 2 Xintf interface write data management module, 3 Xintf interface read data management module, 4 dual-port RAM module, 5 first DSP chip, 6 second DSP chip, 7 FPGA chip, 8 daughter card. DETAILED DESCRIPTION

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] See also Figure 1-2 , which provides a technical solution for the present invention, a Xintf bus interface controller based on a field programmable gate array, including a dual-port RAM module 4, a DSP chip component, an FPGA chip 7, a Xintf interface control line management module 1, a Xintf interface write data management module 2 and a Xintf interface read data management module 3; the DSP chip component and the FPGA chip 7 are interconnected through a parallel asynchronous bus, the FPGA chip 7 is connected to the Xintf interface control line management module 1, and the FPGA chip 7 is connected to a subcard 8 through the Xintf bus; wherein the parallel asynchronous bus includes a data bus XD, an address bus XA, a read control signal / RD, a write control signal / WR, and a chip select control signal / CS.

[0015] It should be noted that the output end of the DSP chip component is connected to the AD, RAM, and Flash external expansion chips, and the sub-card 8 is accessed by the bus of the DSP chip component, and AD, RAM, and Flash are all one-to-one bus access; the FPGA chip 7 is used to release the sub-card 8 bus to the authorized DSP chip according to the permission status of the DSP chip component to realize the connection of the sub-card 8; the chip select signals of the external expansion chip AD, RAM, Flash, and the sub-card are all controlled by the FPGA chip 7; the DSP chip component mentioned includes a first DSP chip 5 and a second DSP chip 6, and the Xintf bus of the first DSP chip 5 and the second DSP chip 6 are both connected to AD, RAM, Flash and FPGA chip 7, and the Xintf bus includes a data bus, an address bus, a read control signal, a write control signal and a chip select signal; wherein, the logic timing control of the first DSP chip 5 and the second DSP chip 6 is realized by the FPGA chip 7, mainly for the address division control of the external expansion space, the chip select access enable control, and the bus access permission switching control; wherein, the first DSP chip 5 and the second DSP chip 6 adopt but are not limited to the DSP-28335 processor.

[0016] In this embodiment, the Xintf interface control line management module 1 mentioned controls the operation of the DSP chip component, the FPGA chip 7, the Xintf interface read data management module 3 and the Xintf interface write data management module 2 respectively. The Xintf interface read data management module 3 is used to control the DSP chip component to read the data signal and write it into the dual-port RAM module 4, and the Xintf interface write data management module 2 is used to control the DSP chip component's DSP data information to write into the dual-port RAM module 4.

[0017] In this embodiment, the daughter card 8 is a MIL-1394 daughter card, which is connected to the FPGA chip 7 separately and is interconnected with the DSP chip bus with control authority through the internal logic control of the FPGA chip 7.

[0018] The FPGA-based Xintf bus interface controller, the mentioned Xintf interface control line management module 1 realizes the bus control logic of FPGA, Flash, RAM, AD, and MIL-1394 according to the external Xintf bus access address of the FPGA chip 7, and the specific logic is as follows: two-level cache synchronization processing is performed on the chip selection, read, and write signals input externally; each external expansion chip is enabled and controlled according to the chip selection signal; when it is determined to access AD, RAM, and Flash, the FPGA chip 7 releases the bus authority to the first DSP chip 5, the second DSP chip 6, and the peripheral chips Flash, RAM, and AD; when it is determined to access the FPGA chip 7, the FPGA chip 7 obtains the bus response authority; when it is determined to access the MIL-1394 sub-card, the FPGA chip 7 releases the MIL-1394 sub-card bus to the DSP chip component with control authority according to the authority status of the first DSP chip 5 and the second DSP chip 6, so as to realize single access to the MIL-1394 sub-card.

[0019] Among them, the mentioned Xintf interface read data management module 3: for the input read signal, identify the rising edge, generate a write enable B single pulse signal as an enable signal, control the DSP chip component to read data information and write it into the dual-port RAM module 4; if the enable B signal is valid, assign the relevant data register to the variable RAMB according to the Xintf bus interface address and store the data in the Xintf-RAM, including but not limited to AD data and communication data.

[0020] Among them, the mentioned Xintf interface write data management module 2: for the RAMA data write enable signal, identify the rising edge, generate the XintfRam_WEA single pulse signal as the enable signal, and control the DSP data information to be written into the dual-port RAMA; and generate the XintfRam_RDA read signal delayed by two clock cycles to control the FPGA to read the data written into the Xintf-RAM by the DSP; if the XintfRam_RDA read enable signal is valid, read the relevant data from the Xintf-RAMA according to the Xintf bus interface address; Xintf interface dual-port RAM module 4: use the FIFO Generator IP core, dual-port RAM type, 16-bit wide data, 1024 depth.

[0021] In summary: the FPGA-based Xintf bus interface controller has the characteristics of simple circuit and reliability. The main functions are realized by FPGA chip, and the logic control can be adjusted according to the actual application requirements. It has high flexibility, configurability and portability, and has reference significance for bus expansion of other types of processing. Through the flexible allocation of DSP bus access address space, the functional requirements of expanding multiple peripherals are realized, and at the same time, the processing efficiency of bus data is improved through dual-port RAM. In terms of hardware, the DSP, FPGA and other peripheral chips are interconnected through asynchronous bus, and the logic and timing control are carried out through FPGA software to realize the functional expansion of DSP asynchronous bus.

[0022] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0023] The above embodiments only express the preferred implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be understood that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. In the present invention, unless otherwise clearly specified and limited, the terms "installation", "connection", "connection", "fixation" and the like should be understood in a broad sense, for example, it can be a fixed connection, or a detachable connection, or integrated; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components; among them, there are many ways of detachable installation, for example, it can be through the way of plug-in and snap-fit, for example, through the way of bolt connection, etc.

[0024] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A Xintf bus interface controller based on a field programmable gate array, characterized in that: It includes a dual-port RAM module, a DSP chip assembly, an FPGA chip, a Xintf interface control line management module, a Xintf interface write data management module and a Xintf interface read data management module; the DSP chip assembly and the FPGA chip are connected to each other through a parallel asynchronous bus, the FPGA chip is connected to the Xintf interface control line management module, and the FPGA chip is connected to a subcard through the Xintf bus; The output end of the DSP chip assembly is connected to an AD, RAM, and Flash external expansion chip. The daughter card is accessed by the bus of the DSP chip assembly, and AD, RAM, and Flash are all one-to-one bus accesses; the FPGA chip is used to release the daughter card bus to the authorized DSP chip according to the authority status of the DSP chip assembly to realize the daughter card conduction connection; The Xintf interface control line management module controls the operation of the DSP chip component, the FPGA chip, the Xintf interface read data management module and the Xintf interface write data management module respectively. The Xintf interface read data management module is used to control the DSP chip component to read the data signal and write it into the dual-port RAM module, and the Xintf interface write data management module is used to control the DSP chip component's DSP data information to be written into the dual-port RAM module.

2. A Xintf bus interface controller based on a field programmable gate array according to claim 1, characterized in that: The DSP chip assembly comprises a first DSP chip and a second DSP chip, the Xintf buses of the first DSP chip and the second DSP chip are both connected to AD, RAM, Flash and FPGA chips, and the Xintf bus comprises a data bus, an address bus, a read control signal, a write control signal and a chip select signal.

3. A Xintf bus interface controller based on a field programmable gate array according to claim 1, characterized in that: The sub-card adopts a MIL-1394 sub-card, which is connected to the FPGA chip separately and is interconnected with the DSP chip bus with control authority through the internal logic control of the FPGA chip.

4. A Xintf bus interface controller based on a field programmable gate array according to claim 1, characterized in that: The chip selection signals of the external expansion chip AD, RAM, Flash, and daughter card are all controlled by the FPGA chip.

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