Configuration method and system of multi-block cascaded programmable device

Abstract

The invention provides a configuration method and system of a multi-block cascaded programmable device. An external storage device is used for storing configuration code stream files of a plurality of cascaded programmable devices, communication connection is achieved through an SPI communication protocol, a main programmable device can actively read configuration data from the outside and configure the main programmable device at first, and after configuration is completed, subsequent code stream data are sequentially transmitted to a next-level programmable device; and subsequently, the slave programmable devices are configured firstly, and are continuously transmitted to the next stage after the configuration is completed until all the programmable devices are configured. According to the method and the system provided by the invention, downloading configuration code stream files of a plurality of cascaded programmable devices can be realized, the number of the cascaded programmable devices in the system is not limited, and the cascaded programmable devices can be randomly expanded according to application requirements, so that the method and the system have extremely high practical value.

Description

Technical Field

[0001] The present application relates to the field of programmable device design, and in particular to a configuration method and system for a multi-block cascaded programmable device. Background Art

[0002] Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are common large-scale programmable devices whose logic functions can be changed through programming. After being correctly configured and started, they can meet various application requirements.

[0003] Taking FPGA as an example, the programmability of FPGA has significant advantages in hardware acceleration and improving system performance. Therefore, it is widely used in many fields such as data processing centers, medical equipment, AI acceleration, and communication equipment. For complex FPGA application systems, multiple cascaded FPGAs are often required to work together. The step of configuring and starting each FPGA module is essential. If the FPGA is configured one by one, the entire system will become very complicated and cumbersome.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] The object of the present invention is to provide a configuration method and system for multiple cascaded programmable devices, so as to obtain a method for simply and quickly configuring multiple cascaded FPGA, CPLD and other chips based on the standard SPI protocol.

[0006] In order to solve the above problem, in a first aspect, a configuration method of a multi-block cascaded programmable device is provided, comprising a storage device and a multi-block cascaded programmable device, wherein the programmable device comprises a master programmable device and a slave programmable device, and the method comprises the following steps: The storage device stores configuration code stream data corresponding to the connection sequence of the programmable devices; After power-on or power-on reset, the master programmable device reads the configuration code stream data from the storage device, the master programmable device first configures itself according to the read configuration code stream data, and after the configuration is completed, transmits the subsequently read configuration code stream data to the next-level slave programmable device; The slave programmable device first configures itself according to the received configuration code stream data, and after the configuration is completed, transmits the subsequently received configuration code stream data to the next-level slave programmable device until the last-level slave programmable device completes the configuration.

[0007] The method provided by the present invention can realize the cascade download configuration code stream file of multiple programmable devices; there is no limit on the number of cascaded programmable devices, and it can be expanded at will according to application requirements, which has extremely high practical value.

[0008] The configuration code stream data in the storage device is stored in sequence starting from the initial address in the storage device according to the connection order of the programmable devices; the initial address is the 0 address or the preset address of the storage device, which facilitates subsequent reading and reduces the total configuration time of the system.

[0009] The master programmable device determines whether to read the configuration code stream data from the storage device based on the global configuration status signal; when the global configuration status signal indicates that not all programmable devices have completed configuration, the master programmable device continuously reads the configuration code stream data from the storage device; when the global configuration status signal indicates that all programmable devices have completed configuration, the master programmable device stops reading data. The reading timing can be determined autonomously according to the configuration status of the programmable device, and data reading from the outside will automatically stop after all programmable devices are successfully configured, without the need to know the number of cascades in advance.

[0010] The master programmable device determines whether to perform configuration or data transmission based on its own configuration status signal; when its own configuration status signal indicates that the configuration is not completed, it first performs its own configuration according to the configuration code stream data read at this time, and when its own configuration status signal indicates that the configuration is completed, it transmits the configuration code stream data read subsequently to the next level of slave programmable devices. It can determine whether the currently read data is its own code stream file based on its own configuration status signal, ensure that its own configuration is correct, and transmit subsequent data to the corresponding device.

[0011] The slave programmable device determines whether to perform configuration or data transmission based on its own configuration status signal; when its own configuration status signal indicates that the configuration is not completed, it first performs its own configuration according to the received configuration code stream data; when its own configuration status signal indicates that the configuration is completed, it transmits the subsequently received configuration code stream data to the next level of slave programmable devices until the last level of slave programmable devices completes the configuration. It can determine whether the currently received data is its own code stream file based on its own configuration status signal, ensure that its own configuration is correct, and transmit subsequent data to the corresponding device.

[0012] When the master programmable device reads the maximum address in the storage device, the master programmable device stops reading data. When the maximum address is read, the master programmable device automatically stops reading data from the outside, thereby ending the configuration program and indicating that the configuration is not completely successful.

[0013] On the other hand, the present application provides a configuration system for multiple cascaded programmable devices, including a storage device and multiple cascaded programmable devices; The multiple cascaded programmable devices include a master programmable device and at least one slave programmable device connected in serial communication; the master programmable device is connected in communication with the storage device; The storage device is used to store the configuration code stream data of the programmable device; The master programmable device is used to read the configuration code stream data from the storage device, and configure or transmit it to the next level slave programmable device based on its own configuration state; The slave programmable device is used to receive the configuration code stream data, and perform configuration based on its own configuration state or transmit it to the next-level slave programmable device until all programmable devices are configured.

[0014] The method provided by the present invention can realize the cascade downloading configuration code stream file of multiple programmable devices. The number of cascaded programmable devices in the system is not limited and can be expanded at will according to application requirements, which has extremely high practical value.

[0015] The storage device and the programmable device are both provided with an SPI interface, and the SPI interface includes an SCK interface, a CS interface, an SI interface, and an SO interface, and the serial communication connection between the master programmable device and the slave programmable device, and the communication connection between the master programmable device and the storage device are realized through the SPI interface. The universal SPI communication protocol is adopted, and the serial interface signals are less and unified, which can simplify the user's system and device and facilitate debugging.

[0016] Each of the programmable devices is provided with a configuration status signal output interface, and the master programmable device is provided with a global configuration status signal input interface; an AND gate judge is also provided, and the configuration status signal output interfaces of all programmable device chips are connected to the input end of the AND gate judge, and the output end of the AND gate judge is connected to the global configuration status signal input interface of the master programmable device. The global configuration status signal of the system is obtained through the AND gate judge, so as to better judge the timing of reading data.

[0017] The SCK interface of the master programmable device is respectively connected to the SCK interface of the storage device and each of the slave programmable devices; the CS interface of the master programmable device is respectively connected to the CS interface of the storage device and each of the slave programmable devices; the SI interface and SO interface of the master programmable device are respectively connected to the SO interface and SI interface of the storage device; the two adjacent programmable devices are serially connected in sequence through the output interface and the SI interface. The universal SPI communication protocol is adopted, and the serial interface signals are less and unified, which can simplify the user's system and device and facilitate debugging.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include the following: the method and system provided by the present invention do not need to be configured and started one by one like the prior art, and can realize the cascade download of configuration code stream files of multiple programmable devices; a universal SPI communication protocol is adopted, and the serial interface signals are less and unified, which can simplify the user's system and device and facilitate debugging; the number of cascaded programmable devices in the system is not limited and can be expanded at will according to application requirements, which has extremely high practical value; after all programmable devices are configured successfully or when the maximum address is read, they will automatically stop reading data from the outside, and there is no need to know the number of cascades in advance. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 The present invention provides a schematic diagram of the configuration system structure of multiple cascaded programmable devices.

[0021] Figure 2 A schematic diagram of a storage method when the number of configuration code stream data provided by the present invention is three.

[0022] Figure 3 A schematic diagram of a storage method when the number of configuration code stream data provided by the present invention is N. DETAILED DESCRIPTION

[0023] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0024] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0025] The steps in the following embodiments do not correspond one to one with the summary of the invention.

[0026] Embodiment 1 The present invention provides a configuration method and system for a plurality of cascaded programmable devices, comprising a storage device and a plurality of cascaded programmable devices, wherein the programmable devices comprise a master programmable device and a slave programmable device, and the method comprises the following steps: the storage device stores configuration code stream data corresponding to the connection order of the programmable devices; after power-on or power-on reset, the master programmable device reads the configuration code stream data from the storage device, the master programmable device first configures itself according to the read configuration code stream data, and after the configuration is completed, transmits the subsequently read configuration code stream data to the next-level slave programmable device; the slave programmable device first configures itself according to the received configuration code stream data, and after the configuration is completed, transmits the subsequently received configuration code stream data to the next-level slave programmable device, until the last-level slave programmable device completes the configuration.

[0027] It can be understood that, depending on the actual situation, the programmable device can be an FPGA chip, a CPLD chip or other types of chips, and the number of programmable devices can also be determined according to the actual situation. For ease of understanding, in this embodiment, the configuration of three FPGA chips is taken as an example to introduce the configuration system method and structure of multiple cascaded programmable devices.

[0028] Step 1: Provide a storage device and multiple programmable devices, connect them in a SPI daisy chain (SPI_CHAIN) mode and configure them uniformly; like Figure 1 The figure shows a schematic diagram of a configuration system structure of a multi-block cascaded programmable device provided by an embodiment of the present invention. It is worth noting that this embodiment is based on FPGA chip and SPI protocol for communication connection. In other embodiments, other programmable devices and other communication connection methods may also be used, and this is not strictly limited.

[0029] refer to Figure 1 Different from the method of individually configuring each FPGA chip in the traditional technology, the present invention connects three FPGA chips to be configured and started and a storage device (in this embodiment, a Flash chip is used) based on the SPI daisy chain (SPI_CHAIN) method and then configures them uniformly.

[0030] Specifically, firstly, a Flash chip is provided, in which the configuration code stream data corresponding to the three FPGA chips are stored, and then the three FPGA chips to be configured and started are connected to the Flash chip for communication, and the corresponding modes are set.

[0031] It can be understood that the configuration methods of FPGA chips can generally be divided into two categories: active and passive. The active configuration method refers to the FPGA chip as the initiator of the request, actively requesting the external storage or processor to send the configuration code stream data, and the FPGA chip receives the configuration code stream data after requesting it. The passive configuration method refers to the external storage or processor as the active party to send the configuration code stream data, and the FPGA chip as the passive party receives the configuration code stream data. In this embodiment, the first FPGA chip is set to SPI_Master mode (i.e., active configuration mode, hereinafter referred to as the master FPGA chip), and the remaining two are all set to SPI_Slave mode (i.e., passive configuration mode, hereinafter referred to as slave FPGA chips, including slave FPGA chip 1 and slave FPGA chip 2). In other embodiments, depending on the number, the first FPGA chip can be set to SPI_Master mode, and the remaining ones can all be set to SPI_Slave mode.

[0032] In this application, in order to simplify the user's system and device, the cascade and communication connection of multiple FPGA chips are realized based on the universal SPI (Serial Peripheral Interface) communication protocol. SPI communication includes four main signal interfaces, including SO interface and SI interface, which are used to transmit data between the master device and the slave device; SCK (Serial Clock) interface, which is used to transmit the serial clock signal, which is generated by the master device and used to synchronize the data transmission between the master device and the slave device; CS (Chip Select) interface, which is used to transmit the slave device selection signal, which is used by the master device to select a specific slave device for communication. Using the above interface, multiple FPGA chips can be connected in series, and then the main FPGA chip and the external Flash chip can be connected; in addition, each FPGA chip also has a Done_in interface (global configuration status signal input interface) and a Done_out interface (configuration status signal output interface). The Done_out interface is used to output the Done_out signal (i.e., the configuration status signal), which is generated internally by the FPGA chip after the configuration is successfully completed; through an external AND gate judgement, the Done_out signals of all FPGA chips can be AND-judged and input to the Done_in interface of the main FPGA chip.

[0033] refer to Figure 1The specific communication connection method is: connect the SCK interface of the main FPGA chip to the SCK interface of the Flash chip and each slave FPGA chip respectively; connect the CS interface of the main FPGA chip to the CS interface of the Flash chip and each slave FPGA chip respectively; two adjacent FPGA chips are serially connected in sequence through their respective output interfaces (i.e., dout interfaces) and SI interfaces; connect the Done_out interfaces of all FPGA chips to an AND gate judger and connect the other end of the AND gate judger to the Done_in interface of the main FPGA chip; the SPI interface of the main FPGA chip is connected to the SPI interface of the Flash chip, including the SO interface of the Flash chip and the SI interface of the main FPGA chip, and the SI interface of the Flash chip and the SO interface of the main FPGA chip.

[0034] Step 2: Store the configuration code stream data of multiple cascaded FPGA chips into the Flash chip; refer to Figure 2 As shown, the configuration code stream data is stored sequentially from the initial address in the external Flash chip. The order of the configuration code stream data corresponds to the connection order of the FPGA chips, that is, the configuration code stream data 0 of the master FPGA chip is first, followed by the configuration code stream data 1 of the slave FPGA chip 1 connected after the master FPGA chip, and finally the configuration code stream data 2 of the slave FPGA chip 2. It can be understood that, refer to Figure 3 When there are N slave FPGA chips connected, they are also stored in sequence, where the configuration code stream data i corresponds to the configuration code stream data of the slave FPGA chip i.

[0035] It should be noted that, in this embodiment, the initial address is address 0 in the Flash chip, which is convenient for subsequent reading, because the usual reading sequence starts from address 0; in other embodiments, a certain preset address can be agreed upon as the initial address, and address 0 in the Flash chip is not limited to be used as the initial address. It can be understood that the configuration code stream data is usually obtained using the compilation tool EDA.

[0036] Step 3: Power on the system or reset the system after powering on; Step 4: After the reset is released, the main FPGA chip monitors the input Done_in signal and reads the configuration bit stream data; It can be understood that the Done_out signal (i.e., the configuration status signal) is a signal generated inside the FPGA chip to indicate whether the configuration of the FPGA chip is completed. In this embodiment, when the FPGA chip has not completed its own configuration, the Done_out signal is 0 (usually represented by a low level); when the FPGA chip has completed its own configuration, the Done_out signal is 1 (usually represented by a high level).

[0037] The main FPGA chip will always monitor the input Done_in signal (i.e., the global configuration status signal). The Done_in signal is the AND gate judgment result of the Done_out signals of all FPGA chips. That is, only when the Done_out signals of all FPGA chips are 1, the Done_in signal is 1, indicating that all FPGA chips in the system have been successfully configured; when the Done_out signal of any FPGA chip is 0, the Done_in signal is always 0, indicating that not all FPGA chips have been successfully configured.

[0038] It can be understood that after power-on or system reset after power-on, all configurations will be initialized. At this time, if the monitored Done_in signal is 0, the main FPGA chip will actively read the configuration code stream data from the Flash chip.

[0039] Step 5: Perform configuration and data transmission based on the Done_out signal of the main FPGA chip itself; The master FPGA chip will always judge its own Done_out signal. At this time, the Done_in signal is 0 and the Done_out signal is also 0. The master FPGA chip believes that the configuration code stream data read from the Flash chip is its own code stream information. Therefore, it will perform configuration work according to the configuration code stream data read at this time, and in this process, it will always output data 0 to the next-level FPGA chip (i.e., slave FPGA chip 1); when the code stream of the master FPGA chip is successfully configured, the Done_out signal of the master FPGA chip will become 1, that is, the Done_in signal of the master FPGA chip is 0 and the Done_out signal is 1. The master FPGA chip determines that the configuration code stream read from the Flash chip at this time is the code stream of the subsequent FPGA chip, so it passes the read data to the next-level FPGA chip (i.e., slave FPGA chip 1) through the dout interface.

[0040] It can be understood that the FPGA chip can perform pipeline processing, that is, it can read data and perform configuration at the same time. When all the configuration code stream data belonging to itself is read, the corresponding configuration is also completed, so the subsequent data can be sent to the next level FPGA chip.

[0041] Step 6: Perform configuration and data transmission based on the Done_out signal of the slave FPGA chip 1; It can be understood that the structure of the configuration code stream data usually includes a synchronization header, code stream data, and CRC check bits. Therefore, when the slave FPGA chip 1 receives data that is not all 0, it means that the data received at this time is the configuration code stream data, and the slave FPGA chip 1 will judge its own Done_out signal to confirm whether the data is its own configuration code stream data. If its Done_out signal is 0, the slave FPGA chip 1 believes that the input configuration code stream data is its own code stream information. The slave FPGA chip 1 will receive the configuration code stream data and perform configuration work at the same time, and in the process, it will always output data 0 to the next level FPGA chip (i.e., the slave FPGA chip 2); when the code stream of the slave FPGA chip 1 is successfully configured, the Done_out signal of the slave FPGA chip 1 will become 1, and the slave FPGA chip 1 will determine that the configuration code stream received at this time is the code stream of the subsequent FPGA chip, so the read data will be passed to the next level FPGA chip (i.e., the slave FPGA chip 2) through the dout interface.

[0042] Step 7: Subsequent slave FPGA chips will perform the same processing as slave FPGA chip 1 until the last slave FPGA chip.

[0043] It can be understood that when slave FPGA chip 2 receives data that is not all 0, slave FPGA chip 2 will begin to continuously judge its own Done_out signal. If the Done_out signal is 0, it will receive the configuration code stream data and perform configuration work at the same time, and in this process, it will continue to output data 0 to the next-level FPGA chip (assuming that the next-level FPGA chip is still connected); when the code stream of slave FPGA chip 2 is successfully configured, the Done_out signal of slave FPGA chip 2 will become 1, then slave FPGA chip 2 will determine that the configuration code stream received at this time is the code stream of the subsequent FPGA chip, and therefore the read data will be passed to the next-level FPGA chip through delivery.

[0044] In other embodiments, if there are N slave FPGA chips in the system, the above steps will be repeated until the configuration code stream data is transmitted to the last FPGA chip, ie, slave FPGA chip N.

[0045] Step 8: The last FPGA chip is configured based on its own Done_out signal.

[0046] In this embodiment, the last-level FPGA chip is the slave FPGA chip 2. When the slave FPGA chip 2 receives data that is not all 0, the slave FPGA chip 2 will start to judge its Done_out signal. If the Done_out signal is 0, it will receive the configuration code stream data and perform configuration work at the same time; when the code stream of the slave FPGA chip 2 is successfully configured, the Done_out signal of the slave FPGA chip 2 will become 1. At this time, the Done_out signals output by all FPGA chips are 1, and the Done_in signal received by the master FPGA chip will also become 1, indicating that all cascaded FPGA chips are successfully configured, and the master FPGA chip also stops reading data from the external Flash chip. That is, when the Done_in signal received by the master FPGA chip is 1, it indicates that the configuration of the system is completed and the configuration is successful.

[0047] It can be understood that in other embodiments, if there are N slave FPGA chips in the system, this step is performed by slave FPGA chip N.

[0048] Step 9: When the main FPGA chip reads the maximum address, it will also stop reading data.

[0049] On the other hand, if an error occurs in the above steps, the Done_in signal received by the main FPGA chip is always 0, and the main FPGA chip will continue to fetch data from the Flash chip. When the maximum address of the Flash chip is read, if the Done_in signal received by the main FPGA chip is still 0, it will stop reading data. In this case, it indicates that the system configuration is over and the configuration fails. Therefore, subsequent corresponding troubleshooting is required.

[0050] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0051] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A configuration method for a multi-block cascaded programmable device, comprising a storage device and a multi-block cascaded programmable device, wherein the programmable device comprises a master programmable device and a slave programmable device, characterized in that: The method comprises the following steps: The storage device stores configuration code stream data corresponding to the connection sequence of the programmable devices; After power-on or power-on reset, the master programmable device reads the configuration code stream data from the storage device, the master programmable device first configures itself according to the read configuration code stream data, and after the configuration is completed, transmits the subsequently read configuration code stream data to the next-level slave programmable device; The slave programmable device first configures itself according to the received configuration code stream data, and after the configuration is completed, transmits the subsequently received configuration code stream data to the next-level slave programmable device until the last-level slave programmable device completes the configuration.

2. A configuration method for a multi-block cascaded programmable device according to claim 1, characterized in that: The configuration code stream data in the storage device is stored sequentially starting from the initial address in the storage device according to the connection order of the programmable devices; The initial address is address 0 or a preset address of the storage device.

3. The configuration method of a multi-block cascaded programmable device according to claim 1, characterized in that: The master programmable device determines whether to read the configuration code stream data from the storage device based on the global configuration status signal; When the global configuration status signal indicates that not all programmable devices have completed configuration, the master programmable device continuously reads the configuration code stream data from the storage device; When the global configuration status signal indicates that all programmable devices have completed configuration, data reading stops.

4. A configuration method for a multi-block cascaded programmable device according to claim 3, characterized in that: The master programmable device determines whether to perform configuration or data transmission based on its own configuration status signal; When its own configuration status signal indicates that configuration is not completed, it first configures itself according to the configuration code stream data read at this time. When its own configuration status signal indicates that configuration is completed, the configuration code stream data read subsequently is transmitted to the next-level slave programmable device.

5. A configuration method for a multi-block cascaded programmable device according to claim 4, characterized in that: The slave programmable device determines whether to perform configuration or data transmission based on its own configuration status signal; When its own configuration status signal indicates that the configuration is not completed, it first configures itself according to the received configuration code stream data. When its own configuration status signal indicates that the configuration is completed, the subsequently received configuration code stream data is transmitted to the next level of slave programmable devices until the configuration of the last level of slave programmable devices is completed.

6. The configuration method of a multi-block cascaded programmable device according to claim 1, characterized in that: When the master programmable device reads a maximum address in the storage device, the master programmable device stops reading data.

7. A configuration system for multiple cascaded programmable devices, characterized in that: Includes storage devices and multiple cascaded programmable devices; The multiple cascaded programmable devices include a master programmable device and at least one slave programmable device connected in serial communication; the master programmable device is connected in communication with the storage device; The storage device is used to store the configuration code stream data of the programmable device; The master programmable device is used to read the configuration code stream data from the storage device, and configure or transmit it to the next level slave programmable device based on its own configuration state; The slave programmable device is used to receive the configuration code stream data, and perform configuration based on its own configuration state or transmit it to the next-level slave programmable device until all programmable devices are configured.

8. A configuration system for multiple cascaded programmable devices according to claim 7, characterized in that: The storage device and the programmable device are both provided with an SPI interface, and the SPI interface includes an SCK interface, a CS interface, an SI interface and an SO interface. The serial communication connection between the master programmable device and the slave programmable device, and the communication connection between the master programmable device and the storage device are realized through the SPI interface.

9. A configuration system for multiple cascaded programmable devices according to claim 8, characterized in that: Each of the programmable devices is provided with a configuration status signal output interface, and the master programmable device is provided with a global configuration status signal input interface; An AND gate judger is also provided, and the configuration status signal output interfaces of all programmable devices are connected to the input end of the AND gate judger, and the output end of the AND gate judger is connected to the global configuration status signal input interface of the master programmable device.

10. A configuration system for multiple cascaded programmable devices according to claim 8, characterized in that: The SCK interface of the master programmable device is respectively connected to the storage device and the SCK interface of each of the slave programmable devices; The CS interface of the master programmable device is respectively connected to the storage device and the CS interface of each slave programmable device; The SI interface and the SO interface of the master programmable device are connected to the SO interface and the SI interface of the storage device respectively; The programmable devices of two adjacent stages are serially connected in sequence through the output interface and the SI interface.

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