A power consumption optimization method, integrated circuit and chip

Abstract

The present invention provides a power consumption optimization method, integrated circuit and chip, the method comprising: obtaining a first terminal register with timing violation in a load register based on an EDA timing report; obtaining all first load registers driven by an ICG; obtaining a second terminal register driven by the ICG and limiting the overall performance of the circuit according to the first load register and the first terminal register; dividing each load register into a plurality of logically unrelated register stacks according to combinational logic; and copying an ICG for each register stack to drive the CP end of each load register in the register stack. The solution utilizes the ICG copy function of the EDA tool and realizes the ICG copy and placement of the key registers that affect the overall performance of the circuit, so that the timing of the path between the load registers can be optimized to the extreme without increasing the complexity of the process and maintaining the power consumption of the integrated circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power consumption optimization method, an integrated circuit and a chip. Background Art

[0002] With the continuous development of integrated circuits, not only the requirements for circuit performance are constantly increasing, but also the constraints on power consumption are becoming more and more stringent. In ultra-large-scale integrated circuits, dynamic power consumption, that is, the power consumption caused by the flipping of data and clock signals, accounts for 95% of the overall power consumption, of which the dynamic power consumption on the clock tree accounts for about 35% of the total dynamic power consumption. If a part of the functional circuit in the entire design does not need to work for a period of time, this means that the data signal of the data port (D end) of the register will not flip, and the clock signal of the clock port (CP end) of the register does not need to flip, so the clock does not flip, and the power consumption caused by the flip on the clock tree can be avoided.

[0003] However, as the scale of integrated circuit design itself becomes larger and larger, the functions of sub-module circuits become more complex, and the number of load registers in module circuits increases. How to control so many load registers to avoid power consumption caused by signal flipping becomes an urgent problem to be solved. Summary of the invention

[0004] The purpose of the present invention is to provide a power consumption optimization method, an integrated circuit and a chip. By utilizing the ICG copy function of an EDA tool and realizing ICG copy and placement of key registers that affect the overall performance of the circuit, the timing of the path between load registers can be optimized to the extreme without increasing the complexity of the process and maintaining power consumption of the integrated circuit, thereby improving chip performance.

[0005] The technical solution provided by the present invention is as follows:

[0006] The present invention provides a power consumption optimization method for timing control of a load register in a submodule circuit of an integrated circuit, comprising the steps of:

[0007] Based on the timing report of the submodule circuit obtained by EDA, obtaining a first endpoint register having a timing violation in the load register;

[0008] Acquire all first load registers driven by the ICG in the load registers;

[0009] According to the first load register and the first endpoint register, obtaining a second endpoint register in the load register that is driven by the ICG and limits the overall performance of the circuit;

[0010] Respectively obtain load registers having combinational logic with each of the second destination registers, and divide each of the load registers into a plurality of logically independent register stacks according to the combinational logic;

[0011] An ICG is copied for each register file through an EDA tool to drive the CP end of each load register in the register file.

[0012] This scheme obtains the timing report of the sub-module circuit through EDA, and can determine the first terminal register with a timing violation in the load register, and then obtain the second terminal register in the load register that is driven by ICG and limits the overall performance of the circuit by determining all the first load registers in the load register. According to the logical relationship, the load register with combinational logic with the second terminal register can be found, and each load register can be divided into a number of logically unrelated register stacks. By copying an ICG for each register stack to drive the CP end of each load register in the register stack, the starting register and the terminal register that are logically connected and on the critical path can share an ICG as much as possible, thereby reducing the need to consider additional pessimism on the clock tree caused by premature clock bifurcation due to non-sharing of ICG, thereby improving the timing performance of the critical path and improving the performance of the entire chip.

[0013] In some implementations, respectively acquiring a load register having a combinational logic with each of the second destination registers further includes:

[0014] A starting point register located at a logical starting point among the load registers having combinational logic with each of the second end point registers is obtained.

[0015] In some implementations, the copying of an ICG for each register file by an EDA tool further includes:

[0016] Calculating the physical center of each of the register files according to the physical distribution range from the starting register to the second end register in each of the register files;

[0017] ICG was placed at the physical center.

[0018] In some implementations, the CP end of each ICG is connected to a clock source, the Q end of each ICG is respectively connected to the CP end of each load register in the corresponding register stack, and the E end of each ICG is used to receive a gating signal.

[0019] In some implementations, the method further includes: according to preset conditions, performing ICG replication for other load registers in the first load register that do not belong to each of the register files through an EDA tool, so that multiple of the other load registers are driven by one ICG.

[0020] In some implementations, the preset condition is the physical distribution of the other load registers and the number of drivers of each ICG.

[0021] In some implementations, an intersection operation is performed on the first load register and the first destination register to obtain the second destination register in the load register that is driven by the ICG and limits the overall performance of the circuit.

[0022] In some implementations, after dividing each of the load registers into a plurality of logically independent register files according to combinational logic, the method further includes:

[0023] Re-acquire the timing report of the submodule circuit, and determine whether the timing of the load registers having the combinational logic in each of the register files is accurate, and re-divide the register files if the determination is no.

[0024] In a second aspect, the present application provides an integrated circuit, which uses the power consumption optimization method described in the first aspect to perform timing control of a load register in a sub-module circuit.

[0025] In a third aspect, the present application provides a chip including the integrated circuit described in the second aspect.

[0026] According to a power consumption optimization method, integrated circuit and chip provided by the present invention, by utilizing the ICG copy function of the EDA tool and realizing the ICG copy and placement of key registers that affect the overall performance of the circuit, the timing of the path between load registers can be optimized to the extreme without increasing the complexity of the process and maintaining power consumption of the integrated circuit, thereby improving chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0028] Figure 1 is a schematic diagram of the control structure of the clock gating unit of the present invention;

[0029] Figure 2 is a waveform diagram of a clock signal of a clock gating unit of the present invention being turned off;

[0030] Figure 3 It is a schematic diagram of ICG control of the present invention;

[0031] Figure 4 It is a schematic diagram of the data path and clock path from the gate control register to the ICG;

[0032] Figure 5 It is a schematic diagram of a circuit after ICG replication in the prior art;

[0033] Figure 6 It is a schematic diagram of the shortcomings of ICG after replication in the prior art;

[0034] Figure 7 It is a schematic diagram of a power consumption optimization method according to an embodiment of the present invention;

[0035] Figure 8 is a schematic diagram of register file partitioning according to an embodiment of the present invention;

[0036] Fig. 9 1 is a schematic diagram of a circuit after ICG replication according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0038] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0039] With the continuous development of integrated circuits, not only the requirements for circuit performance are constantly increasing, but also the constraints on power consumption are becoming more and more stringent. In ultra-large-scale integrated circuits, dynamic power consumption, that is, the power consumption caused by the flipping of data and clock signals, accounts for 95% of the overall power consumption, of which the dynamic power consumption on the clock tree accounts for about 35% of the total dynamic power consumption. If a part of the functional circuit in the entire design does not need to work for a period of time, this means that the data signal of the data port (D end) of the register will not flip, and the clock signal of the clock port (CP end) of the register does not need to flip, so the clock does not flip, and the power consumption caused by the flip on the clock tree can be avoided.

[0040] Reference Manual Attached Figure 1, by using the gating control signal generated by the gating control logic of the gating unit to enter the E end of the gating unit (ICG), the clock sent from the clock source (clock port) is turned off and converted into a shut-off clock, and then this shut-off clock is used as the clock input (clock pin) of the sub-module, so that the clock signal of the clock port (CP end) of the register will not flip.

[0041] The meaning of shutdown is Figure 2 As shown, the clock signal that flips every cycle becomes a fixed 0, so that the CP end of the device (Buffer) and register (REGS) on the clock tree will not flip, which reduces power consumption. The control logic of the gating unit itself is also built by registers. By detecting that the sub-module does not need to work, the gating control signal is set to 0, so that the clock after the gating unit can be turned off.

[0042] Figure 1 The detailed description of the structure is as follows Figure 3 As shown, the register in the submodule circuit is called a load register, and the register that controls the logic of the ICG / E port is called a gate control register.

[0043] However, as the scale of integrated circuit design itself becomes larger and larger, the functions of submodule circuits become more complex, and the number of load registers in the module circuit increases. In order to establish a clock tree from ICG / Q to the CP end of all load register groups, the required clock tree delay is large, and the delay from the clock source to ICG / CP is small. However, the gate control register may be distributed in the load register group, so the delay from the clock source to the CP of the gate control register is large, and the data delay from the gate control register to ICG / E is also large. Figure 4 As shown, the transmit clock path delay is long, the transmit data path delay is long, but the capture clock path delay is long. According to the definition of setup time, the setup time from the gating control register to ICG is prone to problems and does not meet the performance requirements of the circuit.

[0044] Meanwhile, in the prior art, in order to solve the ICG allocation problem when the number of load registers is large, a common method is to use EDA tools to automatically copy the ICG. Figure 5As shown in the figure, ICG is copied into ICG_CP1 and ICG_CP2, and the E end of the copied ICG is connected to the original gate control signal, that is, the conditions for ICG to be turned off are the same, and the function of the circuit is not changed. However, ICG_CP1 and ICG_CP2 can control a part of the load registers respectively, as shown in the figure, which splits the load register group A and load register group B. After copying ICG in this way, because the number of load registers behind each ICG is reduced, the clock delay from ICG / Q to the load register is reduced, that is, the clock delay from the clock source to the ICG / CP port is increased, corresponding to Figure 4 The capture clock path delay becomes longer, so it is beneficial to meet the setup time and help improve the performance of the circuit.

[0045] However, the automatic ICG replication of the tool in the prior art is mainly based on the physical distribution position of the load register to perform ICG replication. At the same time, since the EDA tool adopts a heuristic algorithm, the ICG replication scheme has a certain degree of randomness. Figure 6 As shown, in a random ICG replication scheme, registers that are physically close to each other but have no logical interaction with each other may be allocated under the same ICG, such as registers within load register group B / A have no logical interaction with each other, but there is a logical interaction between load register group B and load register group A. In addition, in the timing check of digital integrated circuits, because the clock path from ICG_CP2 / CP to load register group B (transmit clock path) and the clock path from ICG_CP1 / CP to load register group A (capture clock path) are physically located at different locations, their Voltage / Temperature / Process conditions are different. The worst case is that all devices on the transmit clock path are in slower process conditions, lower voltage and higher temperature, while all devices on the capture clock path are in faster process conditions, higher voltage and normal temperature, resulting in a large delay on the transmit clock path and a small delay on the capture clock path. In order to cover such actual scenarios, it is necessary to multiply the delay of the transmit clock path by a coefficient greater than 1 and the delay of the capture clock path by a coefficient less than 1, that is, to increase the delay of the transmit clock path and reduce the delay of the capture clock, so that the timing performance from register group B to register group A will be poor. However, if the critical path from register group B to register group A is difficult to meet the timing requirements, then such a path will become the bottleneck for improving the performance of the entire chip.

[0046] In order to solve this problem, the application will share an ICG as much as possible for the logically connected start register and the end register of the critical path, so that their shared paths will not be under different voltages / temperatures / processes, and there is no need to multiply additional pessimistic coefficients to cover such scenarios, which is helpful for overall timing improvement. The following is a detailed description of this solution in conjunction with the accompanying drawings:

[0047] In one embodiment, the reference specification Figure 7 The present invention provides a power consumption optimization method for timing control of a load register in a submodule circuit of an integrated circuit, comprising the steps of:

[0048] S100 , based on the timing report of the submodule circuit obtained by EDA, obtain a first destination register having a timing violation in the load register.

[0049] Timing violation refers to the situation in digital circuit design where the signal cannot meet the timing constraints, which usually occurs when the clock frequency is too high or the data path delay is too long. Timing violations are mainly divided into the following types: Setup Time violation: data fails to stabilize before the clock edge arrives, resulting in the possibility of data being captured incorrectly; Hold Time violation: data changes too quickly after the clock edge, resulting in the possibility of data being captured incorrectly; Multi-cycle path violation: the delay of some paths exceeds one clock cycle; Cross-clock domain violation: signal transmission between clock domains of different frequencies or phases does not meet the timing requirements. In the current design without clock tree, the timing report of the sub-module circuit of the designed integrated circuit can be automatically generated based on EDA to find the end registers with timing violations in each load register. These end registers are the most critical end registers for timing that limit the overall performance (which can be expressed as VIO_END_REGS).

[0050] S200, obtaining all first load registers driven by ICG in the load registers. Specifically, the basic commands provided by EDA can be used to find all load registers driven by ICG in the load registers (which can be expressed as ICG_LOAD_REGS).

[0051] S300, according to the first load register and the first destination register, obtaining a second destination register in the load register that is driven by the ICG and limits the overall performance of the circuit.

[0052] In a specific implementation, the second endpoint register (which may be expressed as VIO_ICG_LOAD_END_REGS) driven by the ICG and limiting the overall performance of the circuit may be obtained by performing an intersection operation on the first load register and the first endpoint register.

[0053] S400, respectively obtain load registers that have combinational logic with each second destination register, and divide each load register into a plurality of logically independent register stacks according to the combinational logic.

[0054] In a specific implementation, respectively obtaining the load registers that have combinational logic with each second end register further includes: obtaining the starting register (which can be expressed as VIO_ICG_LOAD_START_REGS) located at the logical starting point among the load registers that have combinational logic with each second end register VIO_ICG_LOAD_END_REGS. Divide each load register into a plurality of logically unrelated register stacks according to the combinational logic, such as Figure 8 shown.

[0055] S500 , using an EDA tool to copy an ICG for each register file to drive the CP end of each load register in the register file.

[0056] like Fig. 9 As shown in the figure, the load registers with combinational logic share one ICG for driving, which can reduce the need to consider additional pessimism on the clock tree caused by premature clock bifurcation due to non-sharing of ICG, thereby improving the timing performance of the critical path and thus improving the performance of the entire chip. The CP end of each ICG is connected to the clock source, the Q end of each ICG is connected to the CP end of each load register in the corresponding register stack, and the E end of each ICG is used to receive the gating signal.

[0057] This scheme obtains the timing report of the sub-module circuit through EDA, and can determine the first terminal register with a timing violation in the load register, and then obtain the second terminal register in the load register that is driven by ICG and limits the overall performance of the circuit by determining all the first load registers in the load register. According to the logical relationship, the load register with combinational logic with the second terminal register can be found, and each load register can be divided into a number of logically unrelated register stacks. By copying an ICG for each register stack to drive the CP end of each load register in the register stack, the starting register and the terminal register that are logically connected and on the critical path can share an ICG as much as possible, thereby reducing the need to consider additional pessimism on the clock tree caused by premature clock bifurcation due to non-sharing of ICG, thereby improving the timing performance of the critical path and improving the performance of the entire chip.

[0058] In one embodiment, based on the above embodiment, an ICG is copied for each register file through an EDA tool, further comprising:

[0059] According to the physical distribution range from the starting register to the second end register in each register file, the physical center of each register file is calculated; and the ICG is placed at the physical center.

[0060] Specifically, for each register stack, each load register from the starting register VIO_ICG_LOAD_START_REGS_K to the second end register VIO_ICG_LOAD_END_REGS_K will copy a copy of ICG_K through the EDA tool to drive their CP ends. At the same time, according to the physical distribution range from the starting register VIO_ICG_LOAD_START_REGS_K to the second end register VIO_ICG_LOAD_END_REGS_K in the register stack, its physical center is calculated, and ICG_K is placed at the position of this physical center to ensure that all registers in the register stack can share the longest clock length.

[0061] By utilizing the ICG replication function of the EDA tool and implementing ICG replication and placement of key registers that affect the overall performance of the circuit, the timing of the paths between load registers can be optimized to the extreme without increasing the complexity of the process and maintaining power consumption of the integrated circuit, thereby improving chip performance.

[0062] In one embodiment, based on the above embodiment, it further includes: according to preset conditions, ICG replication is performed for other load registers in the first load register that do not belong to each register file through the EDA tool, so that multiple other load registers are driven by one ICG. The preset conditions are the physical distribution of other load registers and the number of drivers for each ICG. The number of drivers for each ICG can be determined by the user and input into the EDA tool before replication.

[0063] Since not all load registers in the sub-module circuit have combinational logic, many load registers are independent. At this time, the conventional EDA replication method can be used to perform ICG replication for these load registers driven by ICG but without combinational logic according to the physical distribution to ensure that all load registers driven by ICG in the sub-module circuit can achieve timing control.

[0064] In one embodiment, based on the foregoing embodiment, after dividing each of the load registers into a number of logically unrelated register stacks according to the combinational logic, it also includes: reacquiring the timing report of the sub-module circuit, and determining whether the timing of the load registers with combinational logic in each register stack is accurate, and re-dividing the register stack when the determination is no, so as to ensure that the combinational logic of the load registers in each register stack is accurate, avoid ICG control errors, and affect circuit performance.

[0065] The power consumption optimization method of the present application can be implemented in the form of a script to be applicable to existing EDA tools. In addition, all replicated ICG_Ks can be set to dont_touch to ensure that the connection relationship of these ICGs will not be changed by the strategy of automatically replicating ICGs by the subsequent tools; at the same time, all replicated ICG_Ks can be set to soft_fixed to ensure that the physical locations of these ICGs will not be moved by the tools.

[0066] In one embodiment, the present application provides an integrated circuit, which uses the power consumption optimization method of the aforementioned embodiment to perform timing control of a load register in a sub-module circuit.

[0067] In one embodiment, the present application provides a chip including the integrated circuit of the aforementioned embodiment.

[0068] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A power consumption optimization method, characterized in that: The timing control of a load register in a submodule circuit of an integrated circuit comprises the steps of: Based on the timing report of the submodule circuit obtained by EDA, obtaining a first endpoint register having a timing violation in the load register; Acquire all first load registers driven by the ICG in the load registers; According to the first load register and the first endpoint register, obtaining a second endpoint register in the load register that is driven by the ICG and limits the overall performance of the circuit; Respectively obtain load registers having combinational logic with each of the second destination registers, and divide each of the load registers into a plurality of logically independent register stacks according to the combinational logic; An ICG is copied for each register file through an EDA tool to drive the CP end of each load register in the register file.

2. The power consumption optimization method according to claim 1, characterized in that: The method of respectively acquiring the load registers having combinational logic with each of the second destination registers further includes: A starting point register located at a logical starting point among the load registers having combinational logic with each of the second end point registers is obtained.

3. The power consumption optimization method according to claim 2, characterized in that: The method of copying an ICG for each register file by using an EDA tool further includes: Calculating the physical center of each of the register files according to the physical distribution range from the starting register to the second end register in each of the register files; ICG was placed at the physical center.

4. The power consumption optimization method according to claim 1, characterized in that: The CP end of each ICG is connected to a clock source, the Q end of each ICG is respectively connected to the CP end of each load register in the corresponding register stack, and the E end of each ICG is used to receive a gating signal.

5. The power consumption optimization method according to claim 1, characterized in that: Also includes: According to preset conditions, ICG replication is performed for other load registers in the first load register that do not belong to each of the register files through an EDA tool, so that multiple other load registers are driven by one ICG.

6. The power consumption optimization method according to claim 5, characterized in that: The preset conditions are the physical distribution of the other load registers and the number of drivers of each ICG.

7. The power consumption optimization method according to claim 1, characterized in that: An intersection operation is performed on the first load register and the first destination register to obtain the second destination register in the load register that is driven by the ICG and limits the overall performance of the circuit.

8. The power consumption optimization method according to claim 1, characterized in that: After dividing each of the load registers into a plurality of logically independent register stacks according to the combinational logic, the method further includes: Re-acquire the timing report of the submodule circuit, and determine whether the timing of the load registers having the combinational logic in each of the register files is accurate, and re-divide the register files if the determination is no.

9. An integrated circuit, characterized in that: The integrated circuit adopts the power consumption optimization method described in any one of claims 1 to 8 to perform timing control of the load register in the sub-module circuit.

10. A chip, characterized in that: Comprising the integrated circuit of claim 9.

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