Array substrate and display module

Abstract

The invention relates to an array substrate and a display module. The array substrate comprises m first data lines, m second data lines and m selection modules, wherein m is a positive integer. The first input ends of the m selection modules are correspondingly connected with m data signal ends of the display driving chip respectively, the second input ends of the selection modules are used for being connected with reset signals, and the two output ends of the selection modules are correspondingly connected with one first data line and one second data line respectively; the selection module is configured to conduct the data signal end to the connected first data line, disconnect the data signal end and the second data line and conduct the reset signal to the connected second data line in a first time period; and in a second time period after the first time period, conducting the data signal end to the connected second data line, and disconnecting the connection between the data signal end and the first data line.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display module. Background Technology

[0002] In the field of display technology, for array substrates, when charging pixels in different columns, data signals need to be sequentially controlled to be connected to pixels in different columns. Therefore, there is a certain time interval between charging pixels in different columns, which reduces the effective charging time of the pixels. Summary of the Invention

[0003] Therefore, it is necessary to provide an array substrate and a display module to solve the problem of reduced effective charging time of pixels.

[0004] In a first aspect, embodiments of this application provide an array substrate, the array substrate comprising:

[0005] There are m first data lines and m second data lines, where m is a positive integer;

[0006] There are m selection modules, the first input terminals of the m selection modules are respectively connected to the m data signal terminals of the display driver chip, the second input terminal of the selection module is used to connect to the reset signal, and the two output terminals of the selection module are respectively connected to a first data line and a second data line;

[0007] The selection module is configured to: in a first time period, connect the data signal terminal to the connected first data line, disconnect the connection between the data signal terminal and the second data line, and connect the reset signal to the connected second data line; in a second time period after the first time period, connect the data signal terminal to the connected second data line and disconnect the connection between the data signal terminal and the first data line.

[0008] Secondly, embodiments of this application also provide a display module, which includes a display panel and an array substrate provided in the first aspect.

[0009] The array substrate provided in this application embodiment has two output terminals of the selection module connected to a first data line and a second data line, respectively. During a first time period, the selection module connects the data signal terminal to the connected first data line and disconnects the connection between the data signal terminal and the second data line, while simultaneously connecting a reset signal to the connected second data line. During a second time period following the first, the selection module connects the data signal terminal to the connected second data line and disconnects the connection between the data signal terminal and the first data line. Therefore, while connecting the data signal to the first data line, the reset signal is simultaneously connected to the second data line, thus reducing the voltage on the second data line. After introducing a data signal to the first data line during the first time period, the data signal can be connected to the second data line during the second time period, significantly improving the time for the first and second data lines to receive data signals, thereby increasing the actual pixel charging time. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of an array substrate in related technologies;

[0011] Figure 2 For the attached Figure 1 Timing diagrams of the corresponding MUX1 signal, MUX2 signal, and scan signal;

[0012] Figure 3 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application;

[0013] Figure 4 One of the timing diagrams of the first strobe signal, the second strobe signal, the third strobe signal, and the first scan signal provided in the embodiments of this application;

[0014] Figure 5 A second timing diagram of the first strobe signal, the second strobe signal, the third strobe signal, and the first scan signal provided in an embodiment of this application;

[0015] Figure 6 The third timing diagram of the first strobe signal, the second strobe signal, the third strobe signal, and the first scan signal provided in the embodiments of this application;

[0016] Figure 7 A schematic diagram of the structure of a selection module provided in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of the structure of a first selection unit in a selection module provided in an embodiment of this application;

[0018] Figure 9 When the duration of the first time period is equal to the duration of the second time period provided in this application embodiment, a timing diagram of the first and second strobe signals accessed by the selection module is provided.

[0019] Figure 10 This is a cross-sectional schematic diagram of the display module provided in an embodiment of this application. Detailed Implementation

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0023] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0024] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0025] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0026] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0027] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0028] As described in the background section, in related technologies, when an array substrate charges a pixel, it needs to sequentially control data signals to be connected to pixels in different columns. Therefore, there is a certain time interval between the charging of pixels in different columns, resulting in a reduction in the effective charging time of the pixels. The inventors discovered that the main reason for this phenomenon is, as detailed in the appendix... Figure 1 and attached Figure 2 , attached Figure 1 A schematic diagram of the array substrate structure in the related technology is shown; Appendix Figure 2 It shows the attached Figure 1 Timing diagrams for the corresponding MUX1, MUX2, and scan signals. (Attached) Figure 1 The diagram uses an array substrate comprising 6 columns of pixels as an example. Each column of pixels receives data signals through the same data line, and each row of pixels receives data signals through the same scan line (see attached diagram). Figure 1 (Not shown in the image) Controlled by a switch transistor, when a scan signal of preset level (Scan) is connected to a scan line, the connection between each row of pixels and its corresponding data line is activated, allowing the pixel to receive the data signal transmitted from the data signal terminal connected to the corresponding data line. Each data line is controlled by a switch transistor to receive the data signal. Specifically, the data line used to connect the data signal to odd-numbered columns of pixels is activated when the switch transistor is connected to the preset level (MUX1) signal. After the scan line receives the preset level (Scan) signal, the data line is activated to connect to the corresponding pixel, thus connecting the data signal to the corresponding pixel. The data line used to connect the data signal to even-numbered columns of pixels is activated when the switch transistor is connected to the preset level (MUX2) signal. After the scan line receives the preset level (Scan) signal, the data line is activated to connect to the corresponding pixel, thus connecting the data signal to the corresponding pixel. In related technologies, the MUX1 and MUX2 signals are turned on sequentially, allowing the corresponding first and second data lines to receive data signals. Before charging a pixel, it is necessary to ensure that the charge retained from the previous row is cleared before connecting the scan signal to establish the connection between the corresponding data line and the pixel. If they are turned on simultaneously or prematurely, and the voltage of the previous row is higher, the voltage retained on the data lines will be charged into the corresponding pixel, preventing the lower effective data of the current row from being charged into the pixel. Therefore, the scan signal and the MUX2 signal need to have a certain interval, as shown in the attached diagram. Figure 2The time interval "g0" in the text causes the actual time for charging the pixel to be compressed.

[0029] Based on the aforementioned technical problems, the inventors discovered that by disconnecting the connection between the data signal terminal and the second data line while simultaneously conducting a reset signal to the connected second data line to reduce the voltage of the second data line, the effective charging time of the pixel can be effectively increased. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the array substrate provided in the embodiments of this application has m selection modules configured with a first input terminal, a second input terminal, and two output terminals. The first input terminal of the selection module is connected to the data signal terminal of the display driver chip, the second input terminal of the selection module is used to connect the reset signal, and the two output terminals of the selection module are respectively connected to a first data line and a second data line. In the first time period, the selection module conducts the data signal terminal to the connected first data line, disconnects the connection between the data signal terminal and the second data line, and conducts the reset signal to the connected second data line. In the second time period after the first time period, the selection module conducts the data signal terminal to the connected second data line and disconnects the connection between the data signal terminal and the first data line. By adopting the above scheme, since the reset signal is simultaneously conducted to the second data line while the data signal is conducted to the first data line, and the voltage of the second data line is reduced, after the data signal is introduced to the first data line in the first time period, the data signal can be conducted to the second data line in the second time period. This significantly improves the time for the first and second data lines to receive the data signal, thereby increasing the actual charging time of the pixel.

[0030] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0031] The array substrate 100 provided in this embodiment includes m first data lines 110, m second data lines 120, and m selection modules 130, where m is a positive integer. The first input terminals of the m selection modules 130 are respectively connected to the m data signal terminals of the display driver chip. The second input terminal of the selection module 130 is used to connect to the reset signal Rest. The two output terminals of the selection module 130 are respectively connected to one first data line 110 and one second data line 120. In the first time period a, the selection module 130 conducts the data signal terminal to the connected first data line 110 and disconnects the connection between the data signal terminal and the second data line 120, and conducts the reset signal Rest to the connected second data line 120. In the second time period b after the first time period a, the data signal terminal is conducted to the connected second data line 120 and disconnects the connection between the data signal terminal and the first data line 110.

[0032] For example, see Appendix Figure 3 , attached Figure 3 This is a schematic diagram of the structure of an array substrate 100 provided in an embodiment of this application, wherein... Figure 3 The example uses m = 2. In practical applications, m can be any other positive integer, and is not limited to the given value. Figure 3 Examples.

[0033] Specifically, the array substrate 100 can be of various types, such as an OLED (Organic Light Emitting Diode), SDL (Source Driver Link), or MUX panel (multiplexed). In this embodiment, the array substrate 100 is illustrated by including at least m first data lines 110, m second data lines 120, and m selection modules 130. In other embodiments, the array substrate 100 may also include structures such as a data driver and a gate driver, enabling the data signal terminal of the data driver, when connected to the selection module 130, to transmit the data signal Data to the corresponding data line input data signal terminal via the selection module 130; and enabling the connection between the input and output terminals of the selection module 130 to be turned on or off when the gate driver outputs a corresponding level strobe signal, provided the gate driver is connected to the controlled terminal of the selection module 130. The array substrate 100 may also be equipped with other necessary functional circuits as needed, and is not limited to the examples described above.

[0034] The first data line 110 is used to transmit the data signal Data from the accessed data signal terminal to the same column of pixels. In the entire array substrate, the first data line 110 can be used to transmit the data signal Data from the accessed data signal terminal to an odd number of columns of pixels. See Appendix for details. Figure 3The same column of pixels can refer to pixels arranged along the first direction, such as A1, A3, A5, and A7. In other embodiments, the first data line 110 can also be used to transmit the data signal Data transmitted from the access data signal terminal to the even-numbered columns of pixels in all pixels. The specific configuration can be flexibly set according to actual needs and is not limited thereto.

[0035] The second data line 120 is used to transmit the data signal Data transmitted from the access data signal terminal to pixels in the same column. In the entire array substrate, the first data line 110 can be used to transmit the data signal Data transmitted from the access data signal terminal to pixels in a different column corresponding to the first data signal Data. For example, the first data line 110 is used to transmit the data signal Data transmitted from the access data signal terminal to odd-numbered columns of pixels, and the second data line 120 is used to transmit the data signal Data transmitted from the access data signal terminal to even-numbered columns of pixels. In another example, the first data line 110 can be used to transmit the data signal Data transmitted from the access data signal terminal to even-numbered columns of pixels, and the second data line 120 is used to transmit the data signal Data transmitted from the access data signal terminal to odd-numbered columns of pixels.

[0036] m first data lines 110 and m second data lines 120 can be used to transmit the data signal Data transmitted from the access data signal terminal to 2m columns of pixels in a one-to-one correspondence.

[0037] Selection module 130 can be any gating module or circuit. Selection module 130 can be configured with multiple controlled terminals, and the gating signals connected to the multiple controlled terminals are used to control the on / off state between the first input terminal of selection module 130 and the first data line 110, the on / off state between the first input terminal of selection module 130 and the second data line 120, and the on / off state between the second input terminal of selection module 130 and the second data line 120, respectively.

[0038] The switching between the corresponding input terminal and the corresponding data line can be controlled based on the level state of the strobe signal. The first time period a and the second time period b can be set through the timing state of the strobe signal. The first time period a and the second time period b can be understood as the duration for which the strobe signal, used to control the connection between the corresponding input terminal and the corresponding data line, remains at a preset level.

[0039] For example, the selection module 130 may have a first controlled terminal, a second controlled terminal, and a third controlled terminal. The first controlled terminal may, upon receiving a low-level first strobe signal MUX1, connect the first input terminal to the first data line 110 to connect the data signal terminal to the connected first data line 110. The first strobe signal MUX1 is continuously low during the first time period a.

[0040] The first controlled terminal can also disconnect the connection between the first input terminal and the first data line 110 when it receives a high-level first strobe signal MUX1, so as to disconnect the connection between the data signal terminal and the first data line 110. The first strobe signal MUX1 is continuously high-level in the second time period b.

[0041] The second controlled terminal can disconnect the connection between the first input terminal and the second data line 120 when it receives the high-level second strobe signal MUX2, thereby disconnecting the connection between the data signal terminal and the second data line 120. The second strobe signal MUX2 is continuously high during the first time period a.

[0042] The second controlled terminal can also connect the connection between the first input terminal and the second data signal line when it receives the low-level second strobe signal MUX2, so as to connect the data signal terminal and the second data line 120. The second strobe signal MUX2 is continuously low in the second time period b.

[0043] When the third controlled terminal receives a low-level third strobe signal MUX3, it can connect the second input terminal and the second data line 120 to conduct the reset signal Rest connected to the second input terminal to the connected second data line 120. The third strobe signal MUX3 is continuously low during the first time period a.

[0044] It is understood that in other exemplary applications, the level states of the first strobe signal MUX1, the second strobe signal MUX2, and the third strobe signal MUX3 when controlling the corresponding input terminal and the corresponding data line to be on or off can also be the opposite of the above examples, and are not limited to the above examples. That is, in other exemplary applications, the first controlled terminal can also connect the first input terminal and the first data line 110 when receiving a high-level first strobe signal MUX1, and disconnect the connection between the first input terminal and the first data line 110 when receiving a low-level first strobe signal MUX1. The second controlled terminal can also disconnect the connection between the first input terminal and the second data line 120 when receiving a low-level second strobe signal MUX2, and connect the connection between the first input terminal and the second data signal Data line when receiving a high-level second strobe signal MUX2. The third controlled terminal can also connect the connection between the second input terminal and the second data line 120 when receiving a high-level third strobe signal MUX3, and the specific settings can be flexibly configured according to actual needs.

[0045] The voltage of the reset signal Rest is lower than or much lower than the voltage of the data signal Data transmitted at the access data signal terminal. Therefore, reducing the voltage in the second data line 120 to the voltage corresponding to the reset signal Rest will not affect the access of the accurate data signal Data.

[0046] In summary, in the array substrate 100 provided in this application embodiment, the two output terminals of the selection module 130 are respectively connected to a first data line 110 and a second data line 120. During the first time period a, the selection module 130 connects the data signal terminal to the connected first data line 110, disconnects the connection between the data signal terminal and the second data line 120, and connects the reset signal Rest to the connected second data line 120. During the second time period b after the first time period a, the selection module 130 connects the data signal terminal to the connected second data line 120 and disconnects the connection between the data signal terminal and the first data line 110. Therefore, while the data signal Data is connected to the first data line 110, the reset signal Rest is connected to the second data line 120 to reduce the voltage on the second data line 120. After the data signal Data is introduced to the first data line 110 in the first time period a, the data signal Data can be connected to the second data line 120 in the second time period b, which significantly improves the time for the first data line 110 and the second data line 120 to access the data signal Data, thereby increasing the actual charging time of the pixel.

[0047] In some embodiments, the array substrate in this embodiment further includes n scan lines and a pixel driving circuit. The n scan lines are connected to the n scan signal terminals of the display driving chip to receive scan signals; n is a positive integer; the n controlled terminals of the pixel driving circuit are respectively connected to the n scan lines, the m first conducting terminals of the pixel driving circuit are connected to the m first data lines, the m second conducting terminals of the pixel driving circuit are connected to the m second data lines, and the n×2m third conducting terminals of the pixel driving circuit are respectively connected to the n×2m pixels.

[0048] The pixel driving circuit is configured to, under the driving action of the scanning signal, conduct the connection between the first data line and the second data line and the corresponding connected pixel during the second time period.

[0049] A scan line is used to connect to a scan signal, which controls the pixel driving circuit to turn on or off the connection between pixels in the same row and their corresponding data lines.

[0050] The n controlled terminals of the pixel driving circuit are respectively connected to the n scan lines to receive the scan signals transmitted by the scan lines. The scan signals received by the n controlled terminals are used to control the on / off of the m first conducting terminals, the m second conducting terminals of the pixel driving circuit and the n×2m third conducting terminals of the pixel driving circuit, thereby controlling the on / off of the first data line, the second data line and the n×2m pixels respectively.

[0051] For example, n×2m pixels are arranged in an array of 2m columns and n rows. The explanation is based on the example of a scan signal connected to a scan line controlling the pixel driving circuit to switch the first row of pixels on and off with their corresponding first and second data lines. See Appendix. Figure 3 The first row of pixels can be understood as the first row of pixels in the first direction—A1, A2, B1, B2. Continuing, the first preset third conducting terminal of the pixel driving circuit is connected to pixel A1, the second preset third conducting terminal of the pixel driving circuit is connected to pixel A2, and the first preset first conducting terminal of the pixel driving circuit is connected to the pixel used to transmit data signals to the first column of pixels (as shown in the attached diagram). Figure 3 The first data line connection of pixels A1, A3, A5, and A7, the first preset second conduction terminal of the pixel driving circuit, and the connection for transmitting data signals to the second column of pixels (as shown in the attached diagram) Figure 3 Taking the second data line connection of pixels A2, A4, A6, and A8 as an example, when the scan line is connected to a scan signal of a preset level, the pixel driving circuit controls the first data line to conduct and connect with pixel A1, and controls the second data line to conduct and connect with pixel A2. Therefore, pixels A1 and A2 can be charged according to the data signals in the corresponding data lines. The scan signal can be continuously at a preset level in the second time period.

[0052] In this embodiment, since the second data line has been stepped down by the reset signal in the first time period, the pixels connected to the second data line can be effectively charged throughout the second time period without needing to set an additional time interval after the first time period to step down the second data line, thus effectively increasing the charging time of the pixels.

[0053] In one embodiment, the pixel driving circuit is further configured to disconnect the connection between the first data line 110 and the second data line 120 and the corresponding connected pixel during a first time period a.

[0054] For example, the following explanations are provided: when the selection module 130 receives a low-level first strobe signal MUX1, it controls the connection between the connected data signal terminal and the connected first data line 110; when the selection module 130 receives a low-level second strobe signal MUX2, it controls the connection between the connected data signal terminal and the connected second data line 120; when the selection module 130 receives a low-level third strobe signal MUX3, it conducts the reset signal Rest to the connected second data line 120; and when the pixel driving circuit receives a low-level first scan signal Scan1, it controls the connection between the connected first data line 110, the second data line 120, and the corresponding connected pixels. See Appendix. Figure 2 and attached Figure 4 , attached Figure 4 One of the timing diagrams for the first strobe signal MUX1, the second strobe signal MUX2, the third strobe signal MUX3, and the first scan signal Scan1 is shown. It can be seen that during the first time period a, disconnecting the connection between the first data line 110 and the second data line 120 and the corresponding connected pixels allows the reset signal Rest to continuously step down the voltage of the second data line 120 during the first time period a, ensuring that the voltage in the second data line 120 is lower than or significantly lower than the voltage of the data signal Data transmitted from the connected data signal terminal. Furthermore, compared to the pixel charging time in related technologies, the duration e1 of the second time period b in this embodiment is also longer than that in the attached diagram. Figure 2 The charging time e0 of the medium-sized pixels can effectively increase the charging time of the pixels.

[0055] For example, in related technologies, the effective enable time of the strobe signal MUX1 is 0.8μs, the effective enable time of the strobe signal MUX2 is 1.4μs, the interval g0 is 0.3μs, and the pixel charging time e0=1.3μs. In this embodiment, if the first time period a is 0.8μs and the second time period b is 1.4μs, in one timing period T, the interval g1=a=0.8μs between the low level of the first scan signal Scan1 and the low level of MUX1, the effective charging time e1 of the pixel can be 1.4μs+Δt, where Δt is the time interval between the first time period a and the second time period b in one timing period T. Therefore, e1 is much larger than e0, and the pixel charging time is significantly increased.

[0056] In one embodiment, the first time period a includes a first sub-time period and a second sub-time period; the pixel driving circuit is further configured to: disconnect the connection between the first data line 110 and the second data line 120 and the corresponding connected pixel during the first sub-time period; and connect the connection between the first data line 110 and the second data line 120 and the corresponding connected pixel during the second sub-time period.

[0057] For example, the following explanations are provided: when the selection module 130 receives a low-level first strobe signal MUX1, it controls the connection between the connected data signal terminal and the connected first data line 110; when the selection module 130 receives a low-level second strobe signal MUX2, it controls the connection between the connected data signal terminal and the connected second data line 120; when the selection module 130 receives a low-level third strobe signal MUX3, it conducts the reset signal Rest to the connected second data line 120; and when the pixel driving circuit receives a low-level first scan signal Scan1, it controls the connection between the connected first data line 110, the second data line 120, and the corresponding connected pixels. See Appendix. Figure 2 and attached Figure 5 , attached Figure 5 The second timing diagram shows the first strobe signal MUX1, the second strobe signal MUX2, the third strobe signal MUX3, and the first scan signal Scan1. It can be seen that in the first sub-period a1 of the first time period, the connection between the first data line 110 and the second data line 120 and the corresponding connected pixels is disconnected, allowing the reset signal Rest to complete the voltage reduction of the second data line 120 within the first sub-period. Compared to the previous embodiment, this extends the pixel charging time in the second sub-period a2 of the first time period. Compared to the pixel charging time in related technologies, the duration e2 of the second time period b in this embodiment is significantly longer than that in the previous embodiment. Figure 2 The charging time e0 of the medium-sized pixels can significantly increase the charging time of the pixels.

[0058] For example, in the related technology, the effective enable time of the strobe signal MUX1 is 0.8μs, the effective enable time of the strobe signal MUX2 is 1.4μs, the interval g0 is 0.3μs, and the pixel charging time e0=1.3μs, which is less than the effective enable time of the strobe signal MUX2 of 1.4μs. In this embodiment, if the first time period a is 0.8μs and the second time period b is 1.4μs and remains unchanged, in one timing period T, the interval g2=a1 between the low level of the first scan signal Scan1 and the low level of MUX1, and the effective charging time e2 of the pixel can be b+Δt+a2, where Δt is the time interval between the first time period a and the second time period b in one timing period T. Therefore, e2 is much greater than e0 and greater than e1 in the previous embodiment, and the pixel charging time is significantly increased.

[0059] In one embodiment, the selection module 130 is further configured to disconnect the connection between the data signal terminal and the first data line 110 and the second data line 120 during the third time period c after the second time period b.

[0060] The pixel driving circuit is also configured to: in the first sub-period c1 of the third time period, conduct the connection between the first data line 110 and the second data line 120 and the corresponding connected pixel; and in the second sub-period c2 of the third time period, disconnect the connection between the first data line 110 and the second data line 120 and the corresponding connected pixel.

[0061] For example, the following explanations are provided: when the selection module 130 receives a low-level first strobe signal MUX1, it controls the connection between the connected data signal terminal and the connected first data line 110; when the selection module 130 receives a low-level second strobe signal MUX2, it controls the connection between the connected data signal terminal and the connected second data line 120; when the selection module 130 receives a low-level third strobe signal MUX3, it conducts the reset signal Rest to the connected second data line 120; and when the pixel driving circuit receives a low-level first scan signal Scan1, it controls the connection between the connected first data line 110, the second data line 120, and the corresponding connected pixels. See Appendix. Figure 6 , attached Figure 6 The third timing diagram shows the first strobe signal MUX1, the second strobe signal MUX2, the third strobe signal MUX3, and the first scan signal Scan1. In this embodiment, in the first sub-period c1 of the third time period, the connection between the first data line 110 and the second data line 120 and the corresponding connected pixels is turned on, so that the pixels can continue to be charged according to the data signal Data in the data lines in the first sub-period c1 of the third time period, further extending the charging time of the pixels (the effective charging time of the pixels is e3).

[0062] For example, in the related technology, the effective enable time of the gating signal MUX1 is 0.8μs, the effective enable time of the gating signal MUX2 is 1.4μs, the interval g0 is 0.3μs, and the pixel charging time e0=1.3μs, which is less than the effective enable time of the gating signal MUX2 of 1.4μs. In this embodiment, if the first time period a is 0.8μs and the second time period b is 1.4μs and remains unchanged, the effective charging time e3 of the pixel in one time period T can be a+b+Δt+c1-g2, g2≤a, where Δt is the time interval between the first time period a and the second time period b in one time period T. Therefore, e3 is much greater than e0, and the pixel charging time is significantly increased.

[0063] In one embodiment, the first data line and the second data line are alternately arranged.

[0064] In this embodiment, the first data line and the second data line are alternately arranged, which can flexibly transmit data signals to pixels located in different columns, effectively reduce interference in the data signal during transmission, and improve signal stability.

[0065] In one embodiment, see Appendix Figure 7 , attached Figure 7 A schematic diagram of the structure of a selection module 130 is shown.

[0066] In this embodiment, each selection module 130 includes a first selection unit 131 and a second selection unit 132.

[0067] The input terminal of the first selection unit 131 is used to connect to a data signal terminal. The first output terminal of the first selection unit 131 is connected to the first data line 110. The second output terminal of the first selection unit 131 is connected to the second data line 120. The first controlled terminal of the first selection unit 131 is used to access the first strobe signal MUX1. The second controlled terminal of the first selection unit 131 is used to access the second strobe signal MUX2.

[0068] The input terminal of the second selection unit 132 is used to receive the reset signal Rest. The output terminal of the second selection unit 132 is connected to the second data line 120 and the second output terminal of the first selection unit 131. The controlled terminal of the second selection unit 132 is used to receive the third strobe signal MUX3.

[0069] The timing of the first strobe signal MUX1 is the same as that of the third strobe signal MUX3, and both the first strobe signal MUX1 and the third strobe signal MUX3 are enabled in the first time period a; the second strobe signal MUX2 is enabled in the second time period b.

[0070] In this embodiment, the timing of the first strobe signal MUX1 and the timing of the third strobe signal MUX3 enable the reset signal Rest to simultaneously step down the voltage of the second data line 120 while transmitting the data signal Data to the first data line 110, thereby increasing the charging time of the pixel.

[0071] In one embodiment, see Appendix Figure 8 , attached Figure 8 A schematic diagram of a first selection unit 131 in a selection module 130 is shown. In this embodiment, the first selection unit 131 includes a first switch 1311 and a second switch 1312.

[0072] The controlled terminal of the first switch 1311 is used to connect to the first gating signal MUX1, the input terminal of the first switch 1311 is used to connect to the data signal terminal, and the output terminal of the first switch 1311 is connected to the first data line 110.

[0073] The controlled terminal of the second switch 1312 is used to connect to the second strobe signal MUX2, the input terminal of the second switch 1312 is used to connect to the data signal terminal, and the output terminal of the second switch 1312 is connected to the second data line 120.

[0074] In this embodiment, the first switch 1311 and the second switch 1312 control the connection and disconnection of the first data line 110 and the data signal terminal, and the second data line 120 and the data signal terminal, respectively, so as to realize independent control of the first data line 110 and the second data line, reduce interference in data transmission, and reduce the flickering of display pixels by finely controlling the connection and disconnection of each data line, thus providing a more stable visual experience.

[0075] In one embodiment, the reset signal includes an equivalent ground signal or an initialization signal; the voltage of the initialization signal is greater than zero and less than the voltage of the second data line.

[0076] For example, the initialization signal can be a signal used in other functional circuits in the array substrate, such as the Vint signal. In other examples, the initialization signal can also be an external power supply signal, as long as the voltage of the initialization signal is greater than zero and less than the voltage of the second data line, and is not limited to the examples above.

[0077] In this embodiment, the reset signal can be an equivalent ground signal. When the reset signal is an equivalent ground signal, the voltage of the second data line can be effectively cleared to zero, preventing it from affecting the data signal transmitted to the subsequent data signal terminal and improving the accuracy of signal transmission. The reset signal can also be an initialization signal with a voltage greater than zero and less than the voltage of the second data line. When the reset signal is an initialization signal with a voltage greater than zero and less than the voltage of the second data line, the voltage of the second data line can be effectively reduced, shortening the time for the second data line to receive the data signal and improving signal transmission efficiency.

[0078] In one embodiment, the duration of the first time period a is less than or equal to the duration of the second time period b.

[0079] For example, see Appendix Figures 4-6 and attached Figure 9 , attached Figures 4-6 The timing diagram shows the selection signal accessed by module 130 when the first time period a is less than the second time period b. (Attached) Figure 9 The timing diagram shows the first strobe signal MUX1 and the second strobe signal MUX2 connected to the selection module 130 when the duration of the first time period a is equal to the duration of the second time period b.

[0080] In this embodiment, when the duration of the first time period a is less than the duration of the second time period b, the time for the second data line 120 to access the data signal Data can be effectively extended, thus extending the pixel charging time. When the duration of the first time period a is equal to the duration of the second time period b, the time for the first data line 110 and the second data line 120 to access the data signal Data can be effectively extended, thus extending the pixel charging time.

[0081] Based on the same concept, this application also provides a display module. Figure 10 A cross-sectional view of the display module 10 provided in the embodiments of this application, exemplarily, as shown below. Figure 10 As shown, the display module 10 includes a display panel 200 and an array substrate 100 as described in any of the above embodiments. Therefore, the display module 10 also has the beneficial effects of the array substrate 100 in the above embodiments. The similarities can be understood by referring to the explanation of the array substrate 100 above, and will not be repeated below.

[0082] The display module provided in this application embodiment can be applied to any display device, such as a mobile phone, or any other electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises: m first data lines and m second data lines, where m is a positive integer; m selection modules, wherein the first input ends of the m selection modules are respectively connected to the m data signal ends of the display driver chip, the second input ends of the selection modules are used to connect a reset signal, and the two output ends of the selection modules are respectively connected to one of the first data lines and one of the second data lines; Wherein, the selection module is configured to: in a first time period, conduct the data signal end to the connected first data line, disconnect the connection between the data signal end and the second data line, and conduct the reset signal to the connected second data line; in a second time period after the first time period, conduct the data signal end to the connected second data line, and disconnect the connection between the data signal end and the first data line.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: n scanning lines, wherein the n scanning lines are correspondingly connected to the n scanning signal terminals of the display driver chip to receive scanning signals; n is a positive integer; a pixel driving circuit, wherein n controlled terminals of the pixel driving circuit are respectively connected to the n scanning lines, m first conducting terminals of the pixel driving circuit are connected to the m first data lines, m second conducting terminals of the pixel driving circuit are connected to the m second data lines, and n×2m third conducting terminals of the pixel driving circuit are respectively connected to n×2m pixels; The pixel driving circuit is configured to: under the driving action of the scanning signal, in the second period, conduct the connection between the first data line and the second data line and the correspondingly connected pixels.

3. The array substrate according to claim 2, characterized in that: The pixel driving circuit is further configured to: in the first period, disconnect the first data line and the second data line from the corresponding pixels.

4. The array substrate according to claim 2, characterized in that: The first period includes a first sub-period and a second sub-period; The pixel driving circuit is also configured to: in the first sub-period, disconnect the first data line and the second data line from the correspondingly connected pixels; and in the second sub-period, connect the first data line and the second data line to the correspondingly connected pixels.

5. The array substrate according to claim 2, characterized in that: The selection module is further configured to: disconnect the data signal terminal from the first data line and the second data line in a third period after the second period; The pixel driving circuit is further configured to: in a first sub-period of the third period, conduct the connection between the first data line and the second data line and the correspondingly connected pixels; In a second sub-period of the third period, the first data line and the second data line are disconnected from the correspondingly connected pixels.

6. The array substrate according to claim 1, characterized in that: The first data lines and the second data lines are arranged alternately.

7. The array substrate according to claim 1, characterized in that: Each of the selection modules comprises: a first selection unit, wherein an input end of the first selection unit is used to connect to one of the data signal ends, a first output end of the first selection unit is connected to the first data line, a second output end of the first selection unit is connected to the second data line, a first controlled end of the first selection unit is used to access a first selection signal, and a second controlled end of the first selection unit is used to access a second selection signal; a second selection unit, wherein an input end of the second selection unit is used to access the reset signal, an output end of the second selection unit is connected to the second data line and the second output end of the first selection unit, and a controlled end of the second selection unit is used to access a third selection signal; The timing of the first selection signal is the same as the timing of the third selection signal, and both the first selection signal and the third selection signal are enabled and valid in the first time period; the second selection signal is enabled and valid in the second time period.

8. The array substrate according to claim 7, characterized in that: The first selection unit comprises: a first switch, wherein a controlled end of the first switch is used to receive the first selection signal, an input end of the first switch is used to connect to the data signal end, and an output end of the first switch is connected to the first data line; A second switch, wherein a controlled end of the second switch is used to access the second selection signal, an input end of the second switch is used to connect to the data signal end, and an output end of the second switch is connected to the second data line.

9. The array substrate according to claim 1 or 7, characterized in that: The reset signal includes an equivalent signal or an initialization signal; a voltage of the initialization signal is greater than zero and less than a voltage of the second data line.

10. The array substrate according to claim 1, characterized in that: The duration of the first time period is less than or equal to the duration of the second time period.

11. A display module, characterized in that: The invention comprises a display panel and an array substrate as claimed in any one of claims 1 to 10.

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