Display panel and display device

Abstract

The embodiment of the invention discloses a display panel and a display device, the display panel comprises a substrate, a gate drive circuit, a plurality of output signal lines and a plurality of auxiliary signal lines, and the substrate is provided with a plurality of pixel circuits arranged in an array; the gate drive circuit is correspondingly connected with the output signal line, and the output signal line is used for outputting a gate control signal generated by the gate drive circuit; the auxiliary signal line is connected between the output signal line and the pixel circuit, and the auxiliary signal line is used for transmitting a grid control signal on the output signal line to the pixel circuit; wherein the auxiliary signal lines and the output signal lines are arranged in different layers, and the impedance of the auxiliary signal lines is smaller than that of the output signal lines. According to the scheme, the transmission voltage drop of the grid control signals is reduced, the consistency of the grid control signals in the edge area and the middle area of the display panel is guaranteed, the display difference between the edge area and the middle area of the display panel is reduced, the display uniformity is improved, and the display effect is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display technology, people have higher and higher requirements on the performance of display panels.

[0003] The display panel generally includes a pixel circuit and a gate driving circuit, and the gate driving circuit is used to output a gate driving signal to the pixel circuit to drive the pixel circuit to work. However, the existing display panel has shortcomings in display effect. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to improve the display effect of the display panel.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising:

[0006] A substrate, on which a plurality of pixel circuits arranged in an array are disposed;

[0007] A gate drive circuit and a plurality of output signal lines, wherein the gate drive circuit is connected to the output signal lines correspondingly, and the output signal lines are used to output gate control signals generated by the gate drive circuit;

[0008] a plurality of auxiliary signal lines, wherein the auxiliary signal lines are connected between the output signal lines and the pixel circuits, and the auxiliary signal lines are used to transmit gate control signals on the output signal lines to the pixel circuits;

[0009] Wherein, at least part of the auxiliary signal lines and the output signal lines are arranged in different layers, and the impedance of the auxiliary signal lines is smaller than the impedance of the output signal lines.

[0010] Optionally, the display panel includes a display area and a non-display area arranged around at least a portion of the display area, the gate driving circuit and the output signal line are located in the non-display area, and the pixel circuit is located in the display area;

[0011] The auxiliary signal line extends from the non-display area to the display area and extends along a first direction in the display area, and the plurality of auxiliary signal lines are arranged along a second direction; wherein the first direction intersects with the second direction;

[0012] Optionally, the plurality of auxiliary signal lines are arranged in the same layer.

[0013] Optionally, the display panel further comprises a plurality of gate control signal lines, the gate control signal lines and the auxiliary signal lines are arranged in different layers, the auxiliary signal lines are connected to the gate control signal lines through line exchange holes, and the gate control signal lines are connected to the pixel circuits;

[0014] Optionally, at least part of the orthographic projection of the auxiliary signal line on the substrate covers at least part of the orthographic projection of the gate control signal line on the substrate, so as to achieve a self-shielding effect of the auxiliary signal line and ensure the stability of the gate control signal transmitted by it;

[0015] Optionally, along the first direction, the length of the auxiliary signal line is greater than the length of the gate control signal line, which is beneficial to reduce the impedance change of the auxiliary signal line at the line switching connection and ensure the uniformity of the impedance of the auxiliary signal line;

[0016] Optionally, the plurality of auxiliary signal lines extend along the first direction and are arranged along a second direction, and the first direction intersects with the second direction;

[0017] Optionally, a plurality of gate control signal lines are arranged in the same layer;

[0018] Optionally, the auxiliary signal line is connected to the output signal line through the line changing hole;

[0019] Optionally, the display panel further includes an active layer, the pixel circuit includes a plurality of transistors, the gate control signal line overlaps with the active layer to form the gate of the transistor, and the auxiliary signal line is connected to the gate of the transistor via the line exchange hole;

[0020] Optionally, between adjacent pixel circuits, the gate control signal line connected to the same auxiliary signal line is an integrated structure or a segmented independent structure.

[0021] Optionally, the display panel includes a first metal layer, a second metal layer and a third metal layer which are sequentially stacked and located on one side of the substrate;

[0022] The output signal line is located in the first metal layer and / or the second metal layer, the gate control signal line is located in the first metal layer, and the auxiliary signal line is located in the third metal layer;

[0023] Optionally, the first metal layer and the second metal layer both include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer that are stacked.

[0024] Optionally, the gate control signal line includes a first gate control signal line, the auxiliary signal line includes a first auxiliary signal line, the output signal line includes a first output signal line, one end of the first auxiliary signal line is connected to the first output signal line via the line changing hole, and the other end of the first auxiliary signal line is connected to the first gate control signal line via the line changing hole;

[0025] The pixel circuit includes a driving transistor and a data writing transistor, the first gate control signal line overlaps with the active layer to form the data writing transistor, and the data writing transistor is connected between the data line and the second electrode of the driving transistor;

[0026] Optionally, the pixel circuit further includes a compensation transistor, the first gate control signal line overlaps the active layer to form the compensation transistor, and the compensation transistor is connected between the gate and the first electrode of the driving transistor;

[0027] Optionally, the pixel circuit further includes a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode of the storage capacitor is connected to a fixed voltage; optionally, the gate of the driving transistor is reused as the first electrode of the storage capacitor.

[0028] Optionally, an orthographic projection of the first auxiliary signal line on the substrate does not overlap with an orthographic projection of the first gate control signal line on the substrate;

[0029] Optionally, the first gate control signal line includes a main body, a first branch and a second branch, the main body extends along a first direction, the first branch extends along a second direction, the second branch extends in the opposite direction of the second direction, the main body overlaps with the active layer to form the data write transistor, the first branch overlaps with the active layer to form the compensation transistor, and the second branch is connected to the first auxiliary signal line through the line change hole.

[0030] Optionally, the orthographic projection of the first auxiliary signal line on the substrate covers at least part of the orthographic projection of the first gate control signal line on the substrate;

[0031] Optionally, the first gate control signal line includes a main body and a first branch portion, the main body extends along a first direction, the first branch portion extends along a second direction, the main body overlaps with the active layer to form the data write transistor, the first branch portion and / or the main body overlap with the active layer to form the compensation transistor, and the main body and / or the first branch portion are connected to the first auxiliary signal line through the line change hole.

[0032] Optionally, the gate control signal line further includes a second gate control signal line, the auxiliary signal line further includes a second auxiliary signal line, the output signal line further includes a second output signal line, one end of the second auxiliary signal line is connected to the second output signal line via the line changing hole, and the other end of the second auxiliary signal line is connected to the second gate control signal line via the line changing hole;

[0033] Optionally, the orthographic projection of the second auxiliary signal line on the substrate covers at least part of the orthographic projection of the second gate control signal line on the substrate;

[0034] Optionally, the display panel further includes a first initialization signal line, and the first initialization signal line and the second auxiliary signal line are arranged in different layers;

[0035] The pixel circuit further includes a first initialization transistor, the second gate control signal line overlaps with the active layer to form the first initialization transistor, and the first initialization transistor is connected between the first initialization signal line and the gate of the driving transistor;

[0036] Optionally, the gate control signal line further includes a third gate control signal line, the auxiliary signal line further includes a third auxiliary signal line, the output signal line further includes a third output signal line, one end of the third auxiliary signal line is connected to the third output signal line via the line changing hole, and the other end of the third auxiliary signal line is connected to the third gate control signal line via the line changing hole;

[0037] The orthographic projection of the third auxiliary signal line on the substrate covers at least part of the orthographic projection of the third gate control signal line on the substrate;

[0038] Optionally, the display panel further includes a second initialization signal line, and the second initialization signal line is arranged on the same layer as the first initialization signal line;

[0039] The pixel circuit further includes a second initialization transistor, the third gate control signal line overlaps with the active layer to form the second initialization transistor, and the second initialization transistor is connected between the second initialization signal line and the light emitting element;

[0040] Optionally, the gate control signal line further includes a light-emitting control signal line, the auxiliary signal line further includes a fourth auxiliary signal line, the output signal line further includes a fourth output signal line, one end of the fourth auxiliary signal line is connected to the fourth output signal line via the line-changing hole, and the other end of the fourth auxiliary signal line is connected to the light-emitting control signal line via the line-changing hole;

[0041] The orthographic projection of the fourth auxiliary signal line on the substrate covers at least part of the orthographic projection of the light emitting control signal line on the substrate;

[0042] Optionally, the display panel further includes a first power line and a second power line, the pixel circuit further includes a first light emission control transistor and a second light emission control transistor, the light emission control signal line overlaps with the active layer to form the first light emission control transistor and the second light emission control transistor respectively, the first light emission control transistor is connected between the first power line and the second electrode of the driving transistor, the second light emission control transistor is connected between the first electrode of the driving transistor and the first electrode of the light emitting element, and the second electrode of the light emitting element is connected to the second power line;

[0043] Optionally, the orthographic projection of the first auxiliary signal line on the substrate is located between the orthographic projection of the second auxiliary signal line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the fourth auxiliary signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the third auxiliary signal line on the substrate.

[0044] Optionally, the display panel further includes an active layer, the pixel circuit includes a plurality of transistors, and the auxiliary signal line overlaps with the active layer to form a gate of the transistor, which can reduce the number of signal lines, thereby optimizing the layout;

[0045] Optionally, the auxiliary signal line is connected to the gate of the transistor.

[0046] According to another aspect of the present invention, a display device is provided. The display device includes the display panel provided by any embodiment of the present invention.

[0047] The technical solution provided by the embodiment of the present invention connects the output signal line and the pixel circuit through an auxiliary signal line to transmit the gate control signal output by the gate driving circuit to the pixel circuit; wherein the impedance of the auxiliary signal line is smaller than the impedance of the output signal line so as to reduce the impedance of the signal line transmitting the gate control signal, thereby facilitating reducing the transmission voltage drop of the gate control signal, facilitating ensuring the consistency of the gate control signal in the edge area and the middle area of ​​the display panel, thereby reducing the display difference between the edge area and the middle area of ​​the display panel, facilitating improving the display uniformity and improving the display effect.

[0048] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 A schematic diagram of a top view structure of a display panel provided by an embodiment of the present invention;

[0051] Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0053] Figure 4 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0054] Figure 5 A schematic diagram of the structure of a pixel circuit provided by an embodiment of the present invention;

[0055] Figure 6 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0056] Figure 7 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0057] Figure 8 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention;

[0058] Fig. 9 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0059] Fig.10 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0060] Fig.11 A waveform diagram of a gate control signal provided in the prior art;

[0061] Fig.12 A waveform diagram of a gate control signal provided by an embodiment of the present invention;

[0062] Fig.13 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention;

[0063] Fig.14A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0065] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0066] Figure 1 A schematic diagram of a top view of a display panel provided by an embodiment of the present invention is shown. Figure 2 A schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present invention, specifically: Figure 1 The cross-sectional structure of the display panel shown along the cutting line AA' is shown in FIG. Figure 1 and Figure 2 , the display panel provided in this embodiment includes:

[0067] A substrate 10, on which a plurality of pixel circuits PX arranged in an array are disposed;

[0068] A gate drive circuit GD and a plurality of output signal lines 100, the gate drive circuit GD is connected to the output signal lines 100 correspondingly, and the output signal lines 100 are used to output gate control signals generated by the gate drive circuit GD;

[0069] A plurality of auxiliary signal lines 200 (such as Figure 1 The auxiliary signal line 200 is connected between the output signal line 100 and the pixel circuit PX, and the auxiliary signal line 200 is used to transmit the gate control signal on the output signal line 100 to the pixel circuit PX;

[0070] At least part of the auxiliary signal lines 200 and the output signal lines 100 are disposed in different layers, and the impedance of the auxiliary signal lines 200 is smaller than the impedance of the output signal lines 100 .

[0071] The inventors have found through long-term research in the process of realizing the present invention that in the prior art, the gate drive circuit GD is connected to the pixel circuit PX through the output signal line 100, and the gate drive circuit GD transmits the gate control signal to the pixel circuit PX through the output signal line 100 to drive the pixel circuit PX to work. However, on medium and large-sized display panels, the length of the output signal line 100 is relatively long. When the gate control signal is transmitted from the edge of the panel to the middle, the gate control signal at the edge and the middle of the panel is inconsistent due to the excessive transmission voltage drop, resulting in differences in display effects between the edge area and the middle area, reducing the display uniformity of the display panel.

[0072] In the present embodiment, the display panel further includes auxiliary signal lines 200, and a plurality of auxiliary signal lines 200 are arranged along the second direction Y and extend along the first direction X, the first direction X intersects with the second direction Y, and are both perpendicular to the thickness direction Z of the display panel. The auxiliary signal lines 200 are used to connect the output signal lines 100 and the pixel circuits PX, and transmit gate control signals to the pixel circuits PX through the auxiliary signal lines 200. The auxiliary signal lines 200 and the output signal lines 100 are arranged in different layers, such as the auxiliary signal lines 200 can be connected to the output signal lines 100 through vias, and connected to the pixel circuits PX through vias. An insulating layer is provided between the auxiliary signal lines 200 and the output signal lines 100 to isolate the auxiliary signal lines 200 from the output signal lines 100.

[0073] Furthermore, since the auxiliary signal line 200 and the output signal line 100 are located in different film layers, the auxiliary signal line 200 and the output signal line 100 may be set to have different impedances. Here, the impedance of the auxiliary signal line 200 is designed to be smaller than the impedance of the output signal line 100, and the auxiliary signal line 200 with a smaller impedance is used to transmit the gate control signal to the pixel circuit PX in the plane, which can reduce the transmission voltage drop of the gate control signal, thereby facilitating the consistency of the gate control signal in the edge area and the middle area of ​​the display panel, thereby reducing the display difference between the edge area and the middle area of ​​the display panel, and facilitating the improvement of display uniformity.

[0074] The technical solution provided by the embodiment of the present invention connects the output signal line 100 and the pixel circuit PX through the auxiliary signal line 200 to transmit the gate control signal output by the gate driving circuit GD to the pixel circuit PX; wherein the impedance of the auxiliary signal line 200 is smaller than the impedance of the output signal line 100, so as to reduce the impedance of the signal line transmitting the gate control signal, thereby facilitating the reduction of the transmission voltage drop of the gate control signal, facilitating the consistency of the gate control signal in the edge area and the middle area of ​​the display panel, thereby reducing the display difference between the edge area and the middle area of ​​the display panel, and facilitating the improvement of the display uniformity and the display effect.

[0075] Figure 3 A schematic diagram of a top view of another display panel provided in an embodiment of the present invention, referring to Figure 1 and Figure 3 On the basis of the above embodiments, optionally, the display panel includes a display area AA and a non-display area NA arranged around at least a portion of the display area AA, the gate drive circuit GD and the output signal line 100 are located in the non-display area NA, and the pixel circuit PX is located in the display area AA; the auxiliary signal line 200 extends from the non-display area NA to the display area AA, and extends along the first direction X in the display area AA, and a plurality of auxiliary signal lines 200 are arranged along the second direction Y.

[0076] The number of gate drive circuits GD may be multiple. For example, the gate drive circuit GD includes two, namely, a first gate drive circuit 1 and a second gate drive circuit 2. The output signal line 100 includes a first output signal line 101 and a second output signal line 102. The first gate drive circuit 1 transmits a first gate control signal through the first output signal line 101. The first output signal line 101 is connected to the first auxiliary signal line 201 ( Figure 3 The first gate control signal on the first output signal line 101 is transmitted to the pixel circuit PX of the display area AA via the first auxiliary signal line 201. The impedance of the first auxiliary signal line 201 is smaller than the impedance of the first output signal line 101, so as to reduce the transmission voltage drop of the first gate control signal.

[0077] The second gate driving circuit 2 transmits a second gate control signal through the second output signal line 102. The second output signal line 102 is connected to the second auxiliary signal line 202 ( Figure 3 The second gate control signal on the second output signal line 102 is transmitted to the pixel circuit PX of the display area AA via the second auxiliary signal line 202. The impedance of the second auxiliary signal line 202 is smaller than the impedance of the second output signal line 102 to reduce the transmission voltage drop of the second gate control signal.

[0078] It should be noted that each gate driving circuit GD can adopt a left-right simultaneous driving method to meet the driving requirements of medium and large-sized display panels.

[0079] Optionally, a plurality of auxiliary signal lines 200 are disposed on the same layer, for example, a first auxiliary signal line 201 and a second auxiliary signal line 202 are disposed on the same layer.

[0080] Optionally, the display panel further includes a plurality of gate control signal lines, the gate control signal lines and the auxiliary signal lines 200 are arranged in different layers, the auxiliary signal lines 200 are connected to the gate control signal lines through line switching holes, and the gate control signal lines are connected to the pixel circuits PX. Figure 4 A schematic diagram of a top view of another display panel provided in an embodiment of the present invention, referring to Figure 4 The gate control signal line includes a first gate control signal line 301, one end of the first auxiliary signal line 201 is connected to the first output signal line 101 through a line change hole, and the other end of the first auxiliary signal line 201 is connected to the first gate control signal line 301 through a line change hole.

[0081] The display panel further includes an active layer, the pixel circuit PX includes a plurality of transistors, the gate control signal line overlaps the active layer to form the gate of the transistor, and the auxiliary signal line 200 is connected to the gate of the transistor via a line exchange hole. Figure 5 A schematic diagram of a pixel circuit according to an embodiment of the present invention is provided. Figure 5 The pixel circuit PX includes a driving transistor Q1 and a data writing transistor Q2. The data writing transistor Q2 is connected between the data line and the driving transistor Q1 and is used to transmit the data voltage Vdata on the data line to the driving transistor Q1.

[0082] Optionally, the pixel circuit PX further includes a compensation transistor Q3 connected between the gate and the first electrode of the driving transistor Q1, and the data writing transistor Q2 is connected to the second electrode of the driving transistor Q1. The compensation transistor Q3 is used to compensate for the threshold voltage of the driving transistor Q1.

[0083] Specifically, the first gate control signal line 301 overlaps with the active layer 11 to form a data write transistor Q2 and a compensation transistor Q3 (the compensation transistor Q3 can be a dual-gate transistor), and the first auxiliary signal line 201 can transmit the first scan signal S1 on the first output signal line 101 to the first gate control signal line 301 to drive the data write transistor Q2 and the compensation transistor Q3.

[0084] Exemplarily, the first gate control signal line 301 includes a main body 311, a first branch 312 and a second branch 313, the main body 311 extends along the first direction X, the first branch 312 extends along the second direction Y, and the second branch 313 extends in the opposite direction of the second direction Y. The main body 311 overlaps with the active layer 11 to form a data writing transistor Q2, the first branch 312 overlaps with the active layer 11 to form a compensation transistor Q3, and the second branch 313 is connected to the first auxiliary signal line 201 through a line exchange hole.

[0085] Optionally, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 does not overlap with the orthographic projection of the first gate control signal line 301 on the substrate 10, which is conducive to improving the flexibility of wiring. The first auxiliary signal line 201 includes a first sub-segment 211 extending in the opposite direction of the second direction Y in the non-display area NA, and a second sub-segment 212 extending from the non-display area NA to the display area AA along the first direction X; the first sub-segment 211 is used to connect to the first output signal line 101, and the second sub-segment 212 is used to connect to the first gate control signal line 301, which can be specifically the first scan line 301.

[0086] Of course, in other embodiments, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 overlaps with the orthographic projection of at least part of the first gate control signal line 301 on the substrate 10, such as Figure 6 As shown, Figure 6 A schematic diagram of a top view of another display panel provided by an embodiment of the present invention. Figure 6 The first gate control signal line 301 includes a main body 311 and a first branch 312. The main body 311 extends along the first direction X, and the first branch 312 extends along the second direction Y. The main body 311 overlaps with the active layer 11 to form a data writing transistor Q2. The first branch 312 and / or the main body 311 overlap with the active layer 11 to form a compensation transistor Q3 (the compensation transistor Q3 may be a dual-gate transistor). The main body 311 and / or the first branch 312 are connected to the first auxiliary signal line 201 through the line exchange hole. Since the first auxiliary signal line 201 is connected to the first scanning signal S1, and the first auxiliary signal line 201 is connected to the first gate control signal line 301, the potentials of the first auxiliary signal line 201 and the first gate control signal line 301 are not floating. The first auxiliary signal line 201 shields the first gate control signal line 301, which can play a role of self-shielding of the first auxiliary signal line 201, thereby preventing the transmitted first scanning signal S1 from being disturbed and fluctuating. In addition, by overlapping the orthographic projection of the first auxiliary signal line 201 on the substrate 10 with the orthographic projection of at least part of the first gate control signal line 301 on the substrate 10 , the wiring space of the first auxiliary signal line 201 and the layout area can be saved.

[0087] Optionally, the pixel circuit PX further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the gate of the driving transistor Q1, a second electrode of the storage capacitor C1 is connected to a fixed voltage, and the gate of the driving transistor Q1 is multiplexed as the first electrode of the storage capacitor C1.

[0088] Continue to refer Figure 4 On the basis of the above embodiments, the gate control signal line also includes a second gate control signal line 302, one end of the second auxiliary signal line 202 is connected to the second output signal line 102 via a line switching hole, and the other end of the second auxiliary signal line 202 is connected to the second gate control signal line 302 via a line switching hole.

[0089] Specifically, combined Figure 5 , the second output signal line 102 is connected to the second auxiliary signal line 202, and the second scan signal S2 on the second output signal line 102 is transmitted to the first initialization transistor Q4 in the pixel circuit PX via the second auxiliary signal line 202. The first initialization transistor Q4 is connected between the first initialization signal line (not shown in the figure) and the gate of the driving transistor Q1, and is used to transmit the first initialization voltage Vref1 on the first initialization signal line to the gate of the driving transistor Q1, and initialize the gate of the driving transistor Q1. Among them, the impedance of the second auxiliary signal line 202 is less than the impedance of the second output signal line 102, so as to reduce the transmission voltage drop of the second scan signal S2 and reduce the difference between the second scan signal S2 in the edge area and the middle area of ​​the display panel.

[0090] In this embodiment, the orthographic projection of the second auxiliary signal line 202 on the substrate 10 covers at least part of the orthographic projection of the second gate control signal line 302 on the substrate 10. Since the second auxiliary signal line 202 is connected to the second gate control signal, and the second auxiliary signal line 202 is connected to the second gate control signal line 302, the potentials of the second auxiliary signal line 202 and the second gate control signal line 302 are not floating, and the second auxiliary signal line 202 shields the second gate control signal line 302, which can play a role of self-shielding of the second auxiliary signal line 202, thereby preventing the transmitted second scanning signal S2 from being disturbed and fluctuating.

[0091] Optionally, the orthographic projection of the second auxiliary signal line 202 on the substrate 10 may completely cover the orthographic projection of the second gate control signal line 302 on the substrate 10 to enhance the self-shielding effect.

[0092] The technical solution provided by the embodiment of the present invention realizes the self-shielding effect of the auxiliary signal line 200 and ensures the stability of the gate control signal transmitted therethrough by setting the orthographic projection of at least part of the auxiliary signal line 200 on the substrate 10 to cover at least part of the orthographic projection of the gate control signal line on the substrate 10.

[0093] Figure 7 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Figure 4 The cross-sectional structure of the display panel along the cutting line BB' is shown. Figure 8 A schematic cross-sectional structure diagram of another display panel provided by an embodiment of the present invention, specifically: Figure 4 The cross-sectional structure of the display panel along the cutting line CC' is shown in FIG. Figure 4 , Figure 7 and Figure 8 The display panel includes a first metal layer, a second metal layer and a third metal layer which are stacked in sequence on one side of a substrate 10, a first insulating layer 20 is arranged between the first metal layer and the second metal layer, a second insulating layer 30 is arranged between the second metal layer and the third metal layer, a third insulating layer 40 is arranged on the side of the third metal layer away from the substrate 10, and a buffer layer 50 is arranged between the substrate 10 and the first metal layer. The output signal line 100 (such as the first output signal line 101 and the second output signal line 102) is located in the first metal layer and / or the second metal layer, the gate control signal line (such as the first gate control signal line 301 and the second gate control signal line 302) is located in the first metal layer, and the auxiliary signal line 200 (such as the first auxiliary signal line 201 and the second auxiliary signal line 202) is located in the third metal layer. The first auxiliary signal line 201 is connected to the first scanning line 301 through the line exchange hole.

[0094] On one side of the output signal line 100, the output signal line 100 is connected to the auxiliary signal line 200 through a line-changing hole to prevent the antenna effect and avoid the occurrence of electrostatic radiation. For example, the first output signal line 101 located in the first metal layer is connected to the first auxiliary signal line 201 located in the third metal layer through a line-changing hole, and the second output signal line 102 located in the second metal layer is connected to the second auxiliary signal line 202 located in the third metal layer through a line-changing hole. The second output signal line 102 can also be set in the same layer as the first output signal line 101.

[0095] Optionally, the first metal layer and the second metal layer both include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer (Ti-Al-Ti) that are stacked. Since the impedance of Ti-Al-Ti is less than the impedance of molybdenum, the auxiliary signal line 200 formed by the Ti-Al-Ti layer can effectively reduce the transmission voltage drop of the gate control signal, which is beneficial to improving the consistency of the gate control signal in the edge area and the middle area of ​​the display panel.

[0096] Optionally, continue to refer to Figure 4 and Figure 5The gate control signal line also includes a third gate control signal line 303, the auxiliary signal line 200 also includes a third auxiliary signal line 203, the output signal line 100 also includes a third output signal line 103, one end of the third auxiliary signal line 203 is connected to the third output signal line 103 via a line change hole, and the other end of the third auxiliary signal line 203 is connected to the third gate control signal line 303 via a line change hole.

[0097] Specifically, the third output signal line 103 is connected to the third auxiliary signal line 203, and the third scan signal S3 on the third output signal line 103 is transmitted to the second initialization transistor Q7 in the pixel circuit PX via the third auxiliary signal line 203. The second initialization transistor Q7 is connected between the second initialization signal line (not shown in the figure) and the first electrode of the light-emitting element D1, and is used to transmit the second initialization voltage Vref2 on the second initialization signal line to the first electrode of the light-emitting element D1 to initialize the first electrode of the light-emitting element D1. Among them, the impedance of the third auxiliary signal line 203 is less than the impedance of the third output signal line 103, so as to reduce the transmission voltage drop of the third scan signal S3, thereby reducing the difference between the third scan signal S3 in the edge area and the middle area of ​​the display panel.

[0098] In this embodiment, the orthographic projection of the third auxiliary signal line 203 on the substrate 10 covers at least part of the orthographic projection of the third gate control signal line on the substrate 10, so the third auxiliary signal line 203 also has a self-shielding effect, preventing the transmitted third scanning signal S3 from being disturbed by external signals and fluctuating. The specific working principle can be referred to the relevant description in the above embodiment, which will not be repeated here.

[0099] Optionally, the orthographic projection of the third auxiliary signal line 203 on the substrate 10 may completely cover the orthographic projection of the third gate control signal line on the substrate 10 to enhance the self-shielding effect.

[0100] Continue to refer Figure 4 and Figure 5 The gate control signal line also includes a light-emitting control signal line 304, the auxiliary signal line 200 also includes a fourth auxiliary signal line 204, the output signal line 100 also includes a fourth output signal line 104, one end of the fourth auxiliary signal line 204 is connected to the fourth output signal line 104 via a line switching hole, and the other end of the fourth auxiliary signal line 204 is connected to the light-emitting control signal line 304 via a line switching hole.

[0101] Specifically, the display panel also includes a first power line and a second power line (not shown in the figure), the pixel circuit PX also includes a first light-emitting control transistor Q5 and a second light-emitting control transistor Q6, the light-emitting control signal line 304 overlaps with the active layer 11 to form the first light-emitting control transistor Q5 and the second light-emitting control transistor Q6 respectively, the first light-emitting control transistor Q5 is connected between the first power line and the second electrode of the driving transistor Q1, the second light-emitting control transistor Q6 is connected between the first electrode of the driving transistor Q1 and the first electrode of the light-emitting element D1, and the second electrode of the light-emitting element D1 is connected to the second power line.

[0102] The fourth auxiliary signal line 204 is connected to the fourth output signal line 104 through the line exchange hole. The light-emitting control signal EM on the fourth output signal line 104 is transmitted to the first light-emitting control transistor Q5 and the second light-emitting control transistor Q6 in the pixel circuit PX through the fourth auxiliary signal line 204. The first light-emitting control transistor Q5 and the second light-emitting control transistor Q6 are used to respond to the light-emitting control signal EM to connect the path between the first power line and the second power line, so that the driving transistor Q1 drives the light-emitting element D1 to emit light. Among them, the first power line can be used to transmit the first power supply voltage VDD, and the second power line can be used to transmit the second power supply voltage VSS. Here, the impedance of the fourth auxiliary signal line 204 is less than the impedance of the fourth output signal line 104, so as to reduce the transmission voltage drop of the light-emitting control signal EM, thereby reducing the difference in the light-emitting control signal EM between the edge area and the middle area of ​​the display panel.

[0103] In this embodiment, the orthographic projection of the fourth auxiliary signal line 204 on the substrate 10 covers at least part of the orthographic projection of the light emitting control signal line 304 on the substrate 10. Therefore, the fourth auxiliary signal line 204 also has a self-shielding effect, preventing the transmitted light emitting control signal EM from being disturbed by external signals and fluctuating. The specific working principle can be referred to the relevant description in the above embodiment, which will not be repeated here.

[0104] Of course, in other embodiments, the orthographic projection of the fourth auxiliary signal line 204 on the substrate 10 may completely cover the orthographic projection of the light emitting control signal line 304 on the substrate 10 to enhance the self-shielding effect.

[0105] Optionally, the orthographic projection of the first auxiliary signal line 201 on the substrate 10 is located between the orthographic projection of the second auxiliary signal line 202 on the substrate 10 and the orthographic projection of the gate of the driving transistor Q1 on the substrate 10, and the orthographic projection of the fourth auxiliary signal line 204 on the substrate 10 is located between the orthographic projection of the gate of the driving transistor Q1 on the substrate 10 and the orthographic projection of the third auxiliary signal line 203 on the substrate 10, which facilitates the layout of the pixel circuit PX.

[0106] It should be understood that in the present embodiment, the output signal line 100 is not directly connected to the gate control signal line with a larger impedance, but is transferred to the gate control signal line through the auxiliary signal line 200 with a smaller impedance. In other words, the original direct connection between the output signal line 100 and the gate control signal line is cut off, and the output signal line 100 is connected to the auxiliary signal line 200, and the gate control signal is transmitted through the auxiliary signal line 200. The auxiliary signal line 200 is connected to the gate control signal line through the line change hole. There is no need to change the layout structure in the display area AA, which is conducive to simplifying the process and reducing the difficulty of preparation. For example, the first output signal line 101 located in the first metal layer is changed to the third metal layer through the line change hole to connect the first auxiliary signal line 201 located in the third metal layer, and the first auxiliary signal line 201 is then connected to the first gate control signal line 301 through the line change hole, wherein the first gate control signal line 301 overlaps with the active layer 11 to form a corresponding transistor. Similarly, the connection method of other output signal lines is similar to the connection method of the first output signal line 101, and will not be repeated.

[0107] It should be noted that in the above embodiments, each output signal line is respectively connected to the corresponding gate drive circuit GD, different gate control signals can be output by different groups of gate drive circuits GD, or some gate control signals can be output by the same group of gate drive circuits GD.

[0108] Optionally, along the first direction X, the length of the auxiliary signal line 200 is greater than the length of the gate control signal line.

[0109] Specifically, Fig. 9 FIG. 1 is a schematic diagram of a top view structure of another display panel provided by an embodiment of the present invention. In combination with the above embodiments, between adjacent pixel circuits PX, the gate control signal line connected to the same auxiliary signal line 200 is an integrated structure (eg Figure 4 as shown) or segmented independent structures (such as Fig. 9 As shown). That is to say, the same gate control signal line can be a continuous signal line or a plurality of independent signal lines in the display area AA, and each independent signal line is only arranged at the position where the corresponding transistor is formed, and the gate control signal line is not arranged at the other positions where the transistor is not formed. By setting the length of the auxiliary signal line 200 to be greater than the length of the gate control signal line, it is helpful to reduce the impedance change of the auxiliary signal line 200 at the line switching connection, and ensure the uniformity of the impedance of the auxiliary signal line 200. In the case where the auxiliary signal line 200 and the gate control signal line are not overlapped, it is also possible to save the wiring space of the gate control signal line and prevent the gate control signal line from interfering with other signal lines on the same layer.

[0110] Fig.10A schematic diagram of a top view of another display panel provided in an embodiment of the present invention, referring to Figure 5 and Fig.10 On the basis of the above embodiments, the display panel further includes a first initialization signal line 411 and a second initialization signal line 412, both of which extend along the first direction X and are alternately arranged along the second direction. The first initialization signal line 411 is used to provide a first initialization voltage Vref1 for the pixel circuit PX, and the second initialization signal line 412 is used to provide a second initialization voltage Vref2 for the pixel circuit PX, wherein the first initialization signal line 411 is connected to the first initialization transistor Q4, and the second initialization signal line 412 is connected to the second initialization transistor Q7.

[0111] Optionally, the first initialization signal line 411 is disposed near the second auxiliary signal line 302, and the first initialization signal line 411 and the second auxiliary signal line 302 are disposed in different layers. For example, the first initialization signal line 411 is located in the second metal layer, and the second auxiliary signal line 302 is located in the third metal layer.

[0112] Optionally, the second initialization signal line 412 is disposed close to one side of the third auxiliary signal line 203 , and the second initialization signal line 412 is disposed on the same layer as the first initialization signal line 411 .

[0113] Optionally, continue to refer to Figure 5 and Fig.10 The display panel further includes a data line 61 extending along the second direction Y and arranged along the first direction X. The data line 61 is connected to the data writing transistor Q2 for transmitting a data voltage Vdata.

[0114] Fig.11 A waveform diagram of a gate control signal provided in the prior art, referring to Fig.11 In the prior art, due to the large impedance of the gate control signal line, the rising edge and falling edge of the gate control signal account for a large proportion of time, resulting in a very short effective time of the gate control signal (the duration of the peak or trough of the waveform). For example, for the first scanning signal S1, the rising edge time of its waveform is 1.5884us, and the falling edge time is 1.3273us. The effective time of the first scanning signal S1 is short, resulting in a short pixel charging time, resulting in insufficient charging and affecting the display brightness.

[0115] Fig.12 A waveform diagram of a gate control signal provided by an embodiment of the present invention, referring to Fig.12In this embodiment, since the impedance of the auxiliary signal line 200 is small, the transmission voltage drop of the gate control signal is reduced, so the proportion of the rising edge and the falling edge of the gate control signal can be greatly reduced. Similarly, for the first scanning signal S1, its waveform rising edge time is 818.09ns, and the falling edge time is 848.22ns. The effective time of the first scanning signal S1 is longer, so that the pixel can be charged more fully and the display brightness can reach the standard.

[0116] Optionally, for other gate control signals, such as the second scanning signal S2, the third scanning signal S3 and the light-emitting control signal EM, after adopting the technical solution provided in this embodiment, the transmission voltage drop of the signal can also be reduced, thereby reducing the proportion of the rising edge and the falling edge, thereby improving the display effect.

[0117] Fig.13 A schematic diagram of a top view of another display panel provided in an embodiment of the present invention, referring to Fig.13 On the basis of the above embodiments, the gate control signal line can be omitted, and the auxiliary signal line 200 overlaps with the active layer 11 to form the gate of the transistor. For example, the first auxiliary signal line 201 overlaps with the active layer 11 to form the data writing transistor Q2 and the compensation transistor Q3, the second auxiliary signal line 202 overlaps with the active layer 11 to form the first initialization transistor Q4, the third auxiliary signal line 203 overlaps with the active layer to form the second initialization transistor Q7, and the fourth auxiliary signal line 204 overlaps with the active layer 11 to form the first light emission control transistor Q5 and the second light emission control transistor Q6. The auxiliary signal line 200 is connected to the gate of each transistor accordingly. By multiplexing the auxiliary signal line 200 as the gate control signal line, while reducing the transmission voltage drop of the gate control signal, the number of signal lines can be reduced and the layout can be optimized.

[0118] Alternatively, if Fig.10 and Fig.13 As shown, the display panel is further provided with a redundant via 70 on one side of the output signal line, which can be used to balance the static electricity accumulation of the display panel, prevent static electricity discharge, and improve the protection effect on the circuit and the device.

[0119] Optionally, an embodiment of the present invention further provides a display device, which includes the display panel provided by any embodiment of the present invention, so the display device also has the beneficial effects described in any of the above embodiments. The display panel can be a flexible display panel or a rigid display panel. Fig.14A structural schematic diagram of a display device provided in an embodiment of the present invention. In this embodiment, the display device 300 can be a mobile phone or any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals and other products. The embodiment of the present invention does not make any special limitation on this.

[0120] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0121] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A substrate, on which a plurality of pixel circuits arranged in an array are disposed; A gate drive circuit and a plurality of output signal lines, wherein the gate drive circuit is connected to the output signal lines correspondingly, and the output signal lines are used to output gate control signals generated by the gate drive circuit; a plurality of auxiliary signal lines, wherein the auxiliary signal lines are connected between the output signal lines and the pixel circuits, and the auxiliary signal lines are used to transmit the gate control signals on the output signal lines to the pixel circuits; Wherein, at least part of the auxiliary signal lines and the output signal lines are arranged in different layers, and the impedance of the auxiliary signal lines is smaller than the impedance of the output signal lines.

2. The display panel according to claim 1, characterized in that: The display panel comprises a display area and a non-display area arranged around at least a portion of the display area, the gate driving circuit and the output signal line are located in the non-display area, and the pixel circuit is located in the display area; The auxiliary signal line extends from the non-display area to the display area and extends along a first direction in the display area, and the plurality of auxiliary signal lines are arranged along a second direction; wherein the first direction intersects with the second direction; Preferably, the plurality of auxiliary signal lines are arranged in the same layer.

3. The display panel according to claim 1, characterized in that: The display panel further comprises a plurality of gate control signal lines, the gate control signal lines and the auxiliary signal lines are arranged in different layers, the auxiliary signal lines are connected to the gate control signal lines through line exchange holes, and the gate control signal lines are connected to the pixel circuits; Preferably, at least part of the orthographic projection of the auxiliary signal line on the substrate covers at least part of the orthographic projection of the gate control signal line on the substrate; Preferably, along the first direction, the length of the auxiliary signal line is greater than the length of the gate control signal line; Preferably, the plurality of auxiliary signal lines extend along the first direction and are arranged along a second direction, and the first direction intersects with the second direction; Preferably, a plurality of gate control signal lines are arranged in the same layer; Preferably, the auxiliary signal line is connected to the output signal line through the line changing hole; Preferably, the display panel further comprises an active layer, the pixel circuit comprises a plurality of transistors, the gate control signal line overlaps with the active layer to form the gate of the transistor, and the auxiliary signal line is connected to the gate of the transistor via the line exchange hole; Preferably, between adjacent pixel circuits, the gate control signal line connected to the same auxiliary signal line is an integrated structure or a segmented independent structure.

4. The display panel according to claim 3, characterized in that: The display panel comprises a first metal layer, a second metal layer and a third metal layer which are sequentially stacked and located on one side of the substrate; The output signal line is located in the first metal layer and / or the second metal layer, the gate control signal line is located in the first metal layer, and the auxiliary signal line is located in the third metal layer; Preferably, the first metal layer and the second metal layer both include a molybdenum layer, and the third metal layer includes a first titanium layer, an aluminum layer, and a second titanium layer which are stacked.

5. The display panel according to claim 3, characterized in that: The gate control signal line includes a first gate control signal line, the auxiliary signal line includes a first auxiliary signal line, the output signal line includes a first output signal line, one end of the first auxiliary signal line is connected to the first output signal line through the line changing hole, and the other end of the first auxiliary signal line is connected to the first gate control signal line through the line changing hole; The pixel circuit includes a driving transistor and a data writing transistor, the first gate control signal line overlaps with the active layer to form the data writing transistor, and the data writing transistor is connected between the data line and the second electrode of the driving transistor; Preferably, the pixel circuit further comprises a compensation transistor, the first gate control signal line overlaps with the active layer to form the compensation transistor, and the compensation transistor is connected between the gate and the first electrode of the driving transistor; Preferably, the pixel circuit further comprises a storage capacitor, a first electrode of the storage capacitor is connected to the gate of the driving transistor, and a second electrode of the storage capacitor is connected to a fixed voltage; Preferably, the gate of the driving transistor is reused as the first electrode of the storage capacitor.

6. The display panel according to claim 5, characterized in that: The orthographic projection of the first auxiliary signal line on the substrate does not overlap with the orthographic projection of the first gate control signal line on the substrate; Preferably, the first gate control signal line includes a main body, a first branch and a second branch, the main body extends along a first direction, the first branch extends along a second direction, the second branch extends in the opposite direction of the second direction, the main body overlaps with the active layer to form the data write transistor, the first branch overlaps with the active layer to form the compensation transistor, and the second branch is connected to the first auxiliary signal line through the line change hole.

7. The display panel according to claim 5, characterized in that: The orthographic projection of the first auxiliary signal line on the substrate covers at least part of the orthographic projection of the first gate control signal line on the substrate; Preferably, the first gate control signal line includes a main body and a first branch portion, the main body extends along a first direction, the first branch portion extends along a second direction, the main body overlaps with the active layer to form the data write transistor, the first branch portion and / or the main body overlap with the active layer to form the compensation transistor, and the main body and / or the first branch portion are connected to the first auxiliary signal line through the line change hole.

8. The display panel according to claim 5, characterized in that: The gate control signal line further includes a second gate control signal line, the auxiliary signal line further includes a second auxiliary signal line, the output signal line further includes a second output signal line, one end of the second auxiliary signal line is connected to the second output signal line via the line changing hole, and the other end of the second auxiliary signal line is connected to the second gate control signal line via the line changing hole; Preferably, the orthographic projection of the second auxiliary signal line on the substrate covers at least part of the orthographic projection of the second gate control signal line on the substrate; Preferably, the display panel further comprises a first initialization signal line, and the first initialization signal line and the second auxiliary signal line are arranged in different layers; The pixel circuit further includes a first initialization transistor, the second gate control signal line overlaps with the active layer to form the first initialization transistor, and the first initialization transistor is connected between the first initialization signal line and the gate of the driving transistor; Preferably, the gate control signal line further includes a third gate control signal line, the auxiliary signal line further includes a third auxiliary signal line, the output signal line further includes a third output signal line, one end of the third auxiliary signal line is connected to the third output signal line via the line changing hole, and the other end of the third auxiliary signal line is connected to the third gate control signal line via the line changing hole; The orthographic projection of the third auxiliary signal line on the substrate covers at least part of the orthographic projection of the third gate control signal line on the substrate; Preferably, the display panel further comprises a second initialization signal line, and the second initialization signal line is arranged in the same layer as the first initialization signal line; The pixel circuit further includes a second initialization transistor, the third gate control signal line overlaps with the active layer to form the second initialization transistor, and the second initialization transistor is connected between the second initialization signal line and the light emitting element; Preferably, the gate control signal line further includes a light-emitting control signal line, the auxiliary signal line further includes a fourth auxiliary signal line, the output signal line further includes a fourth output signal line, one end of the fourth auxiliary signal line is connected to the fourth output signal line via the line-changing hole, and the other end of the fourth auxiliary signal line is connected to the light-emitting control signal line via the line-changing hole; The orthographic projection of the fourth auxiliary signal line on the substrate covers at least part of the orthographic projection of the light emitting control signal line on the substrate; Preferably, the display panel further comprises a first power line and a second power line, the pixel circuit further comprises a first light emission control transistor and a second light emission control transistor, the light emission control signal line overlaps with the active layer to form the first light emission control transistor and the second light emission control transistor respectively, the first light emission control transistor is connected between the first power line and the second electrode of the driving transistor, the second light emission control transistor is connected between the first electrode of the driving transistor and the first electrode of the light emitting element, and the second electrode of the light emitting element is connected to the second power line; Preferably, the orthographic projection of the first auxiliary signal line on the substrate is located between the orthographic projection of the second auxiliary signal line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate, and the orthographic projection of the fourth auxiliary signal line on the substrate is located between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the third auxiliary signal line on the substrate.

9. The display panel according to claim 1, characterized in that: The display panel further comprises an active layer, the pixel circuit comprises a plurality of transistors, and the auxiliary signal line overlaps with the active layer to form a gate of the transistor; Preferably, the auxiliary signal line is connected to the gate of the transistor.

10. A display device, characterized in that: A display panel comprising any one of claims 1 to 9.

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