Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises at least two groups of clock signal lines, so that a first type of gate drive unit is connected with one group of clock signal lines, and at least two of a second type of gate drive unit, a third type of gate drive unit, a fourth type of gate drive unit and a fifth type of gate drive unit are arranged along a second direction, and at least two of the second type of gate driving units, the third type of gate driving units, the fourth type of gate driving units and the fifth type of gate driving units are connected with the other group of clock signal lines, so that at least one group of clock signal lines can be reduced in a gate driving circuit setting area on one side; and the space occupied by the gate driving unit in the first direction can be reduced, so that the frame is reduced, and the number of the clock signal lines is reduced, so that the electric signals needing to be output can be correspondingly reduced, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of display devices, the requirements of existing display devices for power consumption and screen-to-body ratio are getting higher and higher. In order to reduce power consumption and increase screen-to-body ratio, existing display devices will make pixel circuits adopt low-temperature polysilicon oxide (LTPO) technology. LTPO technology refers to the use of low-temperature polysilicon thin-film transistors and oxide thin-film transistors at the same time, so that the driving circuit takes into account the advantages of low-temperature polysilicon thin-film transistors and oxide thin-film transistors, thereby reducing power consumption and leakage current. In order to achieve the normal operation of the pixel circuit and avoid the signal difference caused by impedance affecting the display, a gate drive circuit will be set on both sides of the display area, and the transistors in the pixel drive circuit will be controlled by different gate drive circuits to achieve normal display of the display device. However, since gate drive circuits need to be set on both sides of the display area, and each side of the display area includes multiple gate drive circuits and multiple wirings, the border of the display panel is large, and a signal needs to be input to each wiring, resulting in a large power consumption of the display panel.

[0003] Therefore, existing display devices have technical problems such as a large number of wirings in the gate drive circuit, which leads to a large border and high power consumption. Summary of the invention

[0004] The embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that a large number of wirings in a gate drive circuit of an existing display device leads to a large border and high power consumption.

[0005] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, the display panel comprising:

[0006] A display area, wherein a plurality of pixel driving circuits are disposed in the display area, and each of the pixel driving circuits includes a plurality of transistors;

[0007] A non-display area, comprising two gate drive circuit arrangement areas arranged on both sides of the display area along a first direction, each of the gate drive circuit arrangement areas being provided with a group of gate drive circuits, each group of the gate drive circuits comprising a first type of gate drive unit, a second type of gate drive unit, a third type of gate drive unit, a fourth type of gate drive unit and a fifth type of gate drive unit, the first type of gate drive unit, the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit being respectively connected to the gates of different transistors in the pixel drive circuit;

[0008] Wherein, in one of the gate drive circuit arrangement areas, the display panel further comprises at least two groups of clock signal lines, and the first type of gate drive unit is connected to one group of the clock signal lines;

[0009] At least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to another group of the clock signal lines, and an angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

[0010] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0011] The embodiments of the present application provide a display panel and a display device; the display panel includes at least two groups of clock signal lines, so that a first type of gate driving unit is connected to one group of clock signal lines, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to another group of the clock signal lines. In this way, at least one group of clock signal lines can be reduced in the gate driving circuit setting area on one side, and the space occupied by the gate driving unit along the first direction can be reduced, thereby reducing the border, and since the number of clock signal lines is reduced, the electrical signals that need to be output can also be reduced accordingly, thereby reducing power consumption.

[0012] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0014] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0015] Figure 1 A schematic diagram of the arrangement of control units of a comparative display device and their connection with a clock line provided in an embodiment of the present application.

[0016] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application.

[0017] Figure 3 This is a schematic diagram of a first arrangement of various gate driving units in a gate driving circuit in a display panel provided in an embodiment of the present application.

[0018] Figure 4 A schematic diagram of the connection between the first type of gate driving unit and the clock signal line in the gate driving circuit provided in an embodiment of the present application.

[0019] Figure 5 for Figure 3 A schematic diagram of connection between the second type of gate driving unit and the third type of gate driving unit in the gate driving circuit and the clock signal line.

[0020] Figure 6 for Figure 3 Schematic diagram of the connection between the fourth type of gate driving unit and the clock signal line in the gate driving circuit.

[0021] Figure 7 for Figure 3 Schematic diagram of the connection between the fourth type of gate driving unit and the clock signal line in the gate driving circuit.

[0022] Figure 8 This is a schematic diagram of a second arrangement of various gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application.

[0023] Fig. 9 for Figure 8 Schematic diagram of connection between the fourth type of gate driving unit and the fifth type of gate driving unit in the gate driving circuit and the clock signal line.

[0024] Fig.10 for Figure 8 Schematic diagram of connection between the second type of gate driving unit and the clock signal line in the gate driving circuit.

[0025] Fig.11 for Figure 8 Schematic diagram of the connection between the third type of gate driving unit and the clock signal line in the gate driving circuit.

[0026] Fig.12 This is a schematic diagram of a third arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application.

[0027] Fig.13 for Fig.12A schematic diagram of a first connection between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit.

[0028] Fig.14 for Fig.12 A second connection diagram of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit.

[0029] Fig.15 for Fig.12 A schematic diagram of a third connection between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit.

[0030] Fig.16 This is a schematic diagram of a fourth arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application.

[0031] Fig.17 for Fig.16 A schematic diagram of connecting the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit in the gate driving circuit and the clock signal line.

[0032] Fig.18 for Fig.16 Schematic diagram of the connection between the fifth type of gate driving unit and the clock signal line in the gate driving circuit.

[0033] Fig.19 This is a schematic diagram of a fifth arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application.

[0034] Fig. 20 for Fig.19 A schematic diagram of connections between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit.

[0035] Fig.21 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application.

[0036] Fig. 22 This is a first circuit diagram of a gate driving circuit in a display panel provided in an embodiment of the present application.

[0037] Fig.23 This is a second circuit diagram of the gate driving circuit in the display panel provided in an embodiment of the present application.

[0038] Fig.24 This is a third circuit diagram of the gate driving circuit in the display panel provided in an embodiment of the present application.

[0039] Fig.25 A schematic diagram of the arrangement and connection of the second type of gate driving unit, the third type of gate driving unit, the high potential signal line, the low potential signal line and the control signal line in the gate driving circuit provided in an embodiment of the present application.

[0040] Fig.26 A schematic diagram of the arrangement and connection of the fourth type of gate driving unit, the fifth type of gate driving unit, and the high potential signal line, the low potential signal line, and the control signal line in the gate driving circuit provided in an embodiment of the present application.

[0041] Fig. 27 This is a schematic diagram of a first connection between various gate driving units and a pixel driving circuit in a gate driving circuit provided in an embodiment of the present application.

[0042] Fig.28 This is a schematic diagram of a second connection between various gate driving units and a pixel driving circuit in the gate driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0044] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0045] In order to explain the principle of the technical problem of the embodiment of the present application, the embodiment of the present application provides a comparative display device. It is understandable that the comparative display device cannot be used as the prior art in the present application. Figure 1 As shown, Figure 1 (a) is a schematic diagram showing the arrangement of the gate drive circuit and the display area of ​​the display panel. Figure 1(b) is a schematic diagram of the connection between the first N-type control unit and the second N-type control unit and the clock line, Figure 1 (c) is a schematic diagram of the connection between the second P-type control unit and the third P-type control unit and the clock line. Figure 1 As can be seen from (a), in order to prevent the impedance difference between the edge area and the middle area in the display area AA from being too large, gate driving circuits are set on both sides of the display area AA, and the gate driving circuit on each side includes a first P-type control unit Pscan01, a second P-type control unit Pscan02, a third P-type control unit EM0, a first N-type control unit Nscan01 and a second N-type control unit Nscan02. Each control unit is connected to the gate of different transistors in the pixel circuit in the display area AA, thereby realizing the normal operation of the pixel circuit in the display area AA.

[0046] In order to realize the normal operation of each control unit, each control unit is connected to a group of clock lines. Each group of clock lines includes two clock lines, so as to realize the control of control units at different levels. Figure 1 (b) and Figure 1 As shown in (c), the comparative display device includes a first clock line CK01, a second clock line CK02, a third clock line CK03, a fourth clock line CK04, a fifth clock line CK05, a sixth clock line CK06, a seventh clock line CK07, an eighth clock line CK08, a ninth clock line (not shown) and a tenth clock line (not shown), a first N-type control unit Nscan01 is connected to the first clock line CK01 and the second clock line CK02, a second N-type control unit Nscan02 is connected to the third clock line CK03 and the fourth clock line CK04, a first P-type control unit Pscan01 is connected to the ninth clock line and the tenth clock line, a second P-type control unit Pscan02 is connected to the seventh clock line CK07 and the eighth clock line CK08, and a third P-type control unit EM0 is connected to the fifth clock line CK05 and the sixth clock line CK06, thereby realizing normal operation of each control unit. From the above description, it can be seen that each control unit requires a group of clock lines (2 clock lines) as input signals, and five groups of control units require 5 groups of clock lines (10 clock lines) as input signals, resulting in more electrical signals to be input, and the clock lines occupy a larger space, which makes the border of the gate drive circuit larger, and the gate drive circuit is arranged on both sides of the display area, which will cause the borders on both sides of the display area to be larger. Therefore, the existing display devices have a large number of wirings in the gate drive circuit, resulting in a larger border and higher power consumption. Technical problems.

[0047] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0048] Figure 2 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 3 This is a schematic diagram of a first arrangement of various gate driving units in a gate driving circuit in a display panel provided in an embodiment of the present application. Figure 4 A schematic diagram of the connection between the first type of gate driving unit and the clock signal line in the gate driving circuit provided in an embodiment of the present application. Figure 5 for Figure 3 A schematic diagram of connection between the second type of gate driving unit and the third type of gate driving unit in the gate driving circuit and the clock signal line. Figure 6 for Figure 3 Schematic diagram of the connection between the fourth type of gate driving unit and the clock signal line in the gate driving circuit. Figure 7 for Figure 3 Schematic diagram of the connection between the fourth type of gate driving unit and the clock signal line in the gate driving circuit. Figure 8 This is a schematic diagram of a second arrangement of various gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application. Fig. 9 for Figure 8 Schematic diagram of connection between the fourth type of gate driving unit and the fifth type of gate driving unit in the gate driving circuit and the clock signal line. Fig.10 for Figure 8 Schematic diagram of connection between the second type of gate driving unit and the clock signal line in the gate driving circuit. Fig.11 for Figure 8 Schematic diagram of the connection between the third type of gate driving unit and the clock signal line in the gate driving circuit. Fig.12 This is a schematic diagram of a third arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application. Fig.13 for Fig.12 A schematic diagram of a first connection between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit. Fig.14 for Fig.12 A second connection diagram of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit. Fig.15 for Fig.12 A schematic diagram of a third connection between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit. Fig.16 This is a schematic diagram of a fourth arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application. Fig.17 for Fig.16A schematic diagram of connecting the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit in the gate driving circuit and the clock signal line. Fig.18 for Fig.16 Schematic diagram of the connection between the fifth type of gate driving unit and the clock signal line in the gate driving circuit. Fig.19 This is a schematic diagram of a fifth arrangement of various types of gate driving units in the gate driving circuit of the display panel provided in an embodiment of the present application. Fig. 20 for Fig.19 A schematic diagram of connections between the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit and the clock signal line in the gate driving circuit. Fig.21 A circuit diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application. Fig. 22 This is a first circuit diagram of a gate driving circuit in a display panel provided in an embodiment of the present application. Fig.23 This is a second circuit diagram of the gate driving circuit in the display panel provided in an embodiment of the present application. Fig.24 This is a third circuit diagram of the gate driving circuit in the display panel provided in an embodiment of the present application. Fig.25 A schematic diagram of the arrangement and connection of the second type of gate driving unit, the third type of gate driving unit, the high potential signal line, the low potential signal line and the control signal line in the gate driving circuit provided in an embodiment of the present application. Fig.26 A schematic diagram of the arrangement and connection of the fourth type of gate driving unit, the fifth type of gate driving unit, and the high potential signal line, the low potential signal line, and the control signal line in the gate driving circuit provided in an embodiment of the present application. Fig. 27 This is a schematic diagram of a first connection between various gate driving units and a pixel driving circuit in a gate driving circuit provided in an embodiment of the present application. Fig.28 This is a schematic diagram of a second connection between various gate driving units and a pixel driving circuit in the gate driving circuit provided in an embodiment of the present application.

[0049] like Figures 2 to 28As shown, an embodiment of the present application provides a display panel, the display panel 1 includes a display area 101 and a non-display area 102, the display area 101 is provided with a plurality of pixel driving circuits 21, each of the pixel driving circuits 21 includes a plurality of transistors (for example, a driving transistor T1 and a switching transistor T2); the non-display area 102 includes two gate driving circuit setting areas 102a arranged on both sides of the display area 101 along a first direction X, each of the gate driving circuit setting areas 102a is provided with a group of gate driving circuits 22, each group of gate driving circuits 22 includes a first type of gate driving unit 221, a second type of gate driving unit 222, a third type of gate driving unit 223, a fourth type of gate driving unit 224 and a fifth type of gate driving unit 225, the first type of gate driving unit 221, the second type of gate driving unit 222, the third type of gate driving unit 223, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are respectively connected to the gates of different transistors in the pixel driving circuit 21;

[0050] Wherein, in one of the gate driving circuit setting areas 102a, the display panel 1 further includes at least two groups of clock signal lines CK, and the first type of gate driving unit 221 is connected to one group of the clock signal lines CK;

[0051] At least two of the second type of gate driving unit 222, the third type of gate driving unit 223, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are arranged along the second direction Y, and at least two of the second type of gate driving unit 222, the third type of gate driving unit 223, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are connected to another group of the clock signal lines CK, and an angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0052] An embodiment of the present application provides a display panel, which includes at least two groups of clock signal lines, so that a first type of gate driving unit is connected to one group of clock signal lines, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to another group of the clock signal lines. In this way, at least one group of clock signal lines can be reduced in the gate driving circuit setting area on one side, and the space occupied by the gate driving unit along the first direction can be reduced, thereby reducing the border. Since the number of clock signal lines is reduced, the electrical signals that need to be output can also be reduced accordingly, thereby reducing power consumption.

[0053] Specifically, Figure 2As shown, the non-display area 102 can be arranged around the display area 101, but the embodiments of the present application are not limited thereto. The non-display area 102 can be arranged on two sides or three sides of the display area 101, and the non-display area 102 can be bent to the back side of the display panel.

[0054] Specifically, the non-display area 102 may further include a binding area (not shown).

[0055] In some embodiments, within a gate driving circuit setting area, the second type of gate driving unit and the third type of gate driving unit are set along the second direction; and / or the fourth type of gate driving unit and the fifth type of gate driving unit are set along the second direction.

[0056] In some embodiments, within a gate drive circuit setting area, the second type of gate drive unit and the third type of gate drive unit are arranged along the second direction; and / or the fourth type of gate drive unit and the fifth type of gate drive unit are arranged along the second direction, and the display panel includes at least two groups of clock signal lines.

[0057] In some embodiments, Figures 3 to 7 As shown, in a gate drive circuit setting area 102a, the display panel 1 includes four groups of clock signal lines CK, the second type of gate drive unit 222 and the third type of gate drive unit 223 are arranged along the second direction Y, the first type of gate drive unit 221 is connected to a group of the clock signal lines CK, the second type of gate drive unit 222 and the third type of gate drive unit 223 are connected to a group of the clock signal lines CK, the fourth type of gate drive unit 224 is connected to a group of the clock signal lines CK, and the fifth type of gate drive unit 225 is connected to a group of the clock signal lines CK, and the clock signal lines CK connected to the first type of gate drive unit 221, the second type of gate drive unit 222, the fourth type of gate drive unit 224 and the fifth type of gate drive unit 225 are different from each other. By arranging the second type of gate driving unit and the third type of gate driving unit along the second direction, the second type of gate driving unit and the third type of gate driving unit are connected to a group of clock signal lines, so that a group of clock signal lines can be reduced in the gate driving circuit setting area on one side, thereby reducing the space occupied by the clock signal lines and the wiring connecting the clock signal lines, and reducing the lateral space occupied by the second type of gate driving unit and the third type of gate driving unit, reducing the border, and since the clock signal lines are reduced, the power consumption can be reduced.

[0058] Specifically, Figure 1 , Figure 3As shown, compared with the comparative display device in which each control unit is arranged along the first direction, in the embodiment of the present application, the second type of gate driving unit and the third type of gate driving unit are arranged along the second direction, which can reduce the space occupied by the second type of gate driving unit and the third type of gate driving unit, and the second type of gate driving unit and the third type of gate driving unit are connected to the same group of clock signal lines, which can reduce the space occupied by the clock signal lines and the wiring connecting the clock signal lines, reduce the border, and reduce power consumption.

[0059] Specifically, Figures 3 to 7 As shown, in a gate drive circuit setting area 102a, when the display panel 1 includes four groups of clock signal lines CK, the four groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2, a third group of clock signal lines CK3 and a fourth group of clock signal lines CK4, the first group of clock signal lines CK1 may include a first clock signal line CKa and a second clock signal line CKb, the second group of clock signal lines CK2 may include a third clock signal line CKc and a fourth clock signal line CKd, the third group of clock signal lines CK3 may include a fifth clock signal line CKe and a sixth clock signal line CKf, the fourth group of clock signal lines CK4 may include a seventh clock signal line CKg and an eighth clock signal line C Kh, when the fifth type of gate driving unit, the fourth type of gate driving unit, the third type of gate driving unit and the first type of gate driving unit are arranged in sequence, the first clock signal line CKa and the second clock signal line CKb can be arranged between the first type of gate driving unit and the third type of gate driving unit, the third clock signal line CKc and the fourth clock signal line CKd can be arranged between the third type of gate driving unit and the fourth type of gate driving unit, the fifth clock signal line CKe and the sixth clock signal line CKf can be arranged between the fourth type of gate driving unit and the fifth type of gate driving unit, and the seventh clock signal line CKg and the eighth clock signal line CKh can be arranged on the side of the fifth type of gate driving unit away from the fourth type of gate driving unit.

[0060] Specifically, Figure 3 , Figure 4 As shown, the first type of gate driving unit 221 includes a plurality of first gate driving units 221a, each first gate driving unit 221a is connected to the first group of clock signal lines CK1 (i.e., the first clock signal line CKa and the second clock signal line CKb), the first-stage first gate driving unit 221a is connected to the first start signal line STV1, and the other first gate driving units 221a are connected to the output end or the stage transmission end of the previous first gate driving unit 221a (depending on the circuit, the output end Pout1 may be directly used as the stage transmission end in a first gate driving unit, or the output end Pout1 and the stage transmission end may be respectively set, and similarly, other gate driving units may also be designed in this way).

[0061] Specifically, Figure 3 , Figure 5 As shown, the second type of gate driving unit 222 includes a plurality of stages of second gate driving units 222a, each stage of the second gate driving unit 222a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the third type of gate driving unit 223 includes a plurality of stages of third gate driving units 223a, each stage of the third gate driving unit 223a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the second gate driving unit 222a and the third gate driving unit 223a are alternately arranged along the second direction.

[0062] Specifically, Figure 3 , Figure 5 As shown, the first-stage second gate driving unit 222a is connected to the second start signal line STV2, the other-stage second gate driving units 222a are connected to the output end or the stage transfer end of the previous-stage second gate driving unit 222a, the first-stage third gate driving unit 223a is connected to the third start signal line STV3, and the other-stage third gate driving units 223a are connected to the output end or the stage transfer end of the previous-stage third gate driving unit 223a.

[0063] Specifically, Figure 3 , Figure 6 As shown, the fourth type of gate driving unit 224 includes a plurality of stages of fourth gate driving units 224a, each stage of the fourth gate driving unit 224a is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf), the first stage of the fourth gate driving unit 224a is connected to the fourth start signal line STV4, and the fourth gate driving units 224a at other stages are connected to the output end or the stage transmission end of the fourth gate driving unit 224a at the previous stage.

[0064] Specifically, Figure 3 , Figure 7 As shown, the fifth type of gate driving unit 225 includes multiple stages of fifth gate driving units 225a, each stage of the fifth gate driving unit 225a is connected to the fourth group of clock signal lines (i.e., the seventh clock signal line CKg and the eighth clock signal line CKh), the first stage of the fifth gate driving unit 225a is connected to the fifth start signal line STV5, and the other stages of the fifth gate driving units 225a are connected to the output end or the stage transmission end of the fifth gate driving unit 225a of the previous stage.

[0065] In some embodiments, Figure 4 , Figures 8 to 11As shown, in a gate driving circuit setting area 102a, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are arranged along the second direction Y, the display panel 1 includes four groups of clock signal lines CK, the first type of gate driving unit 221 is connected to a group of the clock signal lines CK, the second type of gate driving unit 222 is connected to a group of the clock signal lines CK, the third type of gate driving unit 223 is connected to a group of the clock signal lines CK, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are connected to a group of the clock signal lines CK, and the clock signal lines CK connected to the first type of gate driving unit 221, the second type of gate driving unit 222, the third type of gate driving unit 223 and the fourth type of gate driving unit 224 are different from each other. By arranging the fourth type of gate driving unit and the fifth type of gate driving unit along the second direction, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to a group of clock signal lines, so that a group of clock signal lines can be reduced in the gate driving circuit setting area on one side, thereby reducing the space occupied by the clock signal lines and the wiring connecting the clock signal lines, and reducing the lateral space occupied by the fourth type of gate driving unit and the fifth type of gate driving unit, reducing the border, and since the clock signal lines are reduced, the power consumption can be reduced.

[0066] Specifically, Figure 1 , Figure 8 As shown, compared with the comparative display device in which each control unit is arranged along the first direction, in the embodiment of the present application, the fourth gate driving unit and the fifth gate driving unit are arranged along the second direction, which can reduce the space occupied by the fourth gate driving unit and the fifth gate driving unit, and the fourth gate driving unit and the fifth gate driving unit are connected to the same group of clock signal lines, which can reduce the space occupied by the clock signal lines and the wiring connecting the clock signal lines, reduce the border, and reduce power consumption.

[0067] Specifically, Figure 4 , Figures 8 to 11As shown, in a gate drive circuit setting area 102a, when the display panel 1 includes four groups of clock signal lines CK, the four groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2, a third group of clock signal lines CK3 and a fourth group of clock signal lines CK4, the first group of clock signal lines CK1 may include a first clock signal line CKa and a second clock signal line CKb, the second group of clock signal lines CK2 may include a third clock signal line CKc and a fourth clock signal line CKd, the third group of clock signal lines CK3 may include a fifth clock signal line CKe and a sixth clock signal line CKf, the fourth group of clock signal lines CK4 may include a seventh clock signal line CKg and an eighth clock signal line C Kh, when the fifth type of gate driving unit, the third type of gate driving unit, the second type of gate driving unit and the first type of gate driving unit are arranged in sequence, the first clock signal line CKa and the second clock signal line CKb can be arranged between the first type of gate driving unit and the second type of gate driving unit, the third clock signal line CKc and the fourth clock signal line CKd can be arranged between the second type of gate driving unit and the third type of gate driving unit, the fifth clock signal line CKe and the sixth clock signal line CKf can be arranged between the third type of gate driving unit and the fourth type of gate driving unit, and the seventh clock signal line CKg and the eighth clock signal line CKh can be arranged on the side of the fourth type of gate driving unit away from the third type of gate driving unit.

[0068] Specifically, Figure 4 , Figure 8 As shown, the first type of gate driving unit 221 includes a plurality of first gate driving units 221a, each first gate driving unit 221a is connected to the first group of clock signal lines CK1 (i.e., the first clock signal line CKa and the second clock signal line CKb), the first-stage first gate driving unit 221a is connected to the first start signal line STV1, and the other first gate driving units 221a are connected to the output end or the stage transmission end of the previous first gate driving unit 221a (depending on the circuit, the output end Pout1 may be directly used as the stage transmission end in a first gate driving unit, or the output end Pout1 and the stage transmission end may be respectively set, and similarly, other gate driving units may also be designed in this way).

[0069] Specifically, Figure 8 , Fig. 9As shown, the fourth type of gate driving unit 224 includes a plurality of fourth gate driving units 224a, and each fourth gate driving unit 224a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd). The fifth type of gate driving unit 225 includes a plurality of fifth gate driving units 225a, and each fifth gate driving unit 225a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the fifth gate driving unit 225a and the fourth gate driving unit 224a are alternately arranged along the second direction.

[0070] Specifically, Figure 8 , Fig. 9 As shown, the first-stage fourth gate driving unit 224a is connected to the fourth start signal line STV4, the other-stage fourth gate driving units 224a are connected to the output end or the stage transfer end of the fourth gate driving unit 224a of the previous stage, the first-stage fifth gate driving unit 225a is connected to the fifth start signal line STV5, and the other-stage fifth gate driving units 225a are connected to the output end or the stage transfer end of the fifth gate driving unit 225a of the previous stage.

[0071] Specifically, Figure 8 , Fig.10 As shown, the second type of gate driving unit 222 includes a plurality of stages of second gate driving units 222a, each stage of the second gate driving unit 222a is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf), the first stage of the second gate driving unit 222a is connected to the second start signal line STV2, and the other stages of the second gate driving units 222a are connected to the output end or the stage transmission end of the second gate driving unit 222a of the previous stage.

[0072] Specifically, Figure 8 , Fig.11 As shown, the third type of gate driving unit 223 includes multiple levels of third gate driving units 223a, each level of the third gate driving unit 223a is connected to the fourth group of clock signal lines CK4 (i.e., the seventh clock signal line CKg and the eighth clock signal line CKh), the first level of the third gate driving unit 223a is connected to the third start signal line STV3, and the other levels of the third gate driving units 223a are connected to the output end or the level transfer end of the third gate driving unit 223a of the previous level.

[0073] In some embodiments, Figure 4 , Fig.12 , Fig.13As shown, in the gate driving circuit setting area 102a, the second type of gate driving unit 222 and the third type of gate driving unit 223 are arranged along the second direction Y, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are arranged along the second direction Y, and the second type of gate driving unit 222 and the fourth type of gate driving unit 224 are arranged along the first direction X, and the display panel 1 includes three groups of clock signal lines CK, and the three groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2 and a third group of clock signal lines CK3;

[0074] Wherein, the first type of gate driving unit 221 is connected to the first group of clock signal lines CK1, the second type of gate driving unit 222 and the third type of gate driving unit 223 are connected to the second group of clock signal lines CK2, and the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are connected to the third group of clock signal lines CK3. By arranging the second type of gate driving unit and the third type of gate driving unit along the second direction, the fourth type of gate driving unit and the fifth type of gate driving unit along the second direction, the second type of gate driving unit and the third type of gate driving unit are connected to the second group of clock signal lines, and the fourth type of gate driving unit and the fifth type of gate driving unit are connected to the third group of clock signal lines, two groups of clock signal lines can be reduced in the gate driving circuit arrangement area on one side, thereby reducing the space occupied by the clock signal lines and the wiring connecting the clock signal lines, and reducing the horizontal space occupied by the second type of gate driving unit and the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit, reducing the frame, and reducing power consumption due to the reduction of clock signal lines.

[0075] Specifically, Figure 1 , Fig.12 , Fig.13 , Fig.14 As shown, compared with the comparative display device in which each control unit is arranged along the first direction, in the embodiment of the present application, the second gate drive unit and the third gate drive unit are arranged along the second direction, and the fourth gate drive unit and the fifth gate drive unit are arranged along the second direction, so that the space occupied by the second gate drive unit and the third gate drive unit, and the space occupied by the fourth gate drive unit and the fifth gate drive unit can be reduced, and the second gate drive unit and the third gate drive unit are connected to the same group of clock signal lines, and the fourth gate drive unit and the fifth gate drive unit are connected to the same group of clock signal lines, or the second gate drive unit and the fourth gate drive unit are connected to the same group of clock signal lines, and the third gate drive unit and the fifth gate drive unit are connected to the same group of clock signal lines, which can reduce the space occupied by the clock signal lines and the wiring connecting the clock signal lines, reduce the border, and reduce power consumption.

[0076] Specifically, Figure 4 , Figure 12 to Figure 14 As shown, in a gate driving circuit setting area 102a, when the display panel 1 includes three groups of clock signal lines CK, the three groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2 and a third group of clock signal lines CK3, the first group of clock signal lines CK1 may include a first clock signal line CKa and a second clock signal line CKb, the second group of clock signal lines CK2 may include a third clock signal line CKc and a fourth clock signal line CKd, the third group of clock signal lines CK3 may include a fifth clock signal line CKe and a sixth clock signal line CKf, and when the fourth type of gate driving unit, the second type of gate driving unit and the first type of gate driving unit are sequentially arranged, the first clock signal line CKa and the second clock signal line CKb may be arranged between the first type of gate driving unit and the second type of gate driving unit, the third clock signal line CKc and the fourth clock signal line CKd may be arranged between the second type of gate driving unit and the fourth type of gate driving unit, the fifth clock signal line CKe and the sixth clock signal line CKf may be arranged between the second type of gate driving unit and the fourth type of gate driving unit, or may be arranged on the side of the fourth type of gate driving unit away from the second type of gate driving unit.

[0077] In some embodiments, Fig.12 , Fig.13 As shown, in the first direction X, the second group of clock signal lines CK2 is located between the second type gate driving unit 222 and the fourth type gate driving unit 224, and the third group of clock signal lines CK3 is located on the side of the fourth type gate driving unit 224 away from the second type gate driving unit 222.

[0078] Specifically, Figure 4 , Fig.12 As shown, the first type of gate driving unit 221 includes a plurality of first gate driving units 221a, each first gate driving unit 221a is connected to the first group of clock signal lines CK1 (i.e., the first clock signal line CKa and the second clock signal line CKb), the first-stage first gate driving unit 221a is connected to the first start signal line STV1, and the other first gate driving units 221a are connected to the output end or the stage transmission end of the previous first gate driving unit 221a (depending on the circuit, the output end Pout1 may be directly used as the stage transmission end in a first gate driving unit, or the output end Pout1 and the stage transmission end may be respectively set, and similarly, other gate driving units may also be designed in this way).

[0079] Specifically, Fig.12 , Fig.13As shown, the second type of gate driving unit 222 includes a plurality of stages of second gate driving units 222a, each stage of the second gate driving unit 222a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the third type of gate driving unit 223 includes a plurality of stages of third gate driving units 223a, each stage of the third gate driving unit 223a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the second gate driving unit 222a and the third gate driving unit 223a are alternately arranged along the second direction. The fourth type of gate driving unit 224 includes a plurality of stages of fourth gate driving units 224a, and each stage of the fourth gate driving unit 224a is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf). The fifth type of gate driving unit 225 includes a plurality of stages of fifth gate driving units 225a, and each stage of the fifth gate driving unit 225a is connected to the third group of clock signal lines CK3 (the fifth clock signal line CKe and the sixth clock signal line CKf), and the fifth gate driving unit 225a and the fourth gate driving unit 224a are alternately arranged along the second direction.

[0080] Specifically, Fig.12 , Fig.13 As shown, the first-stage second gate driving unit 222a is connected to the second start signal line STV2, and the other-stage second gate driving units 222a are connected to the output end or the stage transfer end of the second gate driving unit 222a of the previous stage, the first-stage third gate driving unit 223a is connected to the third start signal line STV3, and the other-stage third gate driving units 223a are connected to the output end or the stage transfer end of the third gate driving unit 223a of the previous stage. The first-stage fourth gate driving unit 224a is connected to the fourth start signal line STV4, and the other-stage fourth gate driving units 224a are connected to the output end or the stage transfer end of the fourth gate driving unit 224a of the previous stage, the first-stage fifth gate driving unit 225a is connected to the fifth start signal line STV5, and the other-stage fifth gate driving units 225a are connected to the output end or the stage transfer end of the fifth gate driving unit 225a of the previous stage.

[0081] In some embodiments, Fig.12 , Fig.14As shown, in the gate driving circuit setting area 102a, the second type of gate driving unit 222 and the third type of gate driving unit 223 are arranged along the second direction Y, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are arranged along the second direction Y, and the second type of gate driving unit 222 and the fourth type of gate driving unit 224 are arranged along the first direction X, and the display panel 1 includes three groups of clock signal lines CK, and the three groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2 and a third group of clock signal lines CK3;

[0082] Among them, the first type of gate driving unit 221 is connected to the first group of clock signal lines CK1, the third type of gate driving unit 223 and the fifth type of gate driving unit 225 are connected to the second group of clock signal lines CK2, and the second type of gate driving unit 222 and the fourth type of gate driving unit 224 are connected to the third group of clock signal lines CK3.

[0083] In some embodiments, Fig.12 , Fig.14 As shown, in the first direction X, the second group of clock signal lines CK2 is located between the second type gate driving unit 222 and the fourth type gate driving unit 224, and the third group of clock signal lines CK3 is located between the second type gate driving unit 222 and the fourth type gate driving unit 224.

[0084] Specifically, Fig.12 , Fig.14 As shown, the third type of gate driving unit 223 includes a plurality of third gate driving units 223a, each of which is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the fifth type of gate driving unit 225 includes a plurality of fifth gate driving units 225a, each of which is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd). The second type of gate driving unit 222 includes a plurality of second gate driving units 222a, each of which is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf), and the fourth type of gate driving unit 224 includes a plurality of fourth gate driving units 224a, each of which is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf). The second gate driving unit 222a and the third gate driving unit 223a are alternately disposed along the second direction, and the fifth gate driving unit 225a and the fourth gate driving unit 224a are alternately disposed along the second direction.

[0085] Specifically, the above embodiment is described by taking the second group of clock signal lines CK2 as being located between the second type of gate driving unit 222 and the fourth type of gate driving unit 224, the third group of clock signal lines CK3 as being located between the second type of gate driving unit 222 and the fourth type of gate driving unit 224, the third type of gate driving unit 223 and the fifth type of gate driving unit 225 as being connected to the second group of clock signal lines CK2, and the second type of gate driving unit 222 and the fourth type of gate driving unit 224 as being connected to the third group of clock signal lines CK3 as an example, but the embodiments of the present application are not limited thereto. For example, when the second group of clock signal lines CK2 is located between the second type of gate driving unit 222 and the fourth type of gate driving unit 224, the third group of clock signal lines CK3 is located between the second type of gate driving unit 222 and the fourth type of gate driving unit 224, the second type of gate driving unit 222 and the third type of gate driving unit 223 are connected to the second group of clock signal lines CK2, and the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are connected to the third group of clock signal lines CK3.

[0086] In some embodiments, Fig.12 , Fig.15 As shown, in one of the gate drive circuit setting areas 102a, the display panel 1 includes two groups of clock signal lines CK, the first type of gate drive unit 221 is connected to one group of the clock signal lines CK, and the second type of gate drive unit 222, the third type of gate drive unit 223, the fourth type of gate drive unit 224 and the fifth type of gate drive unit 225 are connected to another group of the clock signal lines CK. By connecting the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit to one group of clock signal lines, three groups of clock signal lines can be reduced in one side of the gate drive circuit setting area, thereby reducing the space occupied by the clock signal lines and the wiring connecting the clock signal lines, and due to the reduction of clock signal lines, power consumption can be reduced.

[0087] Specifically, Figure 4 , Fig.12 , Fig.15As shown, in a gate driving circuit setting area 102a, when the display panel 1 includes two groups of clock signal lines CK, the two groups of clock signal lines CK include a first group of clock signal lines CK1 and a second group of clock signal lines CK2, the first group of clock signal lines CK1 may include a first clock signal line CKa and a second clock signal line CKb, and the second group of clock signal lines CK2 may include a third clock signal line CKc and a fourth clock signal line CKd, and when the fourth type of gate driving unit, the second type of gate driving unit and the first type of gate driving unit are arranged in sequence, the first clock signal line CKa and the second clock signal line CKb may be arranged between the first type of gate driving unit and the second type of gate driving unit, the third clock signal line CKc and the fourth clock signal line CKd may be arranged between the second type of gate driving unit and the fourth type of gate driving unit, or may be arranged on a side of the fourth type of gate driving unit away from the second type of gate driving unit.

[0088] In some embodiments, Fig.12 , Fig.15 As shown, in the second direction Y, the second type of gate driving unit 222 and the third type of gate driving unit 223 are arranged in sequence, the fourth type of gate driving unit 224 and the fifth type of gate driving unit 225 are arranged in sequence, and in the first direction X, the second type of gate driving unit 222, a group of clock signal lines CK connected to the second type of gate driving unit 222, and the fourth type of gate driving unit 224 are arranged. By arranging the second type of gate driving unit and the third type of gate driving unit along the second direction, and arranging the fourth type of gate driving unit and the fifth type of gate driving unit along the second direction, the lateral space occupied by the second type of gate driving unit and the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit can be reduced, and the frame can be reduced.

[0089] Specifically, Figure 1 , Fig.12 , Fig.15 As shown, compared with the comparative display device in which each control unit is arranged along the first direction, in the embodiment of the present application, the second gate driving unit and the third gate driving unit are arranged along the second direction, and the fourth gate driving unit and the fifth gate driving unit are arranged along the second direction, so that the space occupied by the second gate driving unit and the third gate driving unit, and the space occupied by the fourth gate driving unit and the fifth gate driving unit can be reduced, and the second gate driving unit, the third gate driving unit, the fourth gate driving unit and the fifth gate driving unit are connected to the same group of clock signal lines, which can reduce the space occupied by the clock signal lines and the wiring connecting the clock signal lines, reduce the border, and reduce power consumption.

[0090] Specifically, Fig.12 , Fig.15As shown, the second type of gate driving unit 222 includes a plurality of stages of second gate driving units 222a, each stage of the second gate driving unit 222a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), the third type of gate driving unit 223 includes a plurality of stages of third gate driving units 223a, each stage of the third gate driving unit 223a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), the fourth type of gate driving unit 224 includes a plurality of stages of fourth gate driving units 224a, each stage of the fourth gate driving unit 224a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the fifth type of gate driving unit 225 includes a plurality of stages of fifth gate driving units 225a, each stage of the fifth gate driving unit 225a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd). The second gate driving unit 222a and the third gate driving unit 223a are alternately disposed along the second direction, and the fifth gate driving unit 225a and the fourth gate driving unit 224a are alternately disposed along the second direction.

[0091] Specifically, Fig.12 , Fig.15 As shown, the first-stage second gate driving unit 222a is connected to the second start signal line STV2, and the other-stage second gate driving units 222a are connected to the output end or the stage transfer end of the second gate driving unit 222a of the previous stage, the first-stage third gate driving unit 223a is connected to the third start signal line STV3, and the other-stage third gate driving units 223a are connected to the output end or the stage transfer end of the third gate driving unit 223a of the previous stage. The first-stage fourth gate driving unit 224a is connected to the fourth start signal line STV4, and the other-stage fourth gate driving units 224a are connected to the output end or the stage transfer end of the fourth gate driving unit 224a of the previous stage, the first-stage fifth gate driving unit 225a is connected to the fifth start signal line STV5, and the other-stage fifth gate driving units 225a are connected to the output end or the stage transfer end of the fifth gate driving unit 225a of the previous stage.

[0092] In some embodiments, Figure 4 , Figures 16 to 18As shown, in a gate driving circuit setting area 102a, three of the second-type gate driving unit 222, the third-type gate driving unit 223, the fourth-type gate driving unit 224 and the fifth-type gate driving unit 225 are arranged along the second direction Y, and three of the second-type gate driving unit 222, the third-type gate driving unit 223, the fourth-type gate driving unit 224 and the fifth-type gate driving unit 225 are connected to another group of the clock signal lines CK. By arranging three of the second, third, fourth and fifth gate driving units along the second direction, and connecting three of the second, third, fourth and fifth gate driving units to the same group of clock signal lines, the lateral space occupied by the second, third, fourth and fifth gate driving units can be reduced, the border can be reduced, and at least two groups of clock signal lines can be reduced in the gate driving circuit setting area on one side, thereby reducing the space occupied by the clock signal lines and the wiring connecting the clock signal lines, and since the clock signal lines are reduced, the power consumption can be reduced.

[0093] In some embodiments, Figure 4 , Fig.16 , Fig.17 , Fig.18 As shown, taking the second type of gate driving unit 222, the third type of gate driving unit 223 and the fourth type of gate driving unit 224 being arranged along the second direction, and the fifth type of gate driving unit, the second type of gate driving unit and the first type of gate driving unit being arranged along the first direction as an example, the display panel can include three groups of clock signal lines, the three groups of clock signal lines CK include a first group of clock signal lines CK1, a second group of clock signal lines CK2 and a third group of clock signal lines CK3, the first group of clock signal lines CK1 can include a first clock signal line CKa and a second clock signal line CKb, the second group of clock signal lines CK2 can include a third clock signal line CKc and a fourth clock signal line CKd, the third group of clock signal lines CK4 can include a third clock signal line CK5 and a fourth clock signal line CK6, Line CK3 may include a fifth clock signal line CKe and a sixth clock signal line CKf. When the fifth type of gate driving unit, the second type of gate driving unit and the first type of gate driving unit are arranged in sequence, the first clock signal line CKa and the second clock signal line CKb may be arranged between the first type of gate driving unit and the second type of gate driving unit, the third clock signal line CKc and the fourth clock signal line CKd may be arranged between the second type of gate driving unit and the fifth type of gate driving unit, the fifth clock signal line CKe and the sixth clock signal line CKf may be arranged between the second type of gate driving unit and the fifth type of gate driving unit, or may be arranged on the side of the fifth type of gate driving unit away from the second type of gate driving unit.

[0094] Specifically, Figure 4 , Fig.16 As shown, the first type of gate driving unit 221 includes a plurality of first gate driving units 221a, each first gate driving unit 221a is connected to the first group of clock signal lines CK1 (i.e., the first clock signal line CKa and the second clock signal line CKb), the first-stage first gate driving unit 221a is connected to the first start signal line STV1, and the other first gate driving units 221a are connected to the output end or the stage transmission end of the previous first gate driving unit 221a (depending on the circuit, the output end Pout1 may be directly used as the stage transmission end in a first gate driving unit, or the output end Pout1 and the stage transmission end may be respectively set, and similarly, other gate driving units may also be designed in this way).

[0095] Specifically, Fig.16 , Fig.17 As shown, the second type of gate driving unit 222 includes a plurality of stages of second gate driving units 222a, each stage of the second gate driving unit 222a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), the third type of gate driving unit 223 includes a plurality of stages of third gate driving units 223a, each stage of the third gate driving unit 223a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), the fourth type of gate driving unit 224 includes a plurality of stages of fourth gate driving units 224a, each stage of the fourth gate driving unit 224a is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd), and the second gate driving unit 222a, the third gate driving unit 223a and the fourth gate driving unit 224a are alternately arranged along the second direction.

[0096] Specifically, Fig.16 , Fig.17 As shown, the first-stage second gate driving unit 222a is connected to the second start signal line STV2, and the other-stage second gate driving units 222a are connected to the output end or the stage transfer end of the second gate driving unit 222a of the previous stage, and the first-stage third gate driving unit 223a is connected to the third start signal line STV3, and the other-stage third gate driving units 223a are connected to the output end or the stage transfer end of the third gate driving unit 223a of the previous stage. The first-stage fourth gate driving unit 224a is connected to the fourth start signal line STV4, and the other-stage fourth gate driving units 224a are connected to the output end or the stage transfer end of the fourth gate driving unit 224a of the previous stage.

[0097] Specifically, Fig.16 , Fig.18As shown, the fifth type of gate driving unit 225 includes multiple stages of fifth gate driving units 225a, and each stage of the fifth gate driving unit 225a is connected to the third group of clock signal lines CK3 (i.e., the fifth clock signal line CKe and the sixth clock signal line CKf). The first stage of the fifth gate driving unit 225a is connected to the fifth start signal line STV5, and the other stages of the fifth gate driving units 225a are connected to the output end or the stage transmission end of the fifth gate driving unit 225a of the previous stage.

[0098] The above embodiment is described by taking the example that three of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to the same group of clock signal lines, and the other one is connected to another group of clock lines, but the embodiment of the present application is not limited thereto. In a gate driving circuit setting area, the display panel can include two groups of clock signal lines, and the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to the same group of clock signal lines. As for the setting position and connection method of the two groups of clock signal lines, reference can be made to the description in the above embodiment, which will not be repeated here.

[0099] In some embodiments, Figure 5 , Fig.13 , Fig.15 , Fig.17 , Fig. 20 As shown, in a gate drive circuit setting area 102a, the second type of gate drive unit 222 and the third type of gate drive unit 223 are connected to the same group of clock signal lines CK, the second type of gate drive unit 222 includes multiple second gate drive units 222a, and the third type of gate drive unit 223 includes multiple third gate drive units 223a. Along the second direction Y, multiple second gate drive units 222a and multiple third gate drive units 223a are alternately arranged. By connecting the second type of gate drive unit 222 and the third type of gate drive unit 223 to the same group of clock signal lines, the frame can be reduced, the power consumption can be reduced, and the multiple second gate drive units and the multiple third gate drive units are alternately arranged, so that the distance between each level of gate drive unit and the corresponding control signal line can be made smaller, and the voltage drop can be reduced.

[0100] In some embodiments, Fig. 9 , Fig.13 , Fig.15 , Fig. 20As shown, in a gate drive circuit setting area 102a, the fourth type of gate drive unit 224 and the fifth type of gate drive unit 225 are connected to the same group of clock signal lines CK, the fourth type of gate drive unit 224 includes a multi-stage fourth gate drive unit 224a, and the fifth type of gate drive unit 225 includes a multi-stage fifth gate drive unit 225a. Along the second direction Y, the multi-stage fourth gate drive unit 224a and the multi-stage fifth gate drive unit 225a are alternately arranged. By connecting the fourth type of gate drive unit 224 and the fifth type of gate drive unit 225 to the same group of clock signal lines, the frame can be reduced, the power consumption can be reduced, and the multi-stage fourth gate drive unit and the multi-stage fifth gate drive unit are alternately arranged, so that the distance between each level of gate drive unit and the corresponding control signal line can be made smaller, and the voltage drop can be reduced.

[0101] In some embodiments, Fig.25 , Fig.26 As shown, in one of the gate drive circuit setting areas 102a, the display panel 1 further includes a plurality of groups of high potential signal lines VGH, the second type of gate drive unit 222 and the third type of gate drive unit 223 are arranged along the second direction Y, and at least two of the second type of gate drive unit 222, the third type of gate drive unit 223, the fourth type of gate drive unit 224 and the fifth type of gate drive unit 225 are connected to the same group of high potential signal lines VGH. By making at least two of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit connected to the same group of high potential signal lines, at least one group of high potential signal lines can be reduced in the gate drive circuit setting area on one side, and since the number of high potential signal lines is reduced, the electrical signals to be output can also be reduced accordingly, thereby reducing power consumption.

[0102] Specifically, it can be understood that, since the number of high-potential signal lines set in different gate drive units may be different, the number of high-potential signal lines that can be reduced in different designs may be different. And since the setting methods of each gate drive unit are different, the number of high-potential signal lines that can be reduced is different. The setting methods of the high-potential signal lines and the corresponding setting methods of the gate drive units can refer to the setting methods of the clock signal lines in the above embodiments, and the embodiments of this application will not be repeated; only as shown in the example Fig.25 , Fig.26 The design shown is used as an example.

[0103] Specifically, the embodiment of the present application is described by taking an example in which a group of high-potential signal lines includes only one high-potential signal line, but the embodiment of the present application is not limited to this. A group of high-potential signal lines may include multiple high-potential signal lines, and according to different designs in different gate drive units, the number of high-potential signal lines in each group of high-potential signal lines may be different.

[0104] like Fig.25 As shown, the second type gate driving unit 222 and the third type gate driving unit 223 are arranged along the second direction Y, the display panel includes a high potential signal line VGH, and the second type gate driving unit 222 and the third type gate driving unit 223 can be connected to the same group of high potential signal lines VGH.

[0105] like Fig.26 As shown, the fourth type gate driving unit 224 and the fifth type gate driving unit 225 are arranged along the second direction Y, the display panel includes a high potential signal line VGH, and the fourth type gate driving unit 224 and the fifth type gate driving unit 225 can be connected to the same group of high potential signal lines VGH.

[0106] In some embodiments, Fig.25 , Fig.26 As shown, in one of the gate drive circuit setting areas 102a, the display panel 1 further includes a plurality of groups of low potential signal lines VGL, and at least two of the second type of gate drive unit 222, the third type of gate drive unit 223, the fourth type of gate drive unit 224, and the fifth type of gate drive unit 225 are connected to the same group of low potential signal lines VGL. By making at least two of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit, and the fifth type of gate drive unit connected to the same group of low potential signal lines, at least one group of low potential signal lines can be reduced in the gate drive circuit setting area on one side, and since the number of low potential signal lines is reduced, the electrical signals to be output can also be reduced accordingly, thereby reducing power consumption.

[0107] Specifically, it can be understood that, since the number of low-potential signal lines set in different gate drive units may be different, the number of low-potential signal lines that can be reduced in different designs may be different. And since the setting methods of each gate drive unit are different, the number of low-potential signal lines that can be reduced is different. The setting method of the low-potential signal line and the setting method of the corresponding gate drive unit can refer to the setting method of the clock signal line in the above embodiment, and the embodiment of the present application will not be repeated; only as shown in the example Fig.25 , Fig.26 The design shown is used as an example.

[0108] Specifically, the embodiment of the present application is described by taking an example in which a group of low-potential signal lines includes only one low-potential signal line, but the embodiment of the present application is not limited to this. A group of low-potential signal lines may include multiple low-potential signal lines, and according to different designs in different gate driving units, the number of low-potential signal lines in each group of low-potential signal lines may be different.

[0109] like Fig.25 As shown, the second type gate driving unit 222 and the third type gate driving unit 223 are arranged along the second direction Y, the display panel includes a low potential signal line VGL, and the second type gate driving unit 222 and the third type gate driving unit 223 can be connected to the same group of low potential signal lines VGL.

[0110] like Fig.26 As shown, the fourth type gate driving unit 224 and the fifth type gate driving unit 225 are arranged along the second direction Y, the display panel includes a low potential signal line VGL, and the fourth type gate driving unit 224 and the fifth type gate driving unit 225 can be connected to the same group of low potential signal lines VGL.

[0111] In some embodiments, Fig.25 , Fig.26 As shown, in one of the gate drive circuit setting areas 102a, the display panel 1 further includes a plurality of control signal lines CL, and at least two of the second type gate drive unit 222, the third type gate drive unit 223, the fourth type gate drive unit 224, and the fifth type gate drive unit 225 are connected to the same group of control signal lines CL. By connecting at least two of the second type gate drive unit, the third type gate drive unit, the fourth type gate drive unit, and the fifth type gate drive unit to the same group of control signal lines, at least one group of control signal lines can be reduced in the gate drive circuit setting area on one side, and since the number of control signal lines is reduced, the electrical signals to be output can also be reduced accordingly, thereby reducing power consumption.

[0112] Specifically, it can be understood that, since the number of control signal lines set in different gate drive units may be different, and some gate drive units may not even have control signal lines set, the number of control signal lines that can be reduced in different designs may be different. And since the setting methods of each gate drive unit are different, the number of control signal lines that can be reduced is different. The setting method of the control signal line and the setting method of the corresponding gate drive unit can refer to the setting method of the clock signal line in the above embodiment, and the embodiments of this application will not be repeated; only as shown in the example Fig.25 , Fig.26 The design shown is used as an example.

[0113] Specifically, the embodiment of the present application is described by taking an example in which a group of control signal lines includes only one control signal line, but the embodiment of the present application is not limited to this. A group of control signal lines may include multiple control signal lines, and according to different designs in different gate drive units, the number of control signal lines in each group of control signal lines may be different.

[0114] like Fig.25 As shown, the second type gate driving unit 222 and the third type gate driving unit 223 are arranged along the second direction Y, the display panel includes control signal lines CL, and the second type gate driving unit 222 and the third type gate driving unit 223 can be connected to the same group of control signal lines CL.

[0115] like Fig.26 As shown, the fourth type gate driving unit 224 and the fifth type gate driving unit 225 are arranged along the second direction Y, the display panel includes control signal lines CL, and the fourth type gate driving unit 224 and the fifth type gate driving unit 225 can be connected to the same group of control signal lines CL.

[0116] Specifically, compared with the comparative display device, in which each control unit needs to be provided with a group of high-potential signal lines VGH, a group of low-potential signal lines VGL and a group of control signal lines CL, the embodiment of the present application reduces the number of high-potential signal lines VGH, low-potential signal lines VGL and control signal lines CL, reduces the border, and reduces power consumption.

[0117] Specifically, it can be understood that each pixel driving circuit can drive one sub-pixel, and one row of sub-pixels corresponds to one row of pixel driving circuits.

[0118] In the embodiment of the present application, the pixel driving circuit 21 may be a 7T1C, 7T2C, 8T2C, 8T3C, 8T4C or other pixel circuit. The following embodiment is described by taking the 8T2C pixel circuit as an example.

[0119] In some embodiments, Figure 2 , Fig.21 As shown, the pixel driving circuit 21 includes a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first light emitting transistor T5, a first initialization transistor T4 and a second initialization transistor T7, one electrode of the driving transistor T1, one electrode of the switching transistor T2 and one electrode of the first light emitting transistor T5 are connected to a first node A, one electrode of the compensation transistor T3, the gate of the driving transistor T1 and one electrode of the first initialization transistor T4 are connected to a second node Q, and another electrode of the compensation transistor T3, another electrode of the driving transistor T1 and one electrode of the second initialization transistor T7 are connected to a third node B;

[0120] The output terminal Pout1 of the first type gate driving unit 221 is connected to the gate of the switching transistor T2, the output terminal Nout1 of the second type gate driving unit 222 is connected to the gate of the compensation transistor T3, the output terminal Nout2 of the third type gate driving unit 223 is connected to the gate of the first initialization transistor T4, the output terminal Pout2 of the fourth type gate driving unit 224 is connected to the gate of the second initialization transistor T7, and the output terminal EMout of the fifth type gate driving unit 225 is connected to the gate of the first light-emitting transistor T5.

[0121] Specifically, Fig.21 As shown, the pixel driving circuit 21 may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first initialization transistor T4, a second initialization transistor T7, a third initialization transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boost capacitor Cboost and a storage capacitor Cst, the storage capacitor Cst includes a first plate and a second plate, and the boost capacitor Cboost includes a third plate and a fourth plate.

[0122] See also Figure 4, the first electrode of the switching transistor T2 is connected to the data signal line Data, the second electrode of the switching transistor T2 is connected to the first node A, and the gate of the switching transistor T2 is connected to the switching control signal line Pscan1; the first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the third node B, and the gate of the driving transistor T1 is connected to the second node Q; the first electrode of the compensation transistor T3 is connected to the second node Q, the second electrode of the compensation transistor T3 is connected to the third node B, and the gate of the compensation transistor T3 is connected to the compensation control signal line Nscan1; the first electrode of the first initialization transistor T4 is connected to the first reset signal line Vi1, the second electrode of the first initialization transistor T4 is connected to the second node Q, and the gate of the first initialization transistor T4 is connected to the first reset control signal line Nscan2; the first electrode of the second initialization transistor T7 is connected to the second reset signal line Vi2, the second electrode of the second initialization transistor T7 is connected to the fourth node D, that is, the anode of the light emitting device LED, and the gate of the second initialization transistor T7 is connected to the first reset signal line Vi1. The first electrode of the third initialization transistor T8 is connected to the third reset signal line Vi3, the second electrode of the third initialization transistor T8 is connected to the first node A, and the gate of the third initialization transistor T8 is connected to the second reset control signal line Pscan2; the first electrode of the first light-emitting transistor T5 is connected to the high potential power line VDD, the second electrode of the first light-emitting transistor T5 is connected to the first node A, and the gate of the first light-emitting transistor T5 is connected to the light-emitting control signal line EM; the first electrode of the second light-emitting transistor T6 is connected to the third node B, the second electrode of the second light-emitting transistor T6 is connected to the fourth node D, and the gate of the second light-emitting transistor T6 is connected to the light-emitting control signal line EM; the third plate of the boost capacitor Cboost is connected to the second node Q, and the fourth plate of the boost capacitor Cboost is connected to the gate of the switching transistor T2; the first plate of the storage capacitor Cst is connected to the second node Q, and the second plate of the storage capacitor Cst is connected to the high potential power line VDD; the cathode of the light-emitting device is connected to the low potential power line VSS.

[0123] In this embodiment, the high potential power line VDD is used to provide a constant high voltage level to the pixel driving circuit 21 , and the low potential power line VSS is used to provide a constant low voltage level to the pixel driving circuit 21 .

[0124] In this embodiment, the switch transistor T2, the drive transistor T1, the second initialization transistor T7, the third initialization transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 can be one of P-type transistors or N-type transistors, and the compensation transistor T3 and the first initialization transistor T4 can be the other of P-type transistors or N-type transistors; this application is explained by taking the switch transistor T2, the drive transistor T1, the second initialization transistor T7, the third initialization transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as P-type transistors, and the compensation transistor T3 and the first initialization transistor T4 as N-type transistors as an example.

[0125] In this embodiment, the switch transistor T2, the drive transistor T1, the second initialization transistor T7, the third initialization transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 may be one of a silicon semiconductor transistor (e.g., a low-temperature polycrystalline silicon thin film transistor) and an oxide semiconductor transistor (e.g., an indium gallium zinc oxide thin film transistor), and the compensation transistor T3 and the first initialization transistor T4 may be the other of a silicon semiconductor transistor (e.g., a low-temperature polycrystalline silicon thin film transistor) and an oxide semiconductor transistor (e.g., an indium gallium zinc oxide thin film transistor); the present application takes the switch transistor T2, the drive transistor T1, the second initialization transistor T7, the third initialization transistor T8, the first light-emitting transistor T5, and the second light-emitting transistor T6 as silicon semiconductor transistors (e.g., low-temperature polycrystalline silicon thin film transistors), and the compensation transistor T3 and the first initialization transistor T4 as oxide semiconductor transistors (e.g., indium gallium zinc oxide thin film transistors) as an example for description.

[0126] In this embodiment, the capacitance value of the boost capacitor Cboost is less than the capacitance value of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the second node Q, so the capacitance of the storage capacitor Cst is relatively large, for example, the capacitance value range of the storage capacitor Cst can be 45fF to 55fF, and the capacitance value range of the boost capacitor Cboost can be 5fF to 15fF.

[0127] In this embodiment, the first electrode may be one of the source and the drain, and the second electrode may be the other of the source and the drain.

[0128] Specifically, the output terminal Pout1 of the first type gate driving unit 221 can be connected to the gate of the switching transistor T2 through the switching control signal line Pscan1, the output terminal Nout1 of the second type gate driving unit 222 can be connected to the gate of the compensation transistor T3 through the compensation control signal line Nscan1, the output terminal Nout2 of the third type gate driving unit 223 can be connected to the gate of the first initialization transistor T4 through the first reset control signal line Nscan2, the output terminal Pout2 of the fourth type gate driving unit 224 can be connected to the gate of the second initialization transistor T7 through the second reset control signal line Pscan2, and the output terminal EMout of the fifth type gate driving unit 225 can be connected to the gate of the first light-emitting transistor T5 through the light-emitting control signal line EM.

[0129] In some embodiments, Figure 3 , Fig. 27 , Fig.28 As shown, the second type of gate driving unit 222 includes a multi-stage second gate driving unit 222a, and the output terminal Nout1 of the first stage of the second gate driving unit 222a is connected to the gates of the compensation transistors T3 of the pixel driving circuits 21 of two adjacent rows; or the output terminal of the first stage of the second gate driving unit 222a is connected to the gates of the compensation transistors T3 of the pixel driving circuits 21 of one row;

[0130] And / or, the third type gate driving unit 223 includes a multi-stage third gate driving unit 223a, and the output terminal Nout2 of the third gate driving unit 223a of one stage is connected to the gates of the first initialization transistors T4 of the pixel driving circuits 21 of two adjacent rows; or the output terminal Nout2 of the third gate driving unit 223a of one stage is connected to the gate of the first initialization transistor T4 of the pixel driving circuits 21 of one row;

[0131] And / or, the fourth type of gate driving unit 224 includes a multi-stage fourth gate driving unit 224a, and the output terminal Pscan2 of the fourth gate driving unit 224a of the first stage is connected to the gate of the second initialization transistor T7 of the pixel driving circuit 21 of two adjacent rows; or the output terminal Pscan2 of the fourth gate driving unit 224a of the first stage is connected to the gate of the second initialization transistor T7 of the pixel driving circuit 21 of one row;

[0132] And / or, the fifth type of gate driving unit 225 includes a multi-stage fifth gate driving unit 225a, and the output end EMout of the fifth gate driving unit 225a of one stage is connected to the gate of the first light-emitting transistor T5 of the pixel driving circuit 21 of two adjacent rows; or the output end EMout of the fifth gate driving unit 225a of one stage is connected to the gate of the first light-emitting transistor T5 of the pixel driving circuit 21 of one row.

[0133] Specifically, when the gate driving unit is connected to the pixel driving circuit, except that the gate driving units of each level in the first type of gate driving unit need to be respectively connected to the switching transistors in each row of pixel driving circuit, the first level of gate driving unit in the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit can drive the transistors in two rows of pixel driving units, or can only drive the transistors in one row of pixel driving circuit.

[0134] Specifically, Fig. 27 , Fig.28 by Figure 3 The design of the gate drive circuit on one side is specifically described. It can be understood that when the design in the gate drive circuit is other designs, reference can be made to Fig. 27 , Fig.28 For example, when the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, the design of the fifth gate driving unit and the fourth gate driving unit can refer to Fig. 27 , Fig.28 The designs of the third gate driving unit and the second gate driving unit are not described in detail here.

[0135] Specifically, since the first type of gate driving unit shown in the embodiment of the present application adopts a first-level gate driving unit connected to a row of switch control signal lines, a second-level gate driving unit connected to two rows of compensation control signal lines, a third-level gate driving unit connected to two rows of first reset control signal lines, a fourth-level gate driving unit connected to two rows of second reset control signal lines, and a fifth-level gate driving unit connected to two rows of light-emitting control signal lines, therefore, Figure 3 , Figure 8 , Fig.12 , Fig.16 , Fig.18 In the gate driving circuit setting area 102a on one side, two first-type gate driving units are shown to indicate that the first gate driving unit in the first-type gate driving unit is twice the number of other gate driving units (designs such as invalid gate driving units are not considered).

[0136] In different embodiments, since the gate driving units connected to the clock signal lines are different and the setting positions of the clock signal lines are different, the signals of the clock signal lines in different embodiments can be made the same or different. For example, in some embodiments, the second gate driving unit 222a is connected to the third clock signal line CKc and the fourth clock signal line CKd. In some embodiments, the fourth gate driving unit 224a is connected to the third clock signal line CKc and the fourth clock signal line CKd. Since the setting positions and connection relationships of the third clock signal line CKc and the fourth clock signal line CKd are different in the two embodiments, in the two embodiments, the signals of the third clock signal line CKc can be different and the fourth clock signal line CKd can be different.

[0137] When the second type of gate driving unit and the third type of gate driving unit are arranged along the first direction, the embodiment of the present application is described by taking the second type of gate driving unit being arranged between the first type of gate driving unit and the third type of gate driving unit as an example, but the embodiment of the present application is not limited to this, and the third type of gate driving unit can be arranged between the second type of gate driving unit and the first type of gate driving unit.

[0138] When the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the first direction, the embodiment of the present application is explained by taking the fourth type of gate driving unit being arranged between the first type of gate driving unit and the fifth type of gate driving unit as an example, but the embodiment of the present application is not limited to this. The fifth type of gate driving unit can be arranged between the fourth type of gate driving unit and the first type of gate driving unit.

[0139] The embodiment of the present application is described by taking the second type of gate driving unit and the third type of gate driving unit as an example, but the embodiment of the present application is not limited thereto. The fourth type of gate driving unit and the fifth type of gate driving unit can be arranged between the second type of gate driving unit and the third type of gate driving unit and the first type of gate driving unit. Similarly, other arrangement modes are not described in detail here.

[0140] When the second type of gate driving unit and the third type of gate driving unit are arranged along the second direction, the embodiment of the present application takes the third type of gate driving unit as the topmost gate driving unit in the column as an example for explanation, but the embodiment of the present application is not limited to this, and the second type of gate driving unit can be used as the topmost gate driving unit in the column.

[0141] When the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, the embodiment of the present application takes the fifth type of gate driving unit as the topmost gate driving unit in the column as an example for explanation, but the embodiment of the present application is not limited to this, and the fourth type of gate driving unit can be used as the topmost gate driving unit in the column.

[0142] The above embodiments are described by taking the second type of gate driving unit and the third type of gate driving unit as being arranged along the second direction, and / or the fourth type of gate driving unit and the fifth type of gate driving unit as being arranged along the second direction as an example, but the embodiments of the present application are not limited thereto. For example, the second type of gate driving unit and the fourth type of gate driving unit or the fifth type of gate driving unit may be arranged along the second direction, or the third type of gate driving unit and the fourth type of gate driving unit or the fifth type of gate driving unit may be arranged along the second direction.

[0143] When the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit are arranged along the second direction, the embodiment of the present application is described by taking the fourth type of gate driving unit, the third type of gate driving unit and the second type of gate driving unit as an example in which they are arranged in sequence from top to bottom, but the embodiment of the present application is not limited thereto, and the fourth type of gate driving unit, the second type of gate driving unit and the third type of gate driving unit may be arranged in sequence from top to bottom, or the third type of gate driving unit, the second type of gate driving unit and the fourth type of gate driving unit may be arranged in sequence from top to bottom, or the third type of gate driving unit, the fourth type of gate driving unit and the second type of gate driving unit may be arranged in sequence from top to bottom, or the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit may be arranged in sequence from top to bottom.

[0144] The above embodiments are described by taking the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit as an example in which they are arranged along the second direction, but the embodiments of the present application are not limited to this. For example, the second type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit may be arranged along the second direction, or the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit may be arranged along the second direction.

[0145] When the second, third, fourth and fifth gate drive units are arranged along the second direction, the embodiment of the present application is described by taking the fifth, fourth, third and second gate drive units as an example in which the gate drive units are arranged in sequence from top to bottom, but the embodiment of the present application is not limited to this, and each gate drive unit may be arranged in other ways, for example, the second, third, fourth and fifth gate drive units may be arranged in sequence from top to bottom.

[0146] It can be understood that, in the above embodiments, when there is no conflict between the setting position of the gate driving unit and the connection relationship of the clock signal line, the setting position of the gate driving unit and the connection relationship of the clock signal line in different embodiments can be combined with each other.

[0147] Specifically, it can be understood that each group of clock signal lines may include two clock signal lines. In two adjacent levels of the same type of gate driving units, in one level of gate driving unit, one clock signal line is used as the first type of clock signal line XCK, and the other clock signal line is used as the second type of clock signal line YCK. In the next level of gate driving unit, one clock signal line is used as the second type of clock signal line YCK, and the other clock signal line is used as the first type of clock signal line XCK. For example, the second type of gate driving unit 222 includes a plurality of second gate driving units 222a, and the second type of gate driving unit 222 is connected to The third clock signal line CKc and the fourth clock signal line CKd, in two adjacent levels of second gate driving units, in one level of the second gate driving unit 222a, the third clock signal line CKc serves as the first type of clock signal line XCK, and the fourth clock signal line CKd serves as the second type of clock signal line YCK, and in another level of the second gate driving unit 222a, the third clock signal line CKc serves as the second type of clock signal line YCK, and the fourth clock signal line CKd serves as the first type of clock signal line XCK. Similarly, the connection relationship between other clock signal lines and gate driving units at each level can be determined, which will not be repeated here.

[0148] In order to illustrate the connection relationship between each gate driving unit and the clock signal line, the embodiment of the present application provides three circuits to illustrate a specific circuit corresponding to each gate driving unit. It can be understood that the embodiment of the present application is not limited to the circuit of the gate driving unit. For other circuits, the design in the present application can also be adopted, which will not be repeated here.

[0149] like Fig. 22 As shown, the first circuit 201 may include a stage transmission circuit 211 , an output circuit 212 , a stage transmission frequency division circuit 213 and an output frequency division circuit 214 .

[0150] like Fig. 22 As shown, the level transmission circuit 211 includes a level transmission receiving circuit 2111 and a level transmission output circuit 2112. The level transmission receiving circuit 2111 is used to receive the level transmission signal generated by the upper-level first-type circuit 201. The level transmission output circuit 2112 is electrically connected to the level transmission receiving circuit 2111 through the control node P1 and the control node Q1, and is used to output the level transmission signal of this level to the lower-level first-type circuit 201 according to the signal of the control node P1 and the signal of the control node Q1.

[0151] like Fig. 22As shown, the output circuit 212 is electrically connected to the control node P1 and the control node Q1 in the stage transmission circuit 211, and the output circuit 212 outputs a gate control signal according to the frequency division control signal, the signal of the control node P1 and the control node Q1. The output circuit 212 is electrically connected to the clock signal line, and the clock signal lines connected to the two adjacent first-level circuits 201 are different.

[0152] Specifically, taking the second gate driving unit as the first type of circuit, and the second type of gate driving unit 222 connected to the third clock signal line CKc and the fourth clock signal line CKd as an example, in two adjacent levels of the first type of circuit, in one level of the first type of circuit, the point where the first type of clock signal line XCK is located is connected to the third clock signal line CKc, and the second type of clock signal line YCK is connected to the fourth clock signal line CKd, and in another level of the first type of circuit, the point where the first type of clock signal line XCK is located is connected to the fourth clock signal line CKd, and the second type of clock signal line YCK is connected to the third clock signal line CKc. Similarly, the relationship between other clock signal lines and the first type of clock signal lines and the second type of clock signal lines can be determined, and the connection relationship between various types of gate driving units and clock signal lines can be determined accordingly, which will not be repeated in the following embodiments.

[0153] like Fig. 22 As shown, one end of the output frequency dividing circuit 214 is connected to the output circuit 212 at the control node S1, and the other end of the output frequency dividing circuit 214 is connected to the stage transmission circuit 211 at one of the control node P1 or the control node Q1. The output frequency dividing circuit 214 controls the signal transmission between one of the control node P1 and the control node Q1 and the output circuit 212 according to the signal of one of the control node P1 or the control node Q1 and the frequency dividing control signal.

[0154] like Fig. 22 As shown, the stage transmission frequency division circuit 213 is electrically connected to the stage transmission receiving circuit 2111 through the control node R1, and is electrically connected to the stage transmission output circuit 2112 through the control node P1 or the control node Q1, and is used to control the signal of one of the control nodes P1 and Q1 according to the frequency division control signal, so as to control the stage transmission output circuit 2112 to output the stage transmission signal of the current stage.

[0155] like Fig. 22As shown, the output frequency division circuit 214 includes an eighteenth transistor T18A and a twentieth transistor T20A, the gate of the eighteenth transistor T18A is connected to the first frequency division signal line FDL1, the source of the eighteenth transistor T18A is electrically connected to the control node P1 or the control node Q1, and the drain of the eighteenth transistor T18A is electrically connected to the control node S1; the gate of the twentieth transistor T20A is electrically connected to the control node Z1 of the stage transfer circuit 211, the source of the twentieth transistor T20A is electrically connected to the first frequency division signal line FDL1, and the drain of the twentieth transistor T20A is electrically connected to the gate of the eighteenth transistor T18A.

[0156] like Fig. 22 As shown, the stage transmission frequency division circuit 213 includes a seventeenth transistor T17A, the gate of the seventeenth transistor T17A is electrically connected to the second frequency division signal line FDL2, the source of the seventeenth transistor T17A is electrically connected to the stage transmission receiving circuit 2111 through the control node R1, and the drain of the seventeenth transistor T17A is electrically connected to the control node P1 or the control node Q1.

[0157] like Fig. 22 As shown, the stage transmission output circuit 2112 includes a tenth transistor T10A and a ninth transistor T9A, the gate of the tenth transistor T10A is electrically connected to the control node P1, the source of the tenth transistor T10A is electrically connected to the high potential signal line VGH, and the drain of the tenth transistor T10A is electrically connected to the stage transmission output terminal OUT0 for outputting the stage transmission signal in the first circuit 201; the gate of the ninth transistor T9A is electrically connected to the control node Q1, the source of the ninth transistor T9A is electrically connected to the low potential signal line VGL, and the drain of the ninth transistor T9A is electrically connected to the stage transmission output terminal OUT0.

[0158] like Fig. 22 As shown, the output circuit 212 includes a twenty-second transistor T22A and a twenty-first transistor T21A, the gate of the twenty-second transistor T22A is electrically connected to the control node S1, the source of the twenty-second transistor T22A is electrically connected to the high potential signal line VGH, and the drain of the twenty-second transistor T22A is connected to the first output terminal OUT1; the gate of the twenty-first transistor T21A is electrically connected to the control node P1 or the control node Q1, the source of the twenty-first transistor T21A is electrically connected to the low potential signal line VGL, and the drain of the twenty-first transistor T21A is connected to the first output terminal OUT1.

[0159] like Fig. 22As shown, the stage transmission receiving circuit 2111 includes a third transistor T3A, a gate of the third transistor T3A is connected to the first clock signal line XCK, a source of the third transistor T3A is connected to the first input terminal IN1, and a drain of the third transistor T3A is connected to the control node D1.

[0160] Specifically, the first input terminal can be connected to the start signal line. For example, if the second gate driving unit is a first circuit, the first input terminal of the first-level first circuit can be the second start signal line STV2, and the first input terminals of other first circuits can be the level transmission output terminal OUT0 of a certain level of the first circuit, for example, the level transmission output terminal OUT0 of the previous level of the first circuit. Similarly, the connection relationship between other input terminals and the start signal line, the level transmission output terminal and the output terminal can be determined.

[0161] Specifically, the first output terminal OUT1 can be connected to the gate of the transistor in the pixel driving circuit. For example, if the second gate driving unit is the first circuit, the first output terminal OUT1 is actually the output terminal Nout1 of the second gate driving unit. The first output terminal OUT1 can be connected to the gate of the compensation transistor.

[0162] It can be understood that in some circuits, the level transmission output terminal and the signal output terminal will be independently set. In this case, the input terminal can be connected to the level transmission output terminal. In some circuits, the signal output terminal will be multiplexed as the level transmission output terminal. In this case, the input terminal can be connected to the signal output terminal.

[0163] like Fig. 22 As shown, the stage transmission receiving circuit 2111 includes a fourth transistor T4A, a fifth transistor T5A, a sixth transistor T6A and a seventh transistor T7A arranged in series, the gate of the fifth transistor T5A is electrically connected to the drain of the third transistor T3A, the source of the fifth transistor T5A is connected to the first type of clock signal line XCK, the gate of the fourth transistor T4A is connected to the first type of clock signal line XCK, the source of the fourth transistor T4A is connected to the low potential signal line VGL, the drain of the fourth transistor T4A, the gate of the sixth transistor T6A and the drain of the fifth transistor T5A are electrically connected to the control node C1, the drain of the sixth transistor T6A and the source of the seventh transistor T7A are electrically connected to the control node A1, the source of the sixth transistor T6A and the gate of the seventh transistor T7A are both connected to the second type of clock signal line CK, and the drain of the seventh transistor T7A is electrically connected to the control node R1.

[0164] like Fig. 22As shown, the stage transmission receiving circuit 2111 includes a thirteenth transistor T13A, a first capacitor C1A, a first transistor T1A and a second transistor T2A arranged in series, the gate of the thirteenth transistor T13A is electrically connected to the control signal line CL, the source of the thirteenth transistor T13A is connected to the high potential signal line VGH, the drain of the thirteenth transistor T13A is electrically connected to the control node D1, the gate of the first transistor T1A is electrically connected to the drain of the fourth transistor T4A, the source of the first transistor T1A is connected to the high potential signal line VGH, the drain of the first transistor T1A and the source of the second transistor T2A are electrically connected to the control node E1, the drain of the second transistor T2A is connected to the second type clock signal line YCK, the gate of the second transistor T2A is electrically connected to the control node F1, and the first capacitor C1A is electrically connected between the gate and the drain of the second transistor T2A.

[0165] like Fig. 22 As shown, the stage transmission receiving circuit 2111 includes an eleventh transistor T11A, a second capacitor C2A, and a twelfth transistor T12A. The stage transmission output circuit 2112 may further include a third capacitor C3A electrically connected between the gate and the source of the tenth transistor T10A. The gate of the eleventh transistor T11A and the gate of the twelfth transistor T12A may both be connected to the low potential signal line VGL to maintain opening. The source and the drain of the eleventh transistor T11A are electrically connected to the drain of the fourth transistor T4A and the gate of the sixth transistor T6A at the control node C1 and the control node B1, respectively. The second capacitor C2A is electrically connected between the gate and the drain of the sixth transistor T6A. The source and the drain of the twelfth transistor T12A are electrically connected to the drain of the third transistor T3A and the control node Q1, respectively.

[0166] like Fig. 22 As shown, the stage transmission receiving circuit 2111 includes an eighth transistor T8A, the gate of the eighth transistor is connected to the control node Z1, the drain of the nineteenth transistor T19A is connected to the high potential signal line VGH, and the source of the nineteenth transistor T19A is connected to the control node S1.

[0167] like Fig. 22 As shown, the first circuit further includes a nineteenth transistor T19A, the gate of the nineteenth transistor T19A is connected to the control node Z1, the drain of the eighth transistor T8A is connected to the high potential signal line VGH, and the source of the eighth transistor T8A is connected to the control node P1.

[0168] like Fig. 22As shown, the stage transmission receiving circuit 2111 includes a fourteenth transistor T14A and a sixteenth transistor T16A. The source of the fourteenth transistor T14A is connected to the first input terminal IN1, the gate of the fourteenth transistor T14A is connected to the first type clock signal line XCK, and the drain of the fourteenth transistor T14A is electrically connected to the gate of the second transistor T2A; the gate and source of the sixteenth transistor T16A are both electrically connected to the gate of the second transistor T2A, and the drain of the sixteenth transistor T16A is electrically connected to the control node Q1.

[0169] like Fig. 22 As shown, the stage transmission receiving circuit 2111 includes a fifteenth transistor T15A, the gate of the fifteenth transistor T15A can be connected to the low potential signal line VGL, and the source and drain of the fifteenth transistor T15A can be electrically connected to the drain of the fourteenth transistor T14A and the gate of the second transistor T2A respectively.

[0170] like Fig. 22 As shown, the first circuit 201 also includes a first coupling capacitor C4A and a second coupling capacitor C5A, one end of the first coupling capacitor C4A is connected to the high potential signal line VGH, the other end of the first coupling capacitor C4A is connected to the gate of the twenty-second transistor T22A, one end of the second coupling capacitor C5A is connected to the high potential signal line VGH, and the other end of the second coupling capacitor C5A and the gate of the eighteenth transistor T18A are connected to the control node X1.

[0171] It should be noted that the second gate driving unit and the third gate driving unit may be the first type of circuit, and accordingly, Fig. 22 The first output terminal OUT1 can be the output terminal Nout1 of the second gate driving unit and the output terminal Nout2 of the third gate driving unit, respectively. Correspondingly, the first input terminal IN1 can be the second start signal line STV2 or the level transmission output terminal, the third start signal line STV3 or the level transmission output terminal, respectively. The connection relationship of the clock signal lines connected to the second gate driving unit and the third gate driving unit can be determined according to the first type of clock signal line XCK and the second type of clock signal line YCK.

[0172] Specifically, the above embodiments are described by taking the first circuit having a frequency dividing circuit as an example, but the embodiments of the present application are not limited to this. The first circuit may not have a frequency dividing circuit, that is, a stepless transmission frequency dividing circuit and an output frequency dividing circuit.

[0173] like Fig.23As shown, the second circuit 202 may include a receiving circuit 215 and an exporting circuit 216. The receiving circuit 215 is used to receive the level transmission signal generated by the upper-level second circuit 202. The exporting circuit 216 is electrically connected to the receiving circuit 215 through the control node P2 and the control node Q2, and is used to output the control signal of this level, such as a light-emitting control signal or a second reset control signal, according to the signal of the control node P2 and the signal of the control node Q2.

[0174] like Fig.23 As shown, the derivation circuit 216 includes a tenth transistor T10B and a ninth transistor T9B, the gate of the tenth transistor T10B is electrically connected to the control node P2, the source of the tenth transistor T10B is electrically connected to the high potential signal line VGH, and the drain of the tenth transistor T10B is electrically connected to the second output terminal OUT2 in the second circuit 202; the gate of the ninth transistor T9B is electrically connected to the control node Q2, the source of the ninth transistor T9B is electrically connected to the low potential signal line VGL, and the drain of the ninth transistor T9B is electrically connected to the second output terminal OUT2.

[0175] like Fig.23 As shown, the receiving circuit 215 includes a third transistor T3B, a gate of the third transistor T3B is connected to the first clock signal line XCK, a source of the third transistor T3B is connected to the second input terminal IN2, and a drain of the third transistor T3B is connected to the control node D2.

[0176] like Fig.23 As shown, the receiving circuit 215 includes a fourth transistor T4B, a fifth transistor T5B, a sixth transistor T6B and a seventh transistor T7B, the gate of the fifth transistor T5B is electrically connected to the drain of the third transistor T3B, the source of the fifth transistor T5B is connected to the first type of clock signal line XCK, the gate of the fourth transistor T4B is connected to the first type of clock signal line XCK, the source of the fourth transistor T4B is connected to the low potential signal line VGL, the drain of the fourth transistor T4B, the gate of the sixth transistor T6B and the drain of the fifth transistor T5B are electrically connected to the control node C2, the drain of the sixth transistor T6B and the source of the seventh transistor T7B are electrically connected to the control node A2, the source of the sixth transistor T6B and the gate of the seventh transistor T7B are both connected to the second type of clock signal line YCK, and the drain of the seventh transistor T7B is electrically connected to the control node P2.

[0177] like Fig.23As shown, the receiving circuit 215 includes a thirteenth transistor T13B, a first capacitor C1B, a first transistor T1B and a second transistor T2B, the gate of the thirteenth transistor T13B is electrically connected to the control signal line CL, the source of the thirteenth transistor T13B is connected to the high potential signal line VGH, the drain of the thirteenth transistor T13B is electrically connected to the control node D2, the gate of the first transistor T1B is electrically connected to the drain of the fourth transistor T4B, the source of the first transistor T1B is connected to the high potential signal line VGH, the drain of the first transistor T1B and the source of the second transistor T2B are electrically connected to the control node E2, the drain of the second transistor T2B is connected to the second type clock signal YCK, the gate of the second transistor T2B is also electrically connected to the stage transmission signal generated by the upper second circuit 202, and the first capacitor C1B is electrically connected between the gate and the drain of the second transistor T2B.

[0178] like Fig.23 As shown, the receiving circuit 215 includes an eleventh transistor T11B, a second capacitor C2B, and a twelfth transistor T12B. The derivation circuit 216 may further include a third capacitor C3B electrically connected between the gate and the source of the tenth transistor T10B. The gate of the eleventh transistor T11B and the gate of the twelfth transistor T12B may both be connected to the low potential signal line VGL to maintain the opening. The source and the drain of the eleventh transistor T11B are electrically connected to the drain of the fourth transistor T4B and the gate of the sixth transistor T6B at the control node C2 and the control node B2, respectively. The second capacitor C2B is electrically connected between the gate and the drain of the sixth transistor T6B. The source and the drain of the twelfth transistor T12B are electrically connected to the control node D2 and the control node Q2, respectively.

[0179] like Fig.23 As shown, the receiving circuit 215 includes an eighth transistor T8B, the gate of the eighth transistor is connected to the control node D2, the drain of the eighth transistor T8B is connected to the high potential signal line VGH, and the source of the eighth transistor T8B is connected to the control node P2.

[0180] Specifically, the fourth gate driving unit and the fifth gate driving unit may be the second circuit, and accordingly, Fig.23The second output terminal OUT2 in the circuit can be the output terminal Pout2 of the fourth gate driving unit and the output terminal EMout of the fifth gate driving unit, respectively. Correspondingly, the second input terminal IN2 can be the second output terminal of the fourth start signal line STV4 or the second circuit of the other level, the fifth start signal line STV5 or the second output terminal of the second circuit of the other level, respectively. The connection relationship of the clock signal lines connected to the fourth gate driving unit and the fifth gate driving unit can be determined according to the first clock signal line XCK and the second clock signal line YCK. For example, the fourth gate driving unit is a second circuit, and the fourth gate driving unit is connected to the second group of clock signal lines CK2 (i.e., the third clock signal line CKc and the fourth clock signal line CKd) as an example. In the adjacent two levels of the second circuit, in the first level of the second circuit, the point where the first clock signal line XCK is located is connected to the third clock signal line CKc, and the second clock signal line YCK is connected to the fourth clock signal line CKd. In the other level of the second circuit, the point where the first clock signal line XCK is located is connected to the fourth clock signal line CKd, and the second clock signal line YCK is connected to the third clock signal line CKc. Similarly, the relationship between other clock signal lines and the first type of clock signal lines and the second type of clock signal lines can be determined, and the connection relationship between various types of gate driving units and the clock signal lines can be determined accordingly, which will not be repeated in the following embodiments.

[0181] like Fig.24 As shown, the third circuit 203 may include a first transistor T1C, a second transistor T2C, a third transistor T3C, a fourth transistor T4C, a fifth transistor T5C, a sixth transistor T6C, a seventh transistor T7C, an eighth transistor T8C, a first capacitor C1C and a second capacitor C2C.

[0182] like Fig.24 As shown, the gate of the seventh transistor T7C is electrically connected to the control node P3, the source of the seventh transistor T7C is electrically connected to the high potential signal line VGH, and the drain of the seventh transistor T7C is electrically connected to the third output terminal OUT3 in the third circuit 203; the gate of the sixth transistor T6C is electrically connected to the control node Q3, the source of the sixth transistor T6C is connected to the second type of clock signal YCK, and the drain of the sixth transistor T6C is electrically connected to the third output terminal OUT3; at the same time, the two ends of the first capacitor C1C are respectively connected to the control node Q3 and the third output terminal OUT3, and the two ends of the second capacitor C2C are respectively connected to the control node Q3 and the third output terminal OUT3.

[0183] like Fig.24 As shown, the gate of the third transistor T3C is connected to the first-type clock signal line XCK, the source of the third transistor T3C is connected to the third input terminal IN3, and the drain of the third transistor T3C is connected to the control node D3.

[0184] like Fig.24 As shown, the gate of the fifth transistor T5C is electrically connected to the control node D3, the source of the fifth transistor T5C is connected to the first type of clock signal line XCK, the gate of the fourth transistor T4C is connected to the first type of clock signal line XCK, the source of the fourth transistor T4C is connected to the low potential signal line VGL, and the drain of the fourth transistor T4C is electrically connected to the control node P3 and the drain of the fifth transistor T5C.

[0185] like Fig.24 As shown, the gate of the first transistor T1C is electrically connected to the control node P3, the source of the first transistor T1C is connected to the high potential signal line VGH, the drain of the first transistor T1C is electrically connected to the source of the second transistor T2C, the drain of the second transistor T2C is connected to the control node D3, and the gate of the second transistor T2C is connected to the second type clock signal YCK.

[0186] like Fig.24 As shown, the gate of the eighth transistor T8C is connected to the low potential signal line VGL, and the source and drain of the eighth transistor T8C are connected to the control node D3 and the control node Q3 respectively.

[0187] Specifically, the first gate driving unit may be the third circuit, and accordingly, Fig.24 The third output terminal OUT3 in the circuit can be the output terminal Pout1 of the first gate driving unit, and correspondingly, the third input terminal IN3 can be the first start signal line STV1 or the third output terminal of the third circuit of another level, and the connection relationship of the clock signal line connected to the first gate driving unit can be determined according to the first type of clock signal line XCK and the second type of clock signal line YCK. For example, the first gate driving unit is a third type of circuit, and the first type of gate driving unit is connected to the first group of clock signal lines CK1 (i.e., the first clock signal line CKa and the second clock signal line CKb) as an example, then in two adjacent levels of the third circuit, in one level of the third circuit, the point where the first type of clock signal line XCK is located is connected to the first clock signal line CKa, and the second type of clock signal line YCK is connected to the second clock signal line CKb, and in another level of the third circuit, the point where the first type of clock signal line XCK is located is connected to the second clock signal line CKb, and the second type of clock signal line YCK is connected to the first clock signal line CKa.

[0188] Specifically, in the first circuit, the second circuit and the third circuit, the transistors are all P-type transistors for illustration, but the embodiments of the present application are not limited to this. All transistors can be N-type transistors, or some can be P-type transistors and some can be N-type transistors.

[0189] Specifically, in the first circuit, the second circuit and the third circuit, each transistor can be a silicon semiconductor transistor (for example, a low-temperature polycrystalline silicon thin film transistor) to reduce power consumption, but the embodiments of the present application are not limited to this. Each transistor can be an oxide semiconductor transistor (for example, an indium gallium zinc oxide thin film transistor), or some transistors can be silicon semiconductor transistors (for example, low-temperature polycrystalline silicon thin film transistors) and some transistors can be oxide semiconductor transistors (for example, indium gallium zinc oxide thin film transistors).

[0190] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0191] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0192] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0193] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0194] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: A display area, wherein a plurality of pixel driving circuits are disposed in the display area, and each of the pixel driving circuits includes a plurality of transistors; A non-display area, comprising two gate drive circuit arrangement areas arranged on both sides of the display area along a first direction, each of the gate drive circuit arrangement areas being provided with a group of gate drive circuits, each group of the gate drive circuits comprising a first type of gate drive unit, a second type of gate drive unit, a third type of gate drive unit, a fourth type of gate drive unit and a fifth type of gate drive unit, the first type of gate drive unit, the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit being respectively connected to the gates of different transistors in the pixel drive circuit; Wherein, in one of the gate drive circuit arrangement areas, the display panel further comprises at least two groups of clock signal lines, and the first type of gate drive unit is connected to one group of the clock signal lines; At least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and at least two of the second type of gate driving unit, the third type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to another group of the clock signal lines, and an angle between the first direction and the second direction is greater than 0 and less than or equal to 90 degrees.

2. The display panel according to claim 1, characterized in that: In a gate driving circuit setting area, the second type of gate driving unit and the third type of gate driving unit are arranged along the second direction, the display panel includes four groups of clock signal lines, the first type of gate driving unit is connected to one group of the clock signal lines, the second type of gate driving unit and the third type of gate driving unit are connected to one group of the clock signal lines, the fourth type of gate driving unit is connected to one group of the clock signal lines, and the fifth type of gate driving unit is connected to one group of the clock signal lines, and the clock signal lines connected to the first type of gate driving unit, the second type of gate driving unit, the fourth type of gate driving unit and the fifth type of gate driving unit are different from each other.

3. The display panel according to claim 1, characterized in that: In a gate driving circuit setting area, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, the display panel includes four groups of clock signal lines, the first type of gate driving unit is connected to one group of the clock signal lines, the second type of gate driving unit is connected to one group of the clock signal lines, the third type of gate driving unit is connected to one group of the clock signal lines, the fourth type of gate driving unit and the fifth type of gate driving unit are connected to one group of the clock signal lines, and the clock signal lines connected to the first type of gate driving unit, the second type of gate driving unit, the third type of gate driving unit and the fourth type of gate driving unit are different from each other.

4. The display panel according to claim 1, characterized in that: In a gate driving circuit arrangement area, the second type of gate driving unit and the third type of gate driving unit are arranged along the second direction, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and the second type of gate driving unit and the fourth type of gate driving unit are arranged along the first direction, and the display panel includes three groups of clock signal lines, and the three groups of clock signal lines include a first group of clock signal lines, a second group of clock signal lines, and a third group of clock signal lines; Among them, the first type of gate driving unit is connected to the first group of clock signal lines, the second type of gate driving unit and the third type of gate driving unit are connected to the second group of clock signal lines, and the fourth type of gate driving unit and the fifth type of gate driving unit are connected to the third group of clock signal lines.

5. The display panel according to claim 4, characterized in that: In the first direction, the second group of clock signal lines is located between the second type gate driving unit and the fourth type gate driving unit, and the third group of clock signal lines is located on a side of the fourth type gate driving unit away from the second type gate driving unit.

6. The display panel according to claim 1, characterized in that: In a gate driving circuit arrangement area, the second type of gate driving unit and the third type of gate driving unit are arranged along the second direction, the fourth type of gate driving unit and the fifth type of gate driving unit are arranged along the second direction, and the second type of gate driving unit and the fourth type of gate driving unit are arranged along the first direction, and the display panel includes three groups of clock signal lines, and the three groups of clock signal lines include a first group of clock signal lines, a second group of clock signal lines, and a third group of clock signal lines; Among them, the first type of gate driving unit is connected to the first group of clock signal lines, the third type of gate driving unit and the fifth type of gate driving unit are connected to the second group of clock signal lines, and the second type of gate driving unit and the fourth type of gate driving unit are connected to the third group of clock signal lines.

7. The display panel according to claim 6, characterized in that: In the first direction, the second group of clock signal lines is located between the second type of gate driving unit and the fourth type of gate driving unit, and the third group of clock signal lines is located between the second type of gate driving unit and the fourth type of gate driving unit.

8. The display panel according to claim 1, characterized in that: In a gate drive circuit setting area, the display panel includes two groups of clock signal lines, the first type of gate drive unit is connected to one group of the clock signal lines, and the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to another group of the clock signal lines.

9. The display panel according to claim 8, characterized in that: In the second direction, the second type of gate driving unit and the third type of gate driving unit are arranged in sequence, and the fourth type of gate driving unit and the fifth type of gate driving unit are arranged in sequence. In the first direction, the second type of gate driving unit, a group of clock signal lines connected to the second type of gate driving unit, and the fourth type of gate driving unit are arranged in sequence.

10. The display panel according to claim 1, characterized in that: In a gate drive circuit setting area, three of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are arranged along the second direction, and three of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to another group of the clock signal lines.

11. The display panel according to claim 1, characterized in that: In a gate drive circuit setting area, the second type of gate drive unit and the third type of gate drive unit are connected to the same group of clock signal lines, the second type of gate drive unit includes a plurality of second gate drive units, and the third type of gate drive unit includes a plurality of third gate drive units, and along the second direction, the plurality of second gate drive units and the plurality of third gate drive units are alternately arranged.

12. The display panel according to claim 1, characterized in that: In a gate drive circuit setting area, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to the same group of clock signal lines, the fourth type of gate drive unit includes a multi-level fourth gate drive unit, and the fifth type of gate drive unit includes a multi-level fifth gate drive unit, and along the second direction, the multi-level fourth gate drive unit and the multi-level fifth gate drive unit are alternately arranged.

13. The display panel according to any one of claims 1 to 12, characterized in that: In a gate drive circuit setting area, the display panel also includes multiple groups of high-potential signal lines, and at least two of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to the same group of high-potential signal lines.

14. The display panel according to any one of claims 1 to 12, characterized in that: In a gate drive circuit setting area, the display panel also includes multiple groups of low-potential signal lines, and at least two of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to the same group of low-potential signal lines.

15. The display panel according to any one of claims 1 to 12, characterized in that: In a gate drive circuit setting area, the display panel also includes at least one group of control signal lines, and at least two of the second type of gate drive unit, the third type of gate drive unit, the fourth type of gate drive unit and the fifth type of gate drive unit are connected to the same group of control signal lines.

16. The display panel according to any one of claims 1 to 12, characterized in that: The pixel driving circuit includes a driving transistor, a switching transistor, a compensation transistor, a first light emitting transistor, a first initialization transistor and a second initialization transistor, wherein an electrode of the driving transistor, an electrode of the switching transistor and an electrode of the first light emitting transistor are connected to a first node, an electrode of the compensation transistor, a gate of the driving transistor and an electrode of the first initialization transistor are connected to a second node, and another electrode of the compensation transistor, another electrode of the driving transistor and an electrode of the second initialization transistor are connected to a third node; The output end of the first type of gate driving unit is connected to the gate of the switching transistor, the output end of the second type of gate driving unit is connected to the gate of the compensation transistor, the output end of the third type of gate driving unit is connected to the gate of the first initialization transistor, the output end of the fourth type of gate driving unit is connected to the gate of the second initialization transistor, and the output end of the fifth type of gate driving unit is connected to the gate of the first light-emitting transistor.

17. The display panel according to claim 16, characterized in that: The second type of gate driving unit includes multiple stages of second gate driving units, wherein the output end of one stage of the second gate driving unit is connected to the gates of the compensation transistors of the pixel driving circuits in two adjacent rows; or the output end of one stage of the second gate driving unit is connected to the gates of the compensation transistors of one row of the pixel driving circuits; And / or, the third type of gate driving unit includes multiple stages of third gate driving units, and the output end of the third gate driving unit of one stage is connected to the gates of the first initialization transistors of the pixel driving circuits of two adjacent rows; or the output end of the third gate driving unit of one stage is connected to the gate of the first initialization transistor of the pixel driving circuit of one row; And / or, the fourth type of gate driving unit includes multiple stages of fourth gate driving units, and the output end of the fourth gate driving unit of one stage is connected to the gates of the second initialization transistors of the pixel driving circuits of two adjacent rows; or the output end of the fourth gate driving unit of one stage is connected to the gate of the second initialization transistor of the pixel driving circuit of one row; And / or, the fifth type of gate driving unit includes multiple levels of fifth gate driving units, and the output end of the fifth gate driving unit at one level is connected to the gates of the first light-emitting transistors of the pixel driving circuits in two adjacent rows; or the output end of the fifth gate driving unit at one level is connected to the gates of the first light-emitting transistors of the pixel driving circuits in one row.

18. A display device, characterized in that: Comprising the display panel as described in any one of claims 1 to 17.

Images