Memory element and protection method thereof

Abstract

The invention provides a memory element and a protection method thereof. The memory element includes a memory cell array including a plurality of word lines; a controller configured to update at least one of the plurality of word lines during a first update period in response to an update signal; a random number generator configured to generate a first number; a counter electrically coupled to the random number generator and configured to receive the first number as an initial value of the counter, where the counter is configured to be turned on in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line that is valid when the counter decreases to zero. The controller is configured to access the address register during a second update period to obtain the address of the first wordline and protect a second wordline, wherein an address of the second wordline is adjacent to the address of the first wordline. The controller is configured to update a third word line during the second update period, wherein an address of the third word line is separated from an address of the first word line.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2023117045600, filed on December 12, 2023, with the invention name of “Memory Element and Protection Method Thereof”. Application No. 2023117045600 claims priority and benefits of U.S. formal application No. 18 / 367,602 filed on September 13, 2023. The contents of the U.S. formal application are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a memory element and a protection method thereof, and more particularly to a memory element including a protection circuit for protecting a word line. Background Art

[0003] Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor. The simplest DRAM cell contains a transistor and a capacitor. If charge is stored in the capacitor, the cell is said to store a logical high according to the convention used. If no charge is present, the cell is said to store a logical low. Since the charge in the capacitor is consumed over time, DRAM systems require additional refresh circuits to periodically refresh the charge stored in the capacitor. Since capacitors can only store a very limited amount of charge, in order to quickly distinguish the difference between logical 1 and logical 0, two bit lines (BL) are usually used for each bit, where the first bit in the bit line pair is called bit line true (BLT) and the other is bit line complement (BLC).

[0004] Row hammer is an unexpected and unwelcome side effect in DRAM that poses a security concern. Row hammering occurs when memory cells interact electrically through charge leakage, potentially changing the contents of nearby memory columns (word lines) that were not addressed in the original memory access. Column hammering can be initiated by a specific memory access pattern that rapidly activates the same memory column (word line) multiple times. As a result, memory cells connected to adjacent word lines may experience charge leakage and may have difficulty retaining the original content until the next periodic update cycle. A malicious operator can exploit the column hammering effect to change the contents of nearby memory rows, causing device failure. Therefore, there is a need to develop a device to protect memory (especially word lines) to mitigate the described problems.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] An embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array including a plurality of word lines; a controller configured to update at least one of the plurality of word lines in response to an update signal during a first update cycle; a random number generator configured to generate a first number; a counter electrically coupled to the random number generator and configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line that is valid when the counter is decremented to zero. The controller is configured to access the address register during a second update cycle to obtain the address of the first word line and protect a second word line, wherein an address of the second word line is adjacent to the address of the first word line.

[0007] Another embodiment of the present disclosure provides a memory element. The memory element includes a plurality of word lines; a controller configured to update one of the plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; and a counter configured to receive the first number as an initial value of the counter and start counting from the initial value in response to the update signal. The counting of the counter is triggered by an access signal indicating an access to one of the plurality of word lines. The controller is configured to obtain an address of a first word line accessed when the counter reaches zero, and to update a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line. The controller is configured to update a third word line during the second update cycle, wherein an address of the third word line is separate from an address of the first word line.

[0008] Another embodiment of the present disclosure provides a protection method for a memory element. The protection method, wherein the memory element includes a plurality of word lines. The protection method includes updating a first word line among the plurality of word lines during a first update cycle in response to an update signal; generating a first number by a random number generator; starting to count down from the first number by the counter in response to the update signal; obtaining an address of a second word line accessed when the counter counts down to zero by a controller; and protecting the third word line during a second update cycle by updating the third word line in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0009] Embodiments of the present disclosure provide a memory element having a protection circuit for selecting and protecting a vulnerable word line. Specifically, the protection circuit of the memory element can protect the word line (memory cell) from column hammering. Column hammering is initiated by quickly starting the same memory column so that adjacent unactivated memory columns may leak charge. The present protection circuit provides a random number generator and a counter to randomly select and protect vulnerable memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter reaches zero, an address of the activated memory column can be obtained. In other words, the memory column is selected from the memory columns activated between update cycles. In this case, the selection pool includes the memory columns activated between update cycles. Since the memory columns adjacent to the activated memory columns are more likely to suffer from the column hammering effect, they are protected in subsequent update cycles.

[0010] Typically, the level of activation required to trigger column hammering cannot be accomplished within two update cycles. For example, a memory device with 8192 columns may experience approximately 170 activations between update cycles, while the number of activations required to initiate column hammering on the same column may be 10,000 or more. Therefore, in each update cycle, additional memory columns susceptible to column hammering effects are protected from damage, thereby enhancing the safety and performance of the memory device.

[0011] The above has outlined the technical features and advantages of the present disclosure in a fairly broad manner, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more complete understanding of the present disclosure may be obtained by referring to the detailed description and claims.The present disclosure should also be understood to be associated with the element numbers of the drawings, which represent similar elements throughout the description.

[0013] Figure 1 is a schematic structural diagram illustrating memory elements of some embodiments of the present disclosure.

[0014] Figure 2 is a schematic structural diagram illustrating memory elements of some embodiments of the present disclosure.

[0015] Figure 3 is a structural diagram illustrating the activation of word lines between update cycles along a timeline in some embodiments of the present disclosure.

[0016] Figure 3A is a structural diagram illustrating the word line address accessed at each start-up between update cycles along a timeline according to some embodiments of the present disclosure.

[0017] Figure 3B is a structural diagram illustrating the word line address accessed at each start-up between update cycles along the timeline of some embodiments of the present disclosure.

[0018] Figure 3C is a structural diagram illustrating the word line address accessed at each start-up between update cycles along a timeline according to some embodiments of the present disclosure.

[0019] Figure 4 is a structural diagram illustrating a shift register included in a memory element in some embodiments of the present disclosure.

[0020] Figure 5 is a flowchart illustrating a method for protecting a memory element according to some embodiments of the present disclosure.

[0021] The reference numerals are described as follows:

[0022] 1: Memory components

[0023] 2: Memory components

[0024] 5: Protection method

[0025] 11: Memory cell array

[0026] 12: Sense Amplifier

[0027] 21: Memory cell array

[0028] 22: Controller

[0029] 23: Random number generator

[0030] 24: Counter

[0031] 25: Address register

[0032] 51~55: Steps

[0033] 111~114: Memory column

[0034] 131: Column address decoder

[0035] 132: Row address decoder

[0036] 211: Character line

[0037] 212: Character line

[0038] 213: Character line

[0039] 214: Character line

[0040] 231: Logic Gate

[0041] 232: Logic Gate

[0042] 233: Shift register

[0043] 234: The first number

[0044] 2330, 2331, 2332, 2333, 2334, 2335, 2336, 2337: Triggers

[0045] act_1, act_2, act_3, act_4, act_N-1, act_N: start

[0046] B0~B7: Output terminals

[0047] Bit0~Bit7:Bit value

[0048] CAS: Row Address Strobe

[0049] CBR: First update cycle

[0050] CBR+1: Second update cycle

[0051] CLKA: first clock signal

[0052] CLKB: Second clock signal

[0053] CLKC: The third clock signal

[0054] CLKD: fourth clock signal

[0055] CLKE: fifth clock signal

[0056] D0~D7: Data terminals

[0057] RAS: Column Address Strobe

[0058] RS: Update signal

[0059] R / W: Read / write signal

[0060] T act : Time period

[0061] T CBR : Time period

[0062] WL1: word line address

[0063] WL2: word line address

[0064] WL3: word line address DETAILED DESCRIPTION

[0065] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0066] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the progressive conception of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0067] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the above.

[0068] It should be understood that in the description of the present disclosure, the term "about" is used to change the quantity of the ingredients, components or reactants of the present disclosure, meaning, for example, the quantitative changes that may occur by typical measurements and liquid handling procedures used to prepare concentrates or solutions. Furthermore, inadvertent errors in measurement procedures, differences in the manufacture, source or purity of the ingredients used to make the composition or implement the method, etc. may cause changes. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. Furthermore, in another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2 or 1% of the reported value.

[0069] Figure 1 1 is a schematic structural diagram illustrating a memory element 1 according to some embodiments of the present disclosure. The memory element 1 may include a memory cell array 11, a plurality of sense amplifiers 12, a column address decoder 131 and a row address decoder 132. In some embodiments, the memory element 1 may be a DRAM.

[0070] Please refer to Figure 1 , the memory cell array 11 may include a plurality of rows and columns. Each row of memory cells may share a bit line or a pair of bit lines. Each column of memory cells may share a word line. In some embodiments, a single memory cell may include a capacitor and a transistor and be configured to store a bit of data therein. The charge state (charged or discharged) of the capacitor may determine whether the memory cell stores "1" or "0" as a binary value.

[0071] In some embodiments, the storage address applied to a matrix memory cell array 11 can be expressed as a column address and a row address, which are processed by a column address decoder 131 and a row address decoder 132. When the column address decoder 131 selects a particular column (e.g., memory column 114) for a read operation (this selection is also referred to as column activation), bits from all memory cells in the particular column can be transferred to the sense amplifier 12. In some embodiments, one sense amplifier 12 is dedicated to each row of memory cells to temporarily hold data. In some embodiments, the row address decoder 132 can select the exact bit from the sense amplifier 12. In some embodiments, the sense amplifier 12 can be configured to receive or send data in response to a read / write signal R / W. A write operation decodes the address in a similar manner, but an entire column can be rewritten to change the value of a single bit.

[0072] Since data bits are stored in capacitors with a natural discharge rate, the state stored in the memory cell array 11 may be lost over time, so all memory cells need to be rewritten (charged) periodically to save information, a process called updating. Each memory update cycle can update one or more columns of memory cells, and all memory cells can be repeatedly updated in consecutive cycles. This memory update can be accomplished in a variety of ways. In some embodiments, memory updates can be performed using signals of different modes, such as column address select (RAS) updates, row address select before column address select (CAS-before-RAS) updates (also known as CBR updates for short), and hidden updates.

[0073] To trigger the column hammering effect, the same memory column 111 is repeatedly activated at a high frequency. When the activation frequency and number of memory columns 111 are sufficient, the adjacent unactivated memory columns 112 and 113 may leak charges, so that the data / content stored therein may be lost.

[0074] The protection circuit provides a random number generator and a counter (for detailed description, please refer to Figure 2 ) to randomly select and protect a vulnerable memory column. The counter can be configured to count down from the random number generated by the random number generator. When the counter is reduced to zero, the address of the activated memory column (e.g., memory column 111) can be obtained. In other words, the memory column is selected from the memory columns activated between the update cycles. The memory columns 112 and 113 adjacent to the activated memory column 111 are more susceptible to the column hammering effect, so they are protected in the subsequent update cycle. In some embodiments, the vulnerable memory columns 112 and 113 and the planned update memory column 114 can be updated in the subsequent update cycle.

[0075] Figure 2 is a structural diagram illustrating a memory element 2 of some embodiments of the present disclosure. Figure 2 , the memory element 2 may include a memory cell array 21, a controller 22, a random number generator 23, a counter 24, and an address register 25. In some embodiments, the memory element 2 may be a dynamic random access memory (DRAM). In some embodiments, the random number generator 23, the counter 24, and the address register 25 may be included in a protection circuit of the memory element 2.

[0076] In some embodiments, the memory cell array 21 may include a plurality of word lines. In some embodiments, the memory cell array 21 may include a target word line 211 to be accessed, two vulnerable adjacent word lines 212 and 213 close to the target word line 211, and a normal word line 214. The normal word line 214 may be located at any position in the array 21. For example, the normal word line 214 may be an edge word line or located between two other word lines. In one embodiment, the normal word line 214 may be separated from the target word line 211, and in another embodiment, the normal word line 214 is adjacent to the target word line 211 (not shown).

[0077] The controller 22 may be configured to update at least one word line during a first update cycle in response to an update signal RS. In some embodiments, the update signal RS may be a RAS update command or a CBR update command. The controller 22 may be configured to update one or more word lines during an update cycle. In some embodiments, the controller 22 may be configured to update one, two, three, four or more word lines simultaneously. In some embodiments, the controller 22 may be configured to update the entire memory cell array 21 cycle by cycle.

[0078] The random number generator 23 may be configured to generate a first number 234. The first number 234 may be a positive integer. In some embodiments, the first number 234 may be binary. The first number 234 may be greater than 2 bits. For example, the first number 234 may be 8 bits. That is, the first number 234 may be in the range of 0 to 256.

[0079] Please refer to Figure 2 , the random number generator may include logic gates 231 and 232 and a shift register 233 .

[0080] In some embodiments, the logic gate 231 may have a first input terminal, a second input terminal, and an output terminal. In some embodiments, the logic gate 231 may be configured to receive a first clock signal CLKA and a second clock signal CLKB through the first input terminal and the second input terminal. In some embodiments, the frequency of the first clock signal CLKA is different from the frequency of the second clock signal CLKB. The logic gate 231 may be configured to generate a third clock signal CLKC in response to the first clock signal CLKA and the second clock signal CLKB. In some embodiments, the logic gate 231 may output the third clock signal CLKC via the output terminal of the logic gate 231.

[0081] The logic gate 231 may be an OR, AND, XOR, XNOR or other gate types. In another embodiment, the logic gates 231 and 232 may be other types of logic gates (not shown).

[0082] In some embodiments, the third clock signal CLKC may be unpredictable compared to the first clock signal CLKA and the second clock signal CLKB because it is based on a predetermined calculation in response to the first clock signal CLKA and the second clock signal CLKB. For example, if the logic gate 231 is an XOR gate, then in principle, the output of the two-input XOR is true only when the two input values ​​are different, and if they are equal, the output is false regardless of the input values. Based on such calculation of the XOR gate, the third clock signal CLKC may have an uneven frequency.

[0083] In some embodiments, the logic gate 232 may have a first input terminal, a second input terminal, and an output terminal electrically connected to the logic gate 231. The second input terminal and the output terminal of the logic gate 232 are both electrically connected to the shift register 233. The logic gate 232 may be configured to receive the third clock signal CLKC via the first input terminal of the logic gate 232. In some embodiments, the second input terminal of the logic gate 232 may be configured to receive a bit value associated with the first number 234 output from the shift register 233. The logic gate 232 may be configured to generate a fourth clock signal CLKD in response to the third clock signal CLKC and the bit value associated with the first number 234. In some embodiments, the logic gate 232 may output the fourth clock signal CLKD via the output terminal of the logic gate 232.

[0084] The logic gate 232 may be an OR, AND, XOR, XNOR, or other gate types. In some embodiments, the logic gates 231 and 232 may be the same or different types. For example, the logic gates 231 and 232 may both be XOR gates. In another embodiment, the logic gates 231 and 232 may be other types of logic gates (not shown).

[0085] In some embodiments, by passing the bit value associated with the first number 234 back to the logic gate 232 , the fourth clock signal CLKD can be less predictable than the third clock signal CLKC.

[0086] The shift register 233 may include a first input terminal electrically connected to the output terminal of the logic gate 232, a second input terminal configured to receive a fifth clock signal CLKE, and an output terminal connected to the counter 24. In some embodiments, the shift register 233 is an 8-bit register. Therefore, the output terminal of the shift register 233 may have 8 bits (such as Figure 2In other embodiments, the shift register 233 may have more or less than 8 bits.

[0087] In some embodiments, the first input terminal of the shift register 233 may be configured to receive the fourth clock signal CLKD. In some embodiments, the first input terminal of the shift register 233 may be a data terminal. In some embodiments, the second input terminal of the shift register 233 may be a clock terminal.

[0088] The shift register 233 may be configured to generate the first number 234 in response to the fourth clock signal CLKD and the fifth clock signal CLKE. In some embodiments, the output terminal of the shift register 233 may be configured to output the first number 234 in response to the fourth clock signal CLKD.

[0089] The output terminal of the shift register 233 may be connected to the second input terminal of the logic gate 232, so that the bit value associated with the first number 234 is fed back to the logic gate 232. For example, 3 bits of the output terminal of the shift register 233 may be connected to the second input terminal of the logic gate 232. In some embodiments, the logic gate 232 may be configured to generate a fourth clock signal CLKD in response to the third clock signal CLKC and the bit value (e.g., the bit value outputted in 3 bits). The fourth clock signal CLKD may be associated with the current number outputted from the shift register 233.

[0090] The shift register 233 may be configured to generate a random number (i.e., the first number 234) in response to the fourth clock signal CLKD as a data input and the fifth clock signal CLKE as a clock input. By feeding back the bit value associated with the first number 234 to the logic gate 232, the random number generator 23 may be non-pseudo. Therefore, the first number 234 may be more difficult to predict. Therefore, the security of the memory element 2 may be improved.

[0091] The counter 24 may be electrically coupled to the random number generator 23. The counter 24 may be configured to receive the first number 234 as an initial value of the counter 24. In some embodiments, the counter 24 is configured to be turned on in response to an update signal RS received from the controller 22. In other words, the counter 24 may be configured to start counting down in response to the update signal RS. The counter 24 may be configured to count down (count down) from the initial value (i.e., the first number 234).

[0092] In some embodiments, counter 24 may be configured to decrement in response to an access signal, thereby providing notification of an access to one of the plurality of word lines.

[0093] The address register 25 may be electrically coupled to the counter 24. The address register 25 may be configured to obtain the address of a first word line 211 (or target word line 211) activated when the counter 24 is decremented to zero, and store the address.

[0094] The controller 22 may be configured to access the address register 25 during a second update cycle to obtain the address of the first word line and protect the second word line 212 / 213 (i.e., the adjacent word line 212 or 213). To protect the second word line 212 / 213, the controller may be configured to update the second word line 212 / 213 during the second update cycle in response to the update signal. In some embodiments, the second update cycle is after the first update cycle. For example, the second update cycle is the next update cycle of the first update cycle. In some embodiments, the address of the second word line 212 / 213 is adjacent to the address of the first word line 211.

[0095] The controller 22 may be configured to update one or more word lines during one update cycle. In some embodiments, the controller 22 may be configured to update one, two, three, four or more word lines simultaneously. The controller 22 may be configured to update adjacent word lines 212 and 213 during the same update cycle. In some embodiments, in addition to the second word lines 212 / 213, the controller 22 may also be configured to update a third word line 214 during the second update cycle in response to the update signal RS, wherein the address of the third word line 214 is separate from the address of the first word line 211.

[0096] In some embodiments, the controller 22 may be configured to update one word line adjacent to the target word line 211 and another word line separated from the target word line 211. For example, the word line 212 and the word line 214 may be updated during the second update cycle. In some embodiments, in one update cycle, the controller 22 may be configured to update two normal word lines (e.g., the word line 214) and two high-risk word lines (e.g., the vulnerable word lines 212 and 213), which are determined by the random number generator 23 and the counter 24.

[0097] In the present disclosure, the address of the valid first word line 211 (or target word line 211) can be obtained when the counter 24 is decremented to zero. In this case, the address of the word line to be protected can be randomly selected from those word lines activated between two update cycles.

[0098] Figure 3 is a structural diagram illustrating the activation of word lines between update cycles along a timeline in some embodiments of the present disclosure.

[0099] Please refer to Figure 3, along the timeline (i.e., x-axis), a time period T CBR is located between a first update period CBR and a second update period CBR+1. In some embodiments, the second update period CBR+1 is immediately followed by the first update period CBR. In some embodiments, N activations (act_1, act_2, act_3, ..., act_N-1, act_N) occur between the first update period CBR and the second update period CBR+1. Each activation act_1, act_2, act_3, act_N-1 and act_N represents an access to the word line. For example, the time period T act In some embodiments, the time period T act It may be the minimum necessary time to access a word line (eg, the first activation act_1).

[0100] For the purpose of clarifying the present disclosure, a memory array with 8k word lines is used as an example. The memory array may include 8192 word lines. In some embodiments, the time to update all word lines (i.e., 8192 word lines) may be 64 ms. In this case, the time period T CBR , that is, the time required to update each word line, can be calculated as 64ms / 8192, so the time period T CBR In other words, for a total of 8k word lines, the time period T shared by the two update cycles is CBR It can be 7.8125μs. Assume that the time period T act is 45.75ns, then the maximum number of accesses between two update cycles is N max According to the formula Therefore, the maximum number of access times Nmax can be 7.8125μs / 45.75ns=170.765≈170, making Figure 3 The N in is 170. In this embodiment, 170 word lines can be accessed between two update cycles. Accordingly, the first number 234 received by the counter 24 can be adjusted to be smaller than a predetermined number (eg, 170 in this embodiment).

[0101] In some embodiments, the first number 234 may be smaller than a predetermined number that is related to the time period T for accessing the word line. act and the time period T between the first update period CBR and the second update period CBR+1 CBRIn some embodiments, the counter 24 may be configured to reset the initial value when the first number 234 is greater than a predetermined number. For example, the initial value of the counter 24 may be reset by resetting to zero or by subtracting a constant less than a predetermined number. Thus, the counter 24 may start counting down from an initial value within a range of 0 to a predetermined number (i.e., the maximum number of accesses between two update cycles), and when decremented to zero, a word line may be selected to be protected during the next update cycle.

[0102] Figure 3A 2 is a schematic structural diagram illustrating the word line address accessed at each start-up between update periods CBR and CBR+1 along the timeline of some embodiments of the present disclosure.

[0103] Please refer to Figure 3A , accessing the word line address WL1 each time act_1, act_2, act_3, act_4, ... and act_N are started. In this case, regardless of the initial value of the counter 24, the address register 25 stores the word line address WL1 which is accessed the most times. In other words, the word line address WL1 may be the most likely target of attack. Therefore, selecting a word line adjacent to the word line address WL1 to be protected can effectively prevent the column hammering effect.

[0104] Figure 3B 2 is a structural diagram illustrating a word line address accessed at each start-up between update periods CBR and CBR+1 along a timeline according to some embodiments of the present disclosure.

[0105] Please refer to Figure 3B , word line address WL1 is accessed at start act_1. Word line address WL2 is accessed at start act_2. Word line address WL1 is accessed at start act_3. Word line address WL2 is accessed at start act_4. Word line address WL2 is accessed at start act_N. That is, only word line addresses WL1 and WL2 are accessed. In this case, regardless of the initial value of counter 24, address register 25 stores word line address WL1 or WL2 with the most access times. In some embodiments, the probability of word line addresses WL1 and WL2 being targets is 50%. In other words, word line addresses WL1 and WL2 may be the most likely targets of attack. Therefore, selecting word lines adjacent to word line address WL1 or WL2 for protection can effectively prevent column hammering effect.

[0106] Figure 3C 2 is a schematic structural diagram illustrating the word line address accessed at each start-up between update periods CBR and CBR+1 along the timeline of some embodiments of the present disclosure.

[0107] Please refer to Figure 3C, word line address WL1 is accessed at start act_1. Word line address WL2 is accessed at start act_2. Word line address WL3 is accessed at start act_3. Word line address WL1 is accessed at start act_4. Word line address WL2 is accessed at start act_N-1. Word line address WL3 is accessed at start act_N. In some embodiments, word line addresses WL1, WL2, and WL3 are repeatedly accessed in sequence. That is, only word line addresses WL1, WL2, and WL3 are accessed between update cycles. In this case, address register 25 stores one of word line addresses WL1, WL2, and WL3. In some embodiments, the vulnerability of word line addresses WL1, WL2, and WL3 may be approximately 33.33% (i.e., one third). In other words, word line addresses WL1, WL2, and WL3 may be the most likely targets of attack. Therefore, the column hammering effect can be effectively prevented by selecting the word line adjacent to the word line address WL1, WL2 or WL3 for protection.

[0108] Figure 4 is a structural diagram illustrating a shift register 233 included in a memory element in some embodiments of the present disclosure.

[0109] Please refer to Figure 4 , the shift register 233 may include one or more flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 may be any type of flip-flops, such as D flip-flops. In some embodiments, the 8-bit shift register 233 may include eight flip-flops 2330, 2331, ..., 2335, 2336, and 2337. In some embodiments, the shift register 233 may be a serial input parallel output configuration.

[0110] Each of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 may have a data terminal, a clock terminal, a reset terminal, and an output terminal. In some embodiments, the clock terminals of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 are connected and configured to receive a clock signal CLKE (e.g., Figure 2. As shown). That is, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can operate at a given clock frequency of the clock signal CLKE. The reset terminals of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 are connected and configured to receive a reset signal. In some embodiments, the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can be reset in response to the reset signal. In some embodiments, each of the flip-flops 2330, 2331, ..., 2335, 2336, and 2337 can have a set terminal (not shown).

[0111] In some embodiments, the data terminal D7 of the flip-flop 2337 can be configured to receive a clock signal CLKD (eg, Figure 2 In response to the clock signals CLKD and CLKE, the output terminal B7 of the flip-flop 2337 can be configured to output a bit value Bit7 to be transmitted to the counter 24 and the data terminal D6 of the flip-flop 2336. In response to the bit value Bit7 and the clock signal CLKE, the output terminal B6 of the flip-flop 2336 can be configured to output a bit value Bit6 to be transmitted to the counter 24 and the data terminal D5 of the flip-flop 2335. In response to the bit value Bit6 and the clock signal CLKE, the output terminal B5 of the flip-flop 2335 can be configured to output a bit value Bit5 to be transmitted to the counter 24 and the data terminal D4 (not shown) of the flip-flop 2334. In some embodiments, the omitted flip-flops 2334, 2333, and 2332 can be set between the flip-flops 2335 and 2331 in a manner similar to the flip-flops 2336 and 2335. In response to the bit value Bit2 and the clock signal CLKE received at the data terminal D1 of the flip-flop 2331, the output terminal B1 of the flip-flop 2331 can be configured to output a bit value Bit1 to be transmitted to the counter 24 and the data terminal D0 of the flip-flop 2330. In response to the bit value Bit1 and the clock signal CLKE, the output terminal B0 of the flip-flop 2330 can be configured to output a bit value Bit0 to be transmitted to the counter 24.

[0112] The data input of the shift register 233 is serial. Once the data is input, it can be read out at each output terminal at the same time, or it can be shifted out. Each input bit reaches the Nth output after N clock cycles, thereby forming a parallel output. The bit values ​​Bit7, Bit6, Bit5, ..., Bit1 and Bit0 can form a first number 234 in 8-bit form. Please refer back to Figure 2, the output terminal of the shift register 233 can be connected to the second input terminal of the logic gate 232, so that the bit value associated with the first number 234 is fed back to the logic gate 232. In some embodiments, the fed-back bit value can be Figure 4 The bit value shown is one of Bit7, Bit6, Bit5, ..., Bit1 and Bit0.

[0113] The shift register 233 may be configured to generate a random number (e.g., the first number 234) in response to the data signal (i.e., the clock signal CLKD) and the clock signal CLKE. The unpredictable clock signal CLKC is generated based on the asynchronous clock signals CLKA and CLKB through the logic gate 231. In addition, the clock signal CLKD may be more unpredictable because it is generated based on the unpredictable clock signal CLKC and the feedback bit value associated with the first number 234. In this case, the clock signal CLKD may be more difficult to predict. In the absence of any pseudo-algorithm, the random number generator 23 may be configured to generate a more unpredictable number. Therefore, the protected word line address cannot be predicted or determined by a potential attacker.

[0114] Figure 5 is a flow chart illustrating a method for protecting a memory element in some embodiments of the present disclosure. In some embodiments, method 5 protects a word line included in a memory element. In some embodiments, the memory element may include multiple word lines.

[0115] In step 51, a first word line of the plurality of word lines may be updated during a first update cycle in response to an update signal. In some embodiments, a controller of the memory device may update one or more word lines in each update cycle in response to the update signal.

[0116] In step 52, a first number may be generated by a random number generator. In some embodiments, the random number generator may be configured to generate a random number based on different signals.

[0117] In step 53, the counter may be configured to start counting down from the first number in response to the update signal. In some embodiments, the counter may be configured to start counting in response to the update signal. The counter may start counting down from the first number. In some embodiments, each countdown may be triggered by an access signal indicating an access to a word line.

[0118] In step 54, an address of a second word line accessed when the counter counts down to zero can be obtained by the controller. In some embodiments, when the counter reaches zero, the address of the second word line can be obtained and stored in an address register. The controller can be configured to access the address register and obtain the address of the second word line.

[0119] In step 55, the third word line may be protected during a second update cycle by updating the third word line in response to the update signal, wherein an address of the third word line is adjacent to an address of the second word line.

[0120] The realization of column hammering effect often involves high-frequency access to one or more target word lines. A large number of access actions to the target word line will cause column hammering effect to appear on the word lines adjacent to the target word line. That is, under the column hammering effect, even if the nearby word line is not accessed, the content of the nearby word line will be affected by charge leakage.

[0121] The present disclosure provides a memory device that can determine whether a word line is susceptible to column hammering and protect word lines adjacent to the target word line accordingly. Word lines adjacent to the target word line that is subject to repeated access can therefore be updated to protect the contents therein.

[0122] An embodiment of the present disclosure provides a memory element. The memory element includes a memory cell array including a plurality of word lines; a controller configured to update at least one of the plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; a counter electrically coupled to the random number generator and configured to receive the first number as an initial value of the counter, wherein the counter is configured to be turned on in response to the update signal; and an address register electrically coupled to the counter and configured to store an address of a first word line that is valid when the counter is decremented to zero. The controller is configured to access the address register during a second update cycle to obtain the address of the first word line and protect a second word line, wherein an address of the second word line is adjacent to the address of the first word line. The controller is configured to update a third word line during the second update cycle, wherein an address of the third word line is separate from an address of the first word line.

[0123] Another embodiment of the present disclosure provides a protection method for a memory element. The protection method, wherein the memory element includes a plurality of word lines. The protection method includes updating a first word line among the plurality of word lines during a first update cycle in response to an update signal; generating a first number by a random number generator; starting to count down from the first number by the counter in response to the update signal; obtaining an address of a second word line accessed when the counter counts down to zero by a controller; and protecting the third word line during a second update cycle by updating the third word line in response to the update signal, wherein an address of the third word line is adjacent to the address of the second word line.

[0124] Embodiments of the present disclosure provide a memory element having a protection circuit for selecting and protecting a vulnerable word line. Specifically, the protection circuit of the memory element can protect the word line (memory cell) from column hammering. Column hammering is initiated by quickly starting the same memory column so that adjacent unactivated memory columns may leak charge. The present protection circuit provides a random number generator and a counter to randomly select and protect vulnerable memory columns. The counter can be configured to count down from a random number generated by the random number generator. When the counter reaches zero, an address of the activated memory column can be obtained. In other words, the memory column is selected from the memory columns activated between update cycles. In this case, the selection pool includes the memory columns activated between update cycles. Since the memory columns adjacent to the activated memory columns are more likely to suffer from the column hammering effect, they are protected in subsequent update cycles.

[0125] Typically, the level of activation required to trigger column hammering cannot be accomplished within two update cycles. For example, a memory device with 8192 columns may experience approximately 170 activations between update cycles, while the number of activations required to initiate column hammering on the same column may be 10,000 or more. Therefore, in each update cycle, additional memory columns susceptible to column hammering effects are protected from damage, thereby enhancing the safety and performance of the memory device.

[0126] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0127] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A memory element, comprising: Multiple character lines; a controller configured to update one of the plurality of word lines during a first update cycle in response to an update signal; a random number generator configured to generate a first number; a counter configured to receive the first number as an initial value of the counter and start counting from the initial value in response to the update signal, wherein counting of the counter is triggered by an access signal indicating an access to one of the plurality of word lines, wherein the controller is configured to obtain an address of a first word line accessed when the counter reaches zero and to update a second word line during a second update cycle, wherein an address of the second word line is adjacent to the address of the first word line, The controller is configured to update a third word line during the second update cycle, wherein an address of the third word line is separate from an address of the first word line.

2. The memory device as claimed in claim 1, wherein the first number is a positive integer.

3. The memory device of claim 2, wherein the first number is less than a first predetermined number, wherein the first predetermined number is associated with a first time period for accessing the plurality of word lines and a second time period between the first update cycle and the second update cycle. 4 . The memory device as claimed in claim 3 , wherein the counter is configured to reset the initial value when the first number is greater than the first predetermined number.

5. The memory device of claim 4, further comprising: An address register is connected to the counter, wherein the address register is used to obtain and store the address of the first word line that is valid when the counter is decremented to zero.

6. A method for protecting a memory element, wherein the memory element comprises a plurality of word lines, the method comprising: updating a first word line of the plurality of word lines during a first update cycle in response to an update signal; Generate a first number by a random number generator; In response to the update signal, a counter starts counting down from the first number; Obtaining, by a controller, an address of a second word line among the plurality of word lines accessed when the counter counts down to zero; A third word line of the plurality of word lines is protected during a second refresh cycle by updating the third word line in response to the refresh signal, wherein an address of the third word line is adjacent to the address of the second word line. 7 . The protection method of claim 6 , wherein the countdown of the counter is triggered by an access signal indicating an access to one of the plurality of word lines.

8. The protection method as claimed in claim 6, wherein the random number generator comprises: A shift register, comprising: a first input terminal; as well as an output terminal, used to output the first number; as well as a first logic gate configured to receive a first clock signal and a bit value related to the first number, the first logic gate being used to generate a second clock signal in response to the first clock signal and the bit value and transmit the second clock signal to the first input terminal of the shift register, The shift register is used to generate the first number in response to the second clock signal.

9. The protection method as claimed in claim 8, wherein the random number generator further comprises: A second logic gate is configured to receive a third clock signal and a fourth clock signal, and generate the first clock signal in response to the third clock signal and the fourth clock signal, wherein a frequency of the first clock signal is different from a frequency of the second clock signal.

10. The protection method as claimed in claim 8, wherein the first number is binary and is greater than 2 bits. The protection method as claimed in claim 8 , wherein the first logic gate is an XOR gate.

12. The protection method according to claim 6, further comprising: During the second update cycle, a fourth word line is updated in response to the update signal, wherein an address of the fourth word line is separate from the address of the second word line. 13 . The protection method of claim 12 , wherein refreshing the fourth word line comprises charging the first word line. The protection method as claimed in claim 6 , wherein the first number is a positive integer.

15. The protection method of claim 14, wherein the first number is less than a first predetermined number, wherein the first predetermined number is associated with a first time period for accessing a word line and a second time period between the first update cycle and the second update cycle.

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