A memory and optimization method thereof

Abstract

The present invention provides a memory and an optimization method thereof, wherein the memory comprises: a main control unit receiving different test instructions of a processor, parsing the test instructions, and generating corresponding control instructions; a flash memory unit, used to perform different operations according to the control instructions; a main control monitoring unit, used to record the delay duration of the main control unit in processing different test instructions; and a flash memory monitoring unit, used to record the delay duration of the flash memory unit when performing different operations; wherein the main control unit determines whether the sum of the delay durations is greater than a preset total duration; if greater, the firmware is optimized; otherwise, the firmware does not need to be optimized. Through the memory and the optimization method thereof provided by the present invention, the delay of the memory when performing various operations can be quickly tested for optimization.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a storage device and an optimization method thereof. Background Art

[0002] eMMC (embedded Multimedia Card) is a storage solution integrated into devices, widely used in smartphones, tablets, laptops and other embedded devices. As the performance and user experience requirements of devices increase, the read and write speed, stability and latency of eMMC have gradually become important indicators for measuring product quality. Especially in client applications, the performance of the memory directly affects the device's response speed, standby time and overall user experience.

[0003] As users have higher and higher requirements for device standby time and response speed, how to ensure the stable performance of eMMC storage in various application scenarios has become an important challenge facing storage manufacturers. Latency, as a key factor affecting user experience, reflects the response time of the storage when performing various operations. Minimizing latency is the key to improving user experience, so it is necessary to comprehensively test and evaluate the latency performance of eMMC in different scenarios. How to quickly test the latency of storage produced by different manufacturers when performing various operations for optimization is a problem that needs to be solved urgently. Summary of the invention

[0004] The object of the present invention is to provide a memory and an optimization method thereof, which can quickly test the delay of the memory when executing various operations for optimization.

[0005] To solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a memory, comprising:

[0007] A transmission interface unit, communicatively connected to the processor;

[0008] A main control unit receives different test instructions of the processor through the transmission interface unit, analyzes the test instructions, and generates corresponding control instructions;

[0009] A flash memory unit, used to perform different operations according to the control instructions;

[0010] a main control monitoring unit, communicatively connected between the transmission interface unit and the main control unit, wherein the main control monitoring unit is configured with a plurality of main control registers, and wherein the main control registers are used to record the delay duration of the main control unit in processing different test instructions; and

[0011] A flash memory monitoring unit, communicatively connected between the main control unit and the flash memory unit, wherein the flash memory monitoring unit is configured with a plurality of flash memory registers, and the flash memory registers are used to record the delay duration of the flash memory unit when performing different operations;

[0012] The main control unit determines whether the sum of the delay durations is greater than a preset total duration: if so, the firmware is optimized; otherwise, there is no need to optimize the firmware.

[0013] In one embodiment of the present invention, the delay duration recorded by the master control monitoring unit includes a read command delay duration, a write command delay duration, an erase command delay duration, a command decoding delay duration, a mapping delay duration, a direct access data delay duration, a garbage collection command delay duration, a background operation delay duration, and a firmware execution delay duration;

[0014] When the processor sends a test instruction to the main control unit and the main control unit parses the test instruction, the main control register records a corresponding timestamp and calculates a corresponding delay duration according to the timestamp.

[0015] In one embodiment of the present invention, the delay duration recorded by the flash memory monitoring unit includes a read operation delay duration, a write operation delay duration, an erase operation delay duration, a decoding operation delay duration, an encoding operation delay duration, a bad block management delay duration, and a garbage collection operation delay duration;

[0016] When the main control unit sends a control instruction to the flash memory unit, and the flash memory unit performs different operations according to the control instruction, the flash memory register records a corresponding timestamp and calculates a corresponding delay duration according to the timestamp.

[0017] In one embodiment of the present invention, when the sum of the delay durations is greater than the preset total duration, the main control unit optimizes the corresponding processing flow when determining that the delay duration for processing a certain test instruction is greater than the corresponding preset duration, and / or the flash memory unit optimizes the corresponding processing flow when determining that the delay duration for performing a corresponding operation according to a certain control instruction is greater than the corresponding preset duration.

[0018] In one embodiment of the present invention, when the main control unit determines that one of the read command delay time, the write command delay time, and the erase command delay time is greater than the corresponding preset time, the corresponding processing flow is optimized from the direction of increasing the frequency of the main control unit.

[0019] In one embodiment of the present invention, when the main control unit determines that the command decoding delay duration is greater than the corresponding preset duration, it optimizes from the direction of improving the hardware structure of the decoding module in the main control unit and / or increasing the parallel processing circuit.

[0020] In one embodiment of the present invention, when the main control unit determines that the mapping delay duration is greater than the corresponding preset duration, the main control unit performs optimization from the direction of selecting a different table lookup algorithm and / or increasing the capacity of the cache.

[0021] In one embodiment of the present invention, when the main control unit determines that the delay duration of direct access to data is greater than the corresponding preset duration, it optimizes in the direction of increasing the bus bandwidth and / or in the direction of transmitting the data in blocks.

[0022] In one embodiment of the present invention, when the main control unit determines that one of the garbage collection command delay time, the background operation delay time, and the firmware execution delay time is greater than the corresponding preset time, it optimizes from the direction of optimizing the firmware algorithm.

[0023] The present invention also discloses a memory and an optimization method thereof, comprising:

[0024] The main control unit receives different test instructions of the processor through the transmission interface unit, analyzes the test instructions, and generates corresponding control instructions;

[0025] The main control monitoring unit records the delay time of the main control unit in processing different test instructions through the main control register;

[0026] The flash memory unit performs different operations according to the control instructions;

[0027] The flash memory monitoring unit records the delay duration of the flash memory unit when performing different operations through the flash memory register;

[0028] Determine whether the sum of the delay durations is greater than a preset total duration: if so, optimize the firmware; otherwise, there is no need to optimize the firmware.

[0029] As described above, the present invention provides a memory and an optimization method thereof. Through the newly added main control monitoring unit and flash memory monitoring unit, the whole process time consumption of the memory from receiving the CMD instruction to completing the task operation can be monitored in real time. The monitoring covers all instruction operations and state transitions from the host to the memory, and can accurately quantify and analyze the independent delays and the total delays of each part inside the memory chip. This all-round monitoring provides detailed data support for optimizing the execution efficiency of firmware and hardware. At the same time, it is possible to quantify the delays of each part of the main control unit and flash memory unit of different memories under different CMD instructions. This capability enables system developers to understand the delay bottlenecks under specific operating conditions in detail, find out the main factors affecting performance, and provide accurate directions for further optimization. Furthermore, it is possible to perform comprehensive delay monitoring on the firmware and hardware behaviors inside the memory. For the execution delay of the firmware, the response time of the hardware operation, etc., accurate measurement data can be provided. This capability can help developers identify performance bottlenecks in firmware or hardware, optimize the execution order or algorithm of specific tasks, and thus improve the overall performance and response speed of the memory. Finally, by monitoring and analyzing various delay data, a more specific and intuitive model support can be provided for the performance optimization of the memory system. Developers can develop more sophisticated optimization strategies based on this data to increase the read and write speeds of storage chips, reduce latency, and improve the overall performance of the system.

[0030] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 A schematic diagram of a memory testing system according to an embodiment of the present invention;

[0033] Figure 2 FIG. 4 is a schematic diagram of a memory in an embodiment of the present invention.

[0034] In the figure: 100, processor; 200, memory; 300, storage device; 400, power supply; 500, first interface; 600, second interface; 700, memory; 710, main control unit; 720, transmission interface unit; 730, read-only storage unit; 740, random access memory unit; 750, cache unit; 760, flash memory unit; 770, main control monitoring unit; 780, flash memory monitoring unit. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] See also Figure 1 The present invention provides a memory test system, which can be used to test the memory 700 to comprehensively test and evaluate the delay performance of the memory 700 in different scenarios. The test system may include a processor 100, a memory 200, a storage device 300, a power supply 400, a first interface 500, and a second interface 600.

[0037] In one embodiment, the processor 100 may be a central processing unit. The central processing unit (CPU) may be responsible for interpreting and executing instructions in a program, controlling and processing data. The processor 100 may be a multi-core processor, and each core may process different data read and write requests in parallel, thereby increasing the parallelism of tasks and improving the overall test efficiency. In this embodiment, the processor 100 may test multiple memories 700 simultaneously to improve the test efficiency. Each core of the processor 100 may correspond to a memory 700.

[0038] In one embodiment, the memory 200 may be a dynamic random access memory (DRAM). The memory 200 may be used to store data and program codes so that the processor 100 can quickly access them.

[0039] In one embodiment, the storage device 300 may be a memory card (Secure Digital, SD). The SD card may be used to store an operating system and software programs required for running.

[0040] In one embodiment, the power supply 400 (POWER) can supply power to the processor 100 , the memory 200 , the storage device 300 , the storage 700 , etc., so as to drive the test system to work smoothly.

[0041] In one embodiment, the first interface 500 may be a Universal Asynchronous Receiver / Transmitter (UART). The processor 100 may communicate serially with the peripheral device through the first interface 500 to exchange data.

[0042] In one embodiment, the second interface 600 may be a Universal Serial Bus (USB). The second interface 600 may be used to connect various peripheral devices (such as a keyboard, a mouse, a printer, a mobile hard disk, etc.). The processor 100 may communicate data and provide power to the peripheral devices through the second interface 600.

[0043] In one embodiment, the memory 700 may be an embedded MultiMediaCard (eMMC) or a Universal Flash Storage (UFS). The memory 700 may communicate with the processor 100 via the CMD line and the DATA0~7 lines, and receive instructions from the processor 100 to perform operations such as read, write, and erase. The processor 100 may send instructions via the CMD line and transmit data via the DATA0~7 lines. The communication protocol between the memory 700 and the processor 100 may follow the JEDEC protocol.

[0044] See also Figure 2 In one embodiment, the memory 700 may include a main control unit 710, a transmission interface unit 720, a read-only storage unit 730, a random access storage unit 740, a cache unit 750, a flash memory unit 760, a main control monitoring unit 770, and a flash memory monitoring unit 780, etc.

[0045] In one embodiment, the main control unit 710 may be a microcontroller unit (MCU). The main control unit 710 may be used to perform specific control tasks, such as reading data, processing instructions from the processor 100, etc. The processing core of the main control unit 710 may be designed based on the RISC-V architecture to perform various control and computing tasks.

[0046] In one embodiment, the transmission interface unit 720 may be a transmission interface between the main control unit 710 and the processor 100. The transmission interface unit 720 may receive instructions from the processor 100, and return data or status information to the processor 100. The transmission interface unit 720 may receive instructions from the processor 100 through the CMD line and the DATA line, and return result data or execution status to the processor 100 through the DATA line.

[0047] In one embodiment, the read-only storage unit 730 may be a non-volatile memory (ROM) for long-term data storage. The read-only storage unit 730 may store a program, such as firmware. The program may be a set of pre-written instructions that instruct the main control unit 710 on how to start and run. These instructions include device initialization, peripheral configuration, and a possible boot loader. The boot loader may be used to load an updated program or operating system, etc.

[0048] In one embodiment, the random access memory unit 740 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program codes. The random access memory unit 740 may be used to temporarily store data. When the main control unit 710 executes a program, the program code may be loaded from the read-only storage unit 730 into the random access memory unit 740 for execution.

[0049] In one embodiment, the cache unit 750 can be used as a high-speed temporary storage area between the main control unit 710 and the flash memory unit 760 to store data and instructions frequently accessed by the main control unit 710 to achieve the function of accelerating data transmission.

[0050] In one embodiment, the flash memory unit 760 may be a physical unit for storing data in the memory 700. The flash memory unit 760 may be composed of a plurality of storage blocks. Each storage block may contain a plurality of pages. Each page is the minimum unit of a read / write operation, and a block is the minimum unit of an erase operation. Data is usually read and written in units of pages, and the entire block needs to be erased when erasing.

[0051] In one embodiment, the master control monitoring unit 770 (TeM) can be communicatively connected between the transmission interface unit 720 and the master control unit 710. The master control monitoring unit 770 can be used to monitor the running time of the hardware related to the master control unit 710 and the running time of the firmware. This includes how the processor in the master control unit 710 schedules tasks and how the firmware executes related commands and operations. The master control monitoring unit 770 can be configured with multiple master control registers, each of which can correspond to different operations of the master control unit 710, and the master control register can be used to record the delay time of the master control unit 710 in processing different test instructions issued by the processor 100.

[0052] In one embodiment, the flash memory monitoring unit 780 (TnM) can be communicatively connected between the main control unit 710 and the flash memory unit 760. The flash memory monitoring unit 780 can be used to measure and record various operation times of the flash memory unit 760. This includes the execution time of each instruction, as well as the time consumed when performing data write (Program), read (Read), and erase (Erase) operations. The flash memory monitoring unit 780 can be configured with multiple flash memory registers, each of which can correspond to different operations of the flash memory unit 760, and the main control register can be used to record the delay time of the flash memory unit 760 when performing different operations.

[0053] In one embodiment, when the processor 100 tests the memory 700, the processor 100 can start the memory 700 by sending test instructions such as read, write, and erase. These test instructions are sent to the main control unit 710 inside the memory 700, and the main control unit 710 performs specific operations according to the test instructions, and simultaneously starts the main control monitoring unit 770 and the flash memory monitoring unit 780 to record the corresponding delay duration.

[0054] In one embodiment, when the main control unit 710 receives a test instruction from the processor 100, the main control monitoring unit 770 and the flash memory monitoring unit 780 can be started through the RISC-V core to record the delay duration of different operations related to the main control unit 710 and the delay duration of different operations related to the flash memory unit 760.

[0055] In one embodiment, when the processor 100 sends a test instruction to the main control unit 710 and the main control unit 710 parses the test instruction, the corresponding main control register records the corresponding timestamp and calculates the corresponding delay duration according to the timestamp. The delay duration recorded by the main control monitoring unit 770 may include a read command delay duration, a write command delay duration, an erase command delay duration, a command decoding delay duration, a mapping delay duration, a direct access data delay duration, a garbage collection command delay duration, a background operation delay duration, and a firmware execution delay duration, etc.

[0056] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing a read operation, the master control register A related to the read operation in the master control monitoring unit 770 may be triggered. When the read operation is started, the identifier of the master control register A may be set to 1, and the master control monitoring unit 770 may record the corresponding timestamp. When the read operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register A to 0, and the master control monitoring unit 770 may record the corresponding timestamp. The master control monitoring unit 770 may calculate the read command delay duration (Te-1) through the two recorded timestamps. The read command delay duration (Te-1) refers to the delay duration when the master control unit 710 processes the read operation.

[0057] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing a write operation, the master control register B related to the write operation in the master control monitoring unit 770 may be triggered. When the write operation is started, the identifier of the master control register B may be set to 1, and the master control monitoring unit 770 may record the corresponding timestamp. When the write operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register B to 0, and the master control monitoring unit 770 may record the corresponding timestamp. The master control monitoring unit 770 may calculate the write command delay duration (Te-2) through the two recorded timestamps. The write command delay duration (Te-2) refers to the delay duration when the master control unit 710 processes the write operation.

[0058] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start the erase operation, the master control register C related to the erase operation in the master control monitoring unit 770 can be triggered. When the erase operation is started, the identifier of the master control register C can be set to 1, and the master control monitoring unit 770 can record the corresponding timestamp. When the erase operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register C to 0, and the master control monitoring unit 770 can record the corresponding timestamp. The master control monitoring unit 770 can calculate the erase command delay time (Te-3) through the two recorded timestamps. The erase command delay time (Te-3) refers to the delay time when the master control unit 710 processes the erase operation.

[0059] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing the command decoding (CMDDecode) operation, the master control register D related to the command decoding operation in the master control monitoring unit 770 can be triggered. When the command decoding operation is started, the identifier of the master control register D can be set to 1, and the master control monitoring unit 770 can record the corresponding timestamp. When the command decoding operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register D to 0, and the master control monitoring unit 770 can record the corresponding timestamp. The master control monitoring unit 770 can calculate the command decoding delay time (Te-4) through the two recorded timestamps. The command decoding delay time (Te-4) refers to the delay of the master control unit 710 for command decoding (CMD Decode), and how the master control unit 710 interprets it as the time consumption of a specific operation after receiving the command decoding command.

[0060] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start performing a mapping operation (Logical Block Address / Physical Block Address, LBA / PBA), the master control register E in the master control monitoring unit 770 related to the mapping operation may be triggered. When the mapping operation is started, the identifier of the master control register E may be set to 1, and the master control monitoring unit 770 may record the corresponding timestamp. When the mapping operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register E to 0, and the master control monitoring unit 770 may record the corresponding timestamp. The master control monitoring unit 770 may calculate the mapping delay duration (Te-5) through the two recorded timestamps. The mapping delay duration (Te-5) refers to the delay duration of the master control unit 710 processing the mapping of the logical block address (LBA) and the physical block address (PBA). The conversion of LBA and PBA is an important operation of the storage system, and this part of the delay will affect the efficiency of data access.

[0061] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing a direct memory access operation (DMA), the master control register F in the master control monitoring unit 770 related to the direct memory access operation may be triggered. When the direct memory access operation is started, the identifier of the master control register F may be set to 1, and the master control monitoring unit 770 may record the corresponding timestamp. When the direct memory access operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register F to 0, and the master control monitoring unit 770 may record the corresponding timestamp. The master control monitoring unit 770 may calculate the direct access data delay time (Te-6) through the two recorded timestamps. The direct access data delay time (Te-6) refers to the delay in transmitting data through DMA (direct memory access), which is a mechanism to improve data transmission efficiency.

[0062] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start a garbage collection operation (Garbage Collection, GC), the master control register G related to the garbage collection operation in the master control monitoring unit 770 can be triggered. When the garbage collection operation is started, the identifier of the master control register G can be set to 1, and the master control monitoring unit 770 can record the corresponding timestamp. When the garbage collection operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register G to 0, and the master control monitoring unit 770 can record the corresponding timestamp. The master control monitoring unit 770 can calculate the garbage collection command delay time (Te-7) through the two recorded timestamps. The garbage collection command delay time (Te-7) refers to the delay of garbage collection, and GC is a part of the unused space in the flash memory unit 760.

[0063] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing background operations (Background Operations, BKOPS), the master control register H related to the background operation in the master control monitoring unit 770 can be triggered. When the background operation is started, the identifier of the master control register H can be set to 1, and the master control monitoring unit 770 can record the corresponding timestamp. When the background operation is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register H to 0, and the master control monitoring unit 770 can record the corresponding timestamp. The master control monitoring unit 770 can calculate the background operation delay duration (Te-8) through the two recorded timestamps. The background operation delay duration (Te-8) refers to the delay of the background operation. Background tasks include operations such as data sorting and optimization. These background operations are performed when the system is busy.

[0064] In one embodiment, when the processor 100 notifies the master control monitoring unit 770 to start executing the firmware, the master control register I related to the firmware in the master control monitoring unit 770 may be triggered. When the firmware is started, the identifier of the master control register I may be set to 1, and the master control monitoring unit 770 may record the corresponding timestamp. When the firmware execution is completed, the processor 100 notifies the master control monitoring unit 770 again, sets the identifier of the master control register I to 0, and the master control monitoring unit 770 may record the corresponding timestamp. The master control monitoring unit 770 may calculate the firmware execution delay duration (Te-9) through the two recorded timestamps. The firmware execution delay duration (Te-9) refers to the delay in the execution of the firmware code. The firmware is the operating system of the memory controller. Monitoring its execution delay helps optimize the overall system response.

[0065] In one embodiment, when the main control unit 710 sends a control instruction to the flash memory unit 760 and the flash memory unit 760 performs different operations according to the control instruction, the corresponding flash memory register records the corresponding timestamp and calculates the corresponding delay duration according to the timestamp. The delay duration recorded by the flash memory monitoring unit 780 may include a read operation delay duration, a write operation delay duration, an erase operation delay duration, a decoding operation delay duration, an encoding operation delay duration, a bad block management delay duration, and a garbage collection operation delay duration, etc.

[0066] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start performing a read operation, the flash memory register J related to the read operation in the flash memory monitoring unit 780 can be triggered. When the read operation is started, the identifier of the flash memory register J can be set to 1, and the flash memory monitoring unit 780 can record the corresponding timestamp. When the read operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register J to 0, and the flash memory monitoring unit 780 can record the corresponding timestamp. The flash memory monitoring unit 780 can calculate the read operation delay time (Tn-1) through the two recorded timestamps. The read operation delay time (Tn-1) refers to the delay time of the flash memory unit 760 when performing a read operation.

[0067] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start performing a write operation, the flash memory register K related to the write operation in the flash memory monitoring unit 780 may be triggered. When the write operation is started, the identifier of the flash memory register K may be set to 1, and the flash memory monitoring unit 780 may record the corresponding timestamp. When the write operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register K to 0, and the flash memory monitoring unit 780 may record the corresponding timestamp. The flash memory monitoring unit 780 may calculate the write operation delay duration (Tn-2) through the two recorded timestamps. The write operation delay duration (Tn-2) refers to the delay duration of the flash memory unit 760 when performing a write operation.

[0068] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start the erase operation, the flash memory register L related to the erase operation in the flash memory monitoring unit 780 can be triggered. When the erase operation is started, the identifier of the flash memory register L can be set to 1, and the flash memory monitoring unit 780 can record the corresponding timestamp. When the erase operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register L to 0, and the flash memory monitoring unit 780 can record the corresponding timestamp. The flash memory monitoring unit 780 can calculate the erase operation delay time (Tn-3) through the two recorded timestamps. The erase operation delay time (Tn-3) refers to the delay time of the flash memory unit 760 when performing the erase operation.

[0069] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start a decoding operation (Decode), the flash memory register M related to the decoding operation in the flash memory monitoring unit 780 may be triggered. When the decoding operation is started, the identifier of the flash memory register M may be set to 1, and the flash memory monitoring unit 780 may record the corresponding timestamp. When the decoding operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register M to 0, and the flash memory monitoring unit 780 may record the corresponding timestamp. The flash memory monitoring unit 780 may calculate the decoding operation delay time (Tn-4) through the two recorded timestamps. The decoding operation delay time (Tn-4) refers to the delay time of the flash memory unit 760 when performing the decoding operation. The decoding operation refers to converting the received command or data into an executable format.

[0070] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start executing the encoding operation (Program), the flash memory register N related to the encoding operation in the flash memory monitoring unit 780 can be triggered. When the encoding operation is started, the identifier of the flash memory register N can be set to 1, and the flash memory monitoring unit 780 can record the corresponding timestamp. When the encoding operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register N to 0, and the flash memory monitoring unit 780 can record the corresponding timestamp. The flash memory monitoring unit 780 can calculate the encoding operation delay time (Tn-5) through the two recorded timestamps. The encoding operation delay time (Tn-5) refers to the delay time for the flash memory unit 760 to transfer data from the host to the storage block of the flash memory unit 760. This process involves programming charges in the flash memory block to represent the stored data bits (0 or 1).

[0071] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start performing a bad block management operation (Bad Block Management), the flash memory register O related to the bad block management operation in the flash memory monitoring unit 780 may be triggered. When the bad block management operation is started, the identifier of the flash memory register O may be set to 1, and the flash memory monitoring unit 780 may record the corresponding timestamp. When the bad block management operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register O to 0, and the flash memory monitoring unit 780 may record the corresponding timestamp. The flash memory monitoring unit 780 may calculate the bad block management delay (Tn-6) through the two recorded timestamps. The bad block management delay (Tn-6) refers to the delay of bad block management. The flash memory unit 760 may have bad blocks. It takes time to manage the bad blocks and ensure that data is written to healthy blocks. This part of the delay may also affect performance.

[0072] In one embodiment, when the main control unit 710 notifies the flash memory monitoring unit 780 to start a garbage collection operation (GC), the flash memory register P related to the garbage collection operation in the flash memory monitoring unit 780 may be triggered. When the garbage collection operation is started, the identifier of the flash memory register P may be set to 1, and the flash memory monitoring unit 780 may record the corresponding timestamp. When the garbage collection operation is completed, the main control unit 710 notifies the flash memory monitoring unit 780 again, sets the identifier of the flash memory register P to 0, and the flash memory monitoring unit 780 may record the corresponding timestamp. The flash memory monitoring unit 780 may calculate the garbage collection operation delay (Tn-7) through the two recorded timestamps. The garbage collection operation delay (Tn-7) refers to the delay of the garbage collection of the storage block. In the flash memory unit 760, the deleted or updated data may leave invalid old data blocks. The garbage collection process scans these data blocks and cleans up the data that is no longer needed.

[0073] In one embodiment, after obtaining the corresponding delay durations recorded by multiple master control registers and the corresponding delay durations recorded by multiple flash memory registers, the master control unit 710 can calculate the sum of all delay durations, and compare the sum of the delay durations with the preset total duration to determine whether the memory 700 needs to be optimized. Among them, the preset total duration refers to the sum of all preset durations (Spec (Specification) defined values). The preset duration refers to the performance index of the memory 700 in various operating scenarios. The preset duration is defined by the equipment manufacturer or industry standard organization, and represents the performance that the memory should achieve under ideal or standard conditions. For example, the delay durations of operations such as reading, writing, erasing, decoding, encoding, bad block management, and garbage collection of the memory 700 all correspond to a preset duration, and these preset durations can be determined through a large amount of testing, optimization, and experience.

[0074] In one embodiment, the measured delay duration refers to the delay monitored by the main control monitoring unit 770 and the flash memory monitoring unit 780 in actual operation. These delay durations reflect the actual response time of the main control unit 710 and the flash memory unit 760 under specific operations (such as Read, Write, Erase, Decode, Program, GC, etc.). By comparing the sum of the delay durations with the preset total duration, it is possible to evaluate whether the performance of the memory 700 meets the expected standard. If the sum of the delay durations is greater than the preset total duration, it means that the performance of one or some operations is not up to standard, which may be the performance bottleneck of the memory 700. At this time, it is clear which operations need to be optimized. For high-delay operations, specific optimization strategies (such as improving firmware, optimizing command processing logic, improving hardware performance, etc.) can be adopted. If the sum of the delay durations is less than or equal to the preset total duration, it means that the memory 700 can meet the user experience requirements and industry standards in actual use, ensuring the reliability and consistency of the system.

[0075] In one embodiment, when the sum of the delay durations is greater than the preset total duration, the delay duration of each operation can be compared with the corresponding preset duration. When the delay duration of the main control unit 710 in processing a certain test instruction is greater than the corresponding preset duration, the corresponding processing flow can be optimized. When the delay duration of the flash memory unit 760 in executing a corresponding operation according to a certain control instruction is greater than the corresponding preset duration, the corresponding processing flow can be optimized.

[0076] In one embodiment, when one of the read command delay, write command delay, and erase command delay of the main control unit 710 is greater than the corresponding preset delay, it may indicate that the main control unit 710 failed to complete a certain command operation within the specified time (CMD timeout) when processing the read, write, and erase operations. The main control unit 710 will set a time threshold, and the operation needs to be completed within the time range, otherwise a timeout error will be triggered. Timeout may mean that the operation takes too long, there is a bottleneck in system performance, or the main control unit 710 is inefficient in processing instructions, which may be related to multiple factors such as hardware, firmware, and frequency settings.

[0077] Specifically, the frequency of the MCU directly affects the instruction processing speed of the main control unit 710. The MCU in the main control unit 710 is responsible for processing multiple tasks such as command decoding, data transmission, and storage management. When processing operations such as reading, writing, and erasing, the low MCU frequency may cause the command processing speed to not keep up, thereby increasing the probability of CMD timeout. For the optimization of CMD timeout, the frequency of the MCU can be optimized to increase the computing speed to speed up the processing of commands and the transmission speed of data, thereby reducing the frequency of CMD timeout. For example, when a CMD timeout problem is detected, the MCU frequency can be optimized by adjusting the dynamic voltage and frequency adjustment (DVFS). DVFS is a technology that dynamically adjusts the operating frequency and voltage of the MCU, and automatically adjusts according to the real-time load conditions of the system to achieve a balance between performance and power consumption.

[0078] In one embodiment, when the command decoding delay time of the main control unit 710 is greater than the corresponding preset time, it may mean that when the main control unit 710 is processing the command decoding operation, the main control unit 710 fails to complete the decoding operation within the specified time (CMD Decode timeout). CMD Decode timeout means that after the main control unit 710 receives the command, the process of decoding these commands takes too long, exceeding the predetermined time limit. Command decoding involves converting the received commands (such as read, write, erase) into instructions that can be executed inside the controller. This step is the basis of storage operations, and the delay in decoding will affect the efficiency of subsequent read, write, erase and other operations.

[0079] Specifically, for the optimization of CMD Decode timeout, we can optimize it from the direction of hardware design optimization. Hardware design optimization refers to improving the hardware structure of the decoding module in the main control unit to make the decoding process more efficient and reduce the decoding time. Specific hardware optimization methods include: improving the computing power of the decoder, using more efficient logic circuits or improving decoding algorithms to reduce the number of clock cycles required for decoding; simplifying the decoding process, optimizing the logical path of command decoding, reducing intermediate processing steps, and making the decoding process more direct and efficient; improving the data path, ensuring that the data transmission path is wide enough, and reducing the data transmission bottleneck during decoding, especially when processing large-scale commands at high speed. Optimizing the decoding hardware design can directly improve the overall performance of the decoding module, ensuring that it can complete command processing tasks faster, thereby reducing the occurrence of timeouts.

[0080] Furthermore, for the optimization of CMD Decode timeout, it is also possible to optimize by adding parallel processing circuits. Parallel processing circuits refer to the addition of multiple decoding circuits so that the system can process multiple commands at the same time and increase the throughput of the system. For decoding operations, increasing parallelism can significantly increase the decoding speed. The advantages of adding parallel processing circuits include: processing multiple commands at the same time. Through the parallel decoding mechanism, the system can decode multiple commands at the same time instead of processing them one by one in sequence. This is especially effective when facing a large number of command requests, and can reduce the waiting time for a single command; improving system throughput. Parallel decoding can increase the number of commands processed per unit time, thereby improving the overall performance of the system, especially in high-load scenarios; reducing decoding bottlenecks. Parallel processing can avoid command queuing and delays caused by a single decoding module being busy.

[0081] In one embodiment, when the mapping delay time of the main control unit 710 is greater than the corresponding preset time, it may indicate that when the main control unit 710 processes the mapping operation, the main control unit 710 fails to complete the mapping operation within the specified time (LBA / PBA timeout). LBA is the logical block address of the operating system, and PBA is the physical block address used in the actual memory 700. When the main control unit 710 performs a read and write operation, it is necessary to convert LBA to PBA through a mapping table to find the storage location of the data. If the mapping operation times out, it means that the mapping table search process takes too long, affecting the read and write performance of the system. Therefore, it is necessary to optimize from both software and hardware perspectives. The software optimization direction mainly improves the logical efficiency of the mapping table search by improving the table lookup algorithm. According to different application scenarios, the most suitable algorithm is selected to reduce the time of the mapping operation. The hardware optimization direction mainly increases the capacity of SRAM and reduces the frequency of searching for mapping relationships from the flash memory. The SRAM speed is much faster than the flash memory, so increasing the SRAM capacity can significantly reduce the timeout phenomenon.

[0082] Specifically, for the optimization of LBA / PBA timeout, we can optimize from the direction of software optimization to select a suitable table lookup algorithm. The mapping table lookup algorithm is a key factor affecting the efficiency of LBA / PBA mapping. Different application scenarios may require different algorithms to improve the lookup efficiency. Software optimization mainly selects a suitable table lookup algorithm based on the characteristics of data access to reduce time consumption. For example, for sequential read and write data, LBA can be continuous, so a binary search algorithm can be used. The time complexity of binary search is O(log n). In sequential data access, binary table lookup can quickly locate the PBA corresponding to the LBA. For random read and write, LBA access is irregular, and traditional sequential search or binary search is not efficient. In this case, a hash algorithm can be used. The time complexity of hash search is close to O(1), which can significantly improve the table lookup efficiency in random read and write scenarios.

[0083] Furthermore, for the optimization of LBA / PBA timeout, it is also possible to optimize from the direction of hardware optimization to increase SRAM to improve the table lookup speed. SRAM (Static RAM) is often used as a cache in the memory 700 to store the mapping relationship of LBA / PBA. Compared with searching for mapping relationships from NAND flash memory, searching from SRAM is much faster because SRAM has lower access latency. For example, by increasing the capacity of SRAM, assuming that the current SRAM capacity is 100KB, the stored mapping relationships are limited. When the LBA / PBA mapping table is not in SRAM, the main control unit needs to search from NAND, which is much more time-consuming than searching from SRAM. If the SRAM capacity is increased to 150KB, more mapping tables can be cached in SRAM, reducing the frequency of table lookups from NAND, thereby improving the overall table lookup efficiency.

[0084] In one embodiment, when the direct access data delay time of the main control unit 710 is greater than the corresponding preset time, it may indicate that when the main control unit 710 is processing the direct memory access operation, the main control unit 710 fails to complete the direct memory access operation within the specified time (DMA Data timeout). DMA is a mechanism for directly transferring data between a device and memory, bypassing the CPU, reducing CPU load, and improving data transfer efficiency. DMA operations are widely used in storage controllers, network devices, and embedded systems. DMA Data timeout refers to the failure of data to be completed within the expected time during DMA data transmission, resulting in operation delays or system waits. The reasons for the timeout may include hardware bottlenecks, data transmission path congestion, improper DMA controller configuration, etc. When the main control unit 710 processes direct memory access (DMA Data) operations, if a DMA Data timeout occurs, it means that the data transmission cannot be completed within the predetermined time. This will affect the system performance and cause operation delays or failures. In order to reduce the timeout problem, optimization can be performed from two aspects: hardware speed optimization and DMA usage strategy. Hardware optimization focuses on improving the transmission speed and reducing delays in DMA operations, fundamentally speeding up data transmission. For example, increasing the bus bandwidth or optimizing the design of the DMA controller can directly improve the data transmission efficiency. DMA usage strategy optimization makes DMA operations more efficient and flexible and reduces the occurrence of timeouts by reasonably configuring and managing DMA operations, such as transmitting data in blocks and increasing priorities.

[0085] Specifically, for the optimization of DMA Data timeout, we can optimize from the direction of hardware optimization to speed up data transmission and reduce bottlenecks in the transmission path, thereby improving the efficiency of DMA operations. For example, improving bus bandwidth. DMA operations rely on the system bus for data transmission. If the bus bandwidth is insufficient, the data transmission speed will be limited, resulting in DMA timeout problems. Increasing the operating frequency of the bus or selecting a bus interface with higher bandwidth (such as PCIe, AXI, etc.) can improve the transmission speed. For another example, optimizing the DMA controller design. The design of the DMA controller determines its performance. If the DMA controller has a design bottleneck, such as insufficient processing power or insufficient clock speed, data transmission can be accelerated by optimizing the hardware design or upgrading the DMA controller.

[0086] Furthermore, for the optimization of DMA Data timeout, we can also optimize the DMA usage strategy to reduce timeouts. For example, for large data transmission tasks, data can be transmitted in blocks instead of all at once. This method can avoid timeouts caused by excessive single transmission volume and reduce bus load. At the same time, small block data transmission is easier to schedule, DMA operations can be completed faster, and delays can be reduced. For another example, improving DMA transmission priority In some systems, the priority of DMA operations may be low, resulting in obstruction during bus access. By increasing the priority of DMA transmission, it can be ensured that the DMA controller can obtain bus access rights first, reduce waiting time, and avoid timeouts. For another example, reasonably set the DMA buffer. DMA operations usually use memory buffers to store data to be transmitted. Reasonable configuration and optimization of the size and location of these buffers can reduce data waiting time and improve DMA transmission efficiency. For example, using double-buffering technology, while one buffer is transmitting data, another buffer is preparing the next batch of data, realizing continuous data transmission. For example, using the appropriate DMA transfer mode, DMA controllers usually support multiple transfer modes, such as burst mode, cyclic mode, etc. Selecting the appropriate mode according to different application scenarios can improve the transmission efficiency. For example, the burst mode is more efficient when transmitting a large amount of continuous data, while the cyclic mode is more suitable for the repeated transmission of small data blocks.

[0087] In one embodiment, when the delay time of the garbage collection command of the main control unit 710 is greater than the corresponding preset time, it may indicate that when the main control unit 710 is processing the garbage collection operation, the main control unit 710 fails to complete the garbage collection operation within the specified time (GC timeout). When the GC times out, it may cause an increase in read and write delays and even affect the normal operation of the system. In order to solve the GC timeout problem, the garbage collection efficiency can be improved by optimizing the firmware algorithm strategy. The main optimization directions may include reducing the amount of data migration, optimizing the GC scheduling strategy, adopting a more efficient GC algorithm, and improving data writing and sorting strategies.

[0088] Specifically, the firmware algorithm can be optimized from the perspective of reducing the frequency of GC operations and the amount of data migration. Reducing the frequency of GC operations means postponing GC operations until the system is idle through intelligent prediction and management, thereby reducing interference with real-time operations. By monitoring the I / O load of the system, GC can be performed when the load is low to avoid timeout problems during high loads. Reducing the amount of data migration means using intelligent data sorting algorithms, such as hot and cold data separation, to store frequently accessed data (hot data) and rarely accessed data (cold data) separately, thereby reducing the amount of data that needs to be migrated during the GC process. For blocks where cold data is located, they can be directly erased during GC, greatly reducing migration time.

[0089] Furthermore, the firmware algorithm can be optimized from the perspective of optimizing the GC scheduling strategy. When performing garbage collection, blocks with the most invalid data are selected for cleaning. By giving priority to cleaning blocks with a high proportion of invalid data, the migration of valid data can be minimized and GC efficiency can be improved. The GC strategy can be dynamically adjusted according to the current state and workload of the system. For example, when write operations are frequent, the number of GC operation triggers can be reduced; when read operations are frequent, blocks that affect read performance can be processed first.

[0090] Furthermore, the firmware algorithm can be optimized by adopting a more efficient GC algorithm. Different GC priorities can be set for different I / O operations (read, write, erase). For example, GC activity can be reduced during high-priority read operations to reduce the impact on read performance. If hardware resources allow, GC operations can be parallelized, and multiple GC threads can be assigned to process different storage units or blocks at the same time, reducing the time of a single GC operation.

[0091] Furthermore, the firmware algorithm can be optimized from the perspective of improving data writing and sorting strategies. In particular, the wear leveling algorithm is implemented in the firmware to evenly distribute write and erase operations to avoid the increase in GC burden caused by frequent use of certain blocks. Wear leveling not only prolongs the life of the storage device, but also optimizes the timing and execution efficiency of GC operations. Multiple small blocks of data are merged into a large block for writing and sorting, reducing data fragmentation during the GC process, thereby reducing migration time.

[0092] In one embodiment, when the background operation delay duration of the main control unit 710 is greater than the corresponding preset duration, it may indicate that when the main control unit 710 is processing the background operation, the main control unit 710 fails to complete the background operation within the specified time. Background operation refers to tasks in the memory 700 that are not directly involved in the foreground I / O request, such as garbage collection, wear leveling, bad block management, and data sorting. Background operation timeout means that these tasks cannot be completed within the set time, which may be due to large operation volume, excessive system load, or unreasonable resource scheduling. If the timeout problem is not solved, the background operation may conflict with the foreground operation, reducing the overall system performance. In order to solve the problem of background operation timeout, the garbage collection efficiency can be improved by optimizing the firmware algorithm strategy. By optimizing the firmware algorithm strategy, background tasks can be effectively managed, their impact on system performance can be reduced, and timeouts can be avoided.

[0093] Specifically, the firmware algorithm can be optimized from the perspective of task scheduling and priority management. Background operations can usually be set as low-priority tasks. When the system load is light, background tasks can be fully executed; when the foreground task load is heavy, background tasks should be temporarily stopped or their execution frequency should be reduced. This approach can prevent background operations from occupying too many resources and affecting the response speed of the foreground. According to the current system workload, the execution time and resource occupancy of background operations are dynamically adjusted. For example, when the system detects that there are fewer foreground read and write requests, background tasks can be executed more actively, while execution is postponed under high load conditions. This scheduling strategy can ensure that background tasks can be completed in an appropriate time while balancing system resources.

[0094] Furthermore, the firmware algorithm can be optimized from the perspective of parallelization and block processing. If hardware resources allow, background operations can be processed in parallel. Assigning background tasks to multiple processing units or threads can significantly speed up the completion time of tasks and avoid timeouts. For example, tasks such as garbage collection and wear leveling can be executed in parallel to reduce the time consumption of a single task. Large background tasks can be broken down into multiple smaller blocks and executed step by step. This can avoid occupying too many resources at one time, and at the same time, the foreground and background operations can be performed alternately, reducing the impact of background tasks on system performance.

[0095] Furthermore, the firmware algorithm can be optimized from the perspective of optimizing the algorithm of specific background operations. Different types of background operations can reduce the occurrence of timeouts through specific algorithm optimization. When collecting garbage, an intelligent selection strategy (such as a greedy algorithm) is used to prioritize the recovery of blocks with the most invalid data, reducing the amount of data that needs to be migrated. This can significantly reduce the time of garbage collection operations. By predicting which blocks are about to be severely worn, data migration and sorting are performed in advance to avoid timeouts caused by sudden high-load wear leveling tasks. For the detection and repair of bad blocks, a fast detection algorithm can be used to reduce the resource time occupied during the background scanning and repair process.

[0096] Furthermore, the firmware algorithm can be optimized from the perspective of optimizing data caching and resource utilization. For frequently accessed data, the cache strategy can be optimized to load the relevant data into the cache (such as SRAM) in advance to reduce the need for background operations to access slow storage media (such as NAND), thereby reducing the time spent on background tasks. Dynamically adjust the resource ratio used by foreground and background tasks to ensure that background tasks do not occupy too many resources. When the foreground operation load is low, the resource allocation of background tasks can be appropriately increased to increase their execution speed.

[0097] Furthermore, the firmware algorithm can be optimized from the perspective of monitoring and feedback mechanisms. The firmware can add a timeout monitoring mechanism for background tasks to detect possible task timeouts in advance. When the system detects that a background task has been running for too long, it can avoid timeouts by adjusting the schedule or reducing the task priority. By real-time monitoring of the execution status of foreground and background operations, task allocation can be adjusted to ensure that background operations are performed when the system is idle as much as possible to avoid excessive interference with foreground operations.

[0098] In one embodiment, when one of the delay time of the read operation, the delay time of the write operation, and the delay time of the erase operation of the flash memory unit 760 is greater than the corresponding preset time, it may indicate that the flash memory unit 760 failed to complete a certain command operation within the prescribed time (CMD timeout) when processing the read, write, and erase operations. For the optimization of CMD timeout, the frequency of the MCU may be optimized to increase the operation speed to speed up the processing of commands and the transmission speed of data, thereby reducing the frequency of CMD timeout.

[0099] In one embodiment, when the decoding operation delay time of the flash memory unit 760 is greater than the corresponding preset time, it may indicate that the flash memory unit 760 fails to complete the decoding operation within the specified time when processing the decoding operation (CMD Decode timeout). For the optimization of CMD Decode timeout, the hardware structure of the decoding module in the main control unit may be improved to make the decoding process more efficient and reduce the decoding time, and optimization may also be performed in the direction of increasing parallel processing circuits.

[0100] In one embodiment, when the encoding operation delay time of the flash memory unit 760 is greater than the corresponding preset time, it may indicate that the flash memory unit 760 failed to complete the encoding operation within the specified time (Program timeout) when processing the encoding operation. Program operation timeout may be caused by several reasons such as differences in flash memory characteristics, poor operating conditions, chip wear, and improper parameter settings. Among them, NAND flash memories produced by different manufacturers may differ in process, reliability, and performance. For example, the Program operation of a certain NAND flash memory is slow, resulting in a timeout. The time of the Program operation is affected by physical conditions such as voltage and temperature. If the working environment is harsh, the Program operation may take longer. As the NAND flash memory is used, the storage unit will gradually wear out, and the Program time may increase, resulting in a timeout. Some parameters of the main control unit 710 (such as voltage and timing) may not be optimized, resulting in reduced write efficiency.

[0101] Specifically, for the Program timeout problem, the operation efficiency can be improved by optimizing and adjusting the relevant parameters of the main control unit 710 (adjusting the write voltage, optimizing the timing parameters, and using more efficient error correction codes). The Program operation relies on the control voltage to store the charge. If the write voltage is set too low, the write speed may be slowed down. Properly increasing the write voltage can speed up the write speed, thereby reducing the occurrence of Program timeout. According to the working conditions (such as temperature changes), the write voltage is dynamically adjusted to ensure the execution efficiency of the Program operation under different conditions. The main control unit 710 usually has multiple sets of timing parameters (such as write intervals, delays, etc.), which will affect the speed and stability of writing. By optimizing these timing parameters, especially in high load or high temperature environments, the write operation can be accelerated to avoid timeouts. In some cases, too short a recovery time may cause conflicts in multiple write operations. By extending the recovery time, it can be ensured that each write operation can be completed smoothly to avoid Program operation conflicts. With the use of NAND flash memory, the possibility of bit errors increases, which may lead to multiple retries of the write operation, thereby extending the write time. By using a stronger error correction code (ECC), the frequency of error retries can be reduced and the write efficiency can be improved.

[0102] Furthermore, for the problem of Program timeout, you can also replace NAND flash memory from different manufacturers to improve operation efficiency. Due to differences in manufacturing processes, NAND chips from different manufacturers may have significant differences in Program time. Some NAND manufacturers have more technical advantages in optimizing write speed, so choosing NAND with shorter Program time can reduce timeouts. The service life (wear cycle) of flash memory directly affects write performance. Severely worn NAND may cause slower write speeds. Choosing NAND chips with better durability (such as products using SLC or MLC technology) can effectively avoid Program operation timeouts. NAND from some manufacturers is more stable under temperature fluctuations, suitable for working in extreme environments, and can avoid Program timeouts caused by temperature changes.

[0103] In one embodiment, when the bad block management delay time of the flash memory unit 760 is greater than the corresponding preset time, it may indicate that the flash memory unit 760 failed to complete the bad block management operation within the specified time when processing the bad block management operation. For the optimization of the bad block management timeout, the optimization may be performed from the direction of optimizing the firmware. For example, a fast detection algorithm may be used to reduce the resource time occupied during the background scanning and repair process.

[0104] In one embodiment, when the delay time of the garbage collection operation of the flash memory unit 760 is greater than the corresponding preset time, it can be indicated that when the flash memory unit 760 is processing the garbage collection operation, the flash memory unit 760 fails to complete the garbage collection operation within the specified time. For the optimization of the garbage collection timeout, the optimization can be performed from the direction of optimizing the firmware. For example, during garbage collection, an intelligent selection strategy (such as a greedy algorithm) is used to preferentially recycle the blocks with the most invalid data, thereby reducing the amount of data that needs to be migrated. This can significantly reduce the time of the garbage collection operation.

[0105] It can be seen that in the above scheme, through the newly added main control monitoring unit and flash memory monitoring unit, the time consumption of the entire process from receiving the CMD instruction to completing the task operation can be monitored in real time. This monitoring covers all instruction operations and state transitions from the host to the memory, and can accurately quantify and analyze the independent delays and the total delays of each part inside the memory chip. This all-round monitoring provides detailed data support for optimizing the execution efficiency of firmware and hardware. At the same time, it can quantify the delays of each part of the main control unit and flash memory unit of different memories under different CMD instructions. This capability allows system developers to understand the delay bottlenecks under specific operating conditions in detail, find out the main factors affecting performance, and provide precise directions for further optimization. Furthermore, it can perform comprehensive delay monitoring of the firmware and hardware behaviors inside the memory. It can provide accurate measurement data for the execution delay of firmware, the response time of hardware operations, etc. This capability can help developers identify performance bottlenecks in firmware or hardware, optimize the execution order or algorithm of specific tasks, and thus improve the overall performance and response speed of the memory. Finally, by monitoring and analyzing various delay data, it can provide more specific and intuitive model support for the performance optimization of the memory system. Developers can develop more sophisticated optimization strategies based on this data to increase the read and write speeds of storage chips, reduce latency, and improve the overall performance of the system.

[0106] The present invention also provides a memory optimization method, which can be applied to the above memory, and the optimization method may include the following steps:

[0107] The main control unit receives different test instructions from the processor through the transmission interface unit, analyzes the test instructions, and generates corresponding control instructions;

[0108] The main control monitoring unit records the delay time of the main control unit in processing different test instructions through the main control register;

[0109] The flash memory unit performs different operations according to the control instructions;

[0110] The flash memory monitoring unit records the delay time of the flash memory unit when performing different operations through the flash memory register;

[0111] Determine whether the sum of the delay durations is greater than the preset total duration; if so, optimize the firmware; otherwise, there is no need to optimize the firmware.

[0112] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: A transmission interface unit, communicatively connected to the processor; A main control unit receives different test instructions of the processor through the transmission interface unit, analyzes the test instructions, and generates corresponding control instructions; A flash memory unit, used to perform different operations according to the control instructions; A main control monitoring unit, communicatively connected between the transmission interface unit and the main control unit, wherein the main control monitoring unit is configured with a plurality of main control registers, and the main control registers are used to record the delay duration of the main control unit in processing different test instructions; as well as A flash memory monitoring unit, communicatively connected between the main control unit and the flash memory unit, wherein the flash memory monitoring unit is configured with a plurality of flash memory registers, and the flash memory registers are used to record the delay duration of the flash memory unit when performing different operations; The main control unit determines whether the sum of the delay durations is greater than a preset total duration: if so, the firmware is optimized; otherwise, there is no need to optimize the firmware.

2. The memory according to claim 1, characterized in that: The delay duration recorded by the master control monitoring unit includes read command delay duration, write command delay duration, erase command delay duration, command decoding delay duration, mapping delay duration, direct access data delay duration, garbage collection command delay duration, background operation delay duration, and firmware execution delay duration; When the processor sends a test instruction to the main control unit and the main control unit parses the test instruction, the main control register records a corresponding timestamp and calculates a corresponding delay duration according to the timestamp.

3. The memory according to claim 1, characterized in that: The delay duration recorded by the flash memory monitoring unit includes a read operation delay duration, a write operation delay duration, an erase operation delay duration, a decoding operation delay duration, an encoding operation delay duration, a bad block management delay duration, and a garbage collection operation delay duration; When the main control unit sends a control instruction to the flash memory unit, and the flash memory unit performs different operations according to the control instruction, the flash memory register records a corresponding timestamp and calculates a corresponding delay duration according to the timestamp.

4. The memory according to claim 2 or 3, characterized in that: When the sum of the delay durations is greater than the preset total duration, the main control unit optimizes the corresponding processing flow when determining that the delay duration for processing a certain test instruction is greater than the corresponding preset duration, and / or the flash memory unit optimizes the corresponding processing flow when determining that the delay duration for performing a corresponding operation according to a certain control instruction is greater than the corresponding preset duration.

5. The memory according to claim 4, characterized in that: When the main control unit determines that one of the read command delay time, the write command delay time, and the erase command delay time is greater than the corresponding preset time, the main control unit optimizes the corresponding processing flow in the direction of increasing the frequency of the main control unit.

6. The memory according to claim 4, characterized in that: When the main control unit determines that the command decoding delay time is greater than the corresponding preset time, the main control unit optimizes the hardware structure of the decoding module in the main control unit and / or increases the parallel processing circuit.

7. The memory according to claim 4, characterized in that: When the main control unit determines that the mapping delay duration is greater than the corresponding preset duration, the main control unit performs optimization from the direction of selecting a different table lookup algorithm and / or increasing the capacity of the cache.

8. The memory according to claim 4, characterized in that: When the main control unit determines that the delay time of direct access to data is greater than the corresponding preset time, it optimizes in the direction of increasing the bus bandwidth and / or in the direction of transmitting the data in blocks.

9. The memory according to claim 4, characterized in that: When the main control unit determines that one of the garbage collection command delay time, the background operation delay time, and the firmware execution delay time is greater than the corresponding preset time, the main control unit optimizes from the direction of optimizing the firmware algorithm.

10. A memory and an optimization method thereof, characterized in that: include: The main control unit receives different test instructions of the processor through the transmission interface unit, analyzes the test instructions, and generates corresponding control instructions; The main control monitoring unit records the delay time of the main control unit in processing different test instructions through the main control register; The flash memory unit performs different operations according to the control instructions; The flash memory monitoring unit records the delay duration of the flash memory unit when performing different operations through the flash memory register; Determine whether the sum of the delay durations is greater than a preset total duration: if so, optimize the firmware; otherwise, there is no need to optimize the firmware.

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