Power device and forming method thereof

Abstract

The embodiment of the invention provides a power device and a forming method thereof, and the method comprises the steps: providing a substrate which is provided with an epitaxial layer; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in contact with the top of the epitaxial layer in the dielectric layer; forming a metal contact layer on the dielectric layer; forming a first opening exposing the first alignment structure in the metal contact layer; an anti-etching layer filling the first opening and covering the top of the metal contact layer is formed, and the light transmittance of the anti-etching layer to the probe light is larger than that of the metal contact layer to the probe light. By adopting the technical scheme, the detection precision of the alignment structure can be improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a power device and a method for forming the same. Background Art

[0002] In the semiconductor field, power devices have high driving voltage, low resistance and good switching characteristics, and are widely used in high-voltage integrated circuits and power integrated circuits.

[0003] In the process of forming a power device, an alignment structure is usually formed, and the position of the alignment structure is detected to ensure the overlay accuracy between different process layers.

[0004] However, in the power devices currently formed, when the alignment structure is detected by detection light, the alignment structure cannot be detected or the detection effect is poor, and the intensity of the obtained alignment signal is weak. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a power device and a method for forming the same, which can improve the detection accuracy of the alignment structure.

[0006] An embodiment of the present invention provides a method for forming a power device, comprising: providing a substrate having an epitaxial layer on the substrate; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer that contacts the top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer that exposes the first alignment structure; forming an anti-etching layer that fills the first opening and covers the top of the metal contact layer, wherein the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light.

[0007] Optionally, the first alignment structure has a width of 1 μm to 8.8 μm and a height of 0.5 μm to 0.7 μm.

[0008] Optionally, a material of the first alignment structure includes one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

[0009] Optionally, the metal contact layer has a thickness of 3 μm to 5 μm.

[0010] Optionally, forming a first opening in the metal contact layer to expose the first alignment structure includes:

[0011] Forming a mask structure having a first graphic opening on the metal contact layer, wherein the first graphic opening is arranged opposite to the first alignment structure along a normal direction of the substrate surface;

[0012] Along the first graphic opening, removing the metal contact layer exposed by the first graphic opening, and forming a first opening in the metal contact layer to expose the first alignment structure;

[0013] After forming the first opening, the mask structure is removed.

[0014] Optionally, the process of removing the metal contact layer exposed by the first pattern opening includes: a dry etching process;

[0015] The parameters of the dry etching process include: pressure of 7mTorr to 9mTorr, power of 1000wT to 1200wT, RF energy of 335wB to 410wB, etching gases of CL2 and BCL3, wherein the flow rate of CL2 is 220sccm to 270sccm, and the flow rate of BCL3 is 125sccm to 150sccm.

[0016] Optionally, the step of forming a first opening in the metal contact layer to expose the first alignment structure further includes: forming a second opening in the metal contact layer on one side of the first opening to expose the top of the dielectric layer;

[0017] In the step of forming an anti-etching layer filling the first opening and covering the top of the metal contact layer, the anti-etching layer also fills the second opening, wherein the anti-etching layer located in the second opening serves as a second alignment structure.

[0018] Optionally, the material of the anti-etching layer is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0019] Optionally, before forming the anti-etching layer filling the first opening and covering the top of the metal contact layer, the method further includes:

[0020] forming a protective layer on the metal contact layer and in the first opening, wherein a top height of the protective layer in the first opening is lower than a top height of the first opening;

[0021] In the step of forming an anti-etching layer filling the first opening and covering the metal contact layer, the anti-etching layer also covers the top and a portion of the sidewall of the protection layer.

[0022] An embodiment of the present invention also provides a power device, comprising: a substrate having an epitaxial layer; a dielectric layer located on the epitaxial layer; a first alignment structure located in the dielectric layer and in contact with the top of the epitaxial layer; a metal contact layer located on the dielectric layer; and an anti-etching layer, comprising a first portion located on the metal contact layer and a second portion located in the metal contact layer and in contact with the top of the first alignment structure.

[0023] Optionally, the power device further includes: a protection layer located between the first portion and the metal contact layer, and between the second portion and the first alignment structure.

[0024] Optionally, the anti-etching layer further includes a third portion located in the metal contact layer and in contact with the top of the dielectric layer, and the third portion serves as a second alignment mark.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0026] In the method for forming a power device provided by an embodiment of the present invention, after forming a first alignment structure in contact with the top of the epitaxial layer in the dielectric layer, an anti-etching layer can be formed in the first opening by forming a first opening in the metal contact layer to expose the first alignment structure. Since the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light, the blocking of the metal contact layer to the detection light can be reduced, so that most of the detection light can be transmitted to the first alignment structure. In this way, when most of the detection light is irradiated to the first alignment structure, the intensity of the alignment signal can be increased, thereby improving the detection accuracy of the alignment structure.

[0027] In the power device provided by the embodiment of the present invention, the anti-etching layer includes a second portion within the metal contact layer and in contact with the top of the first alignment structure. Since the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light, the blocking of the metal contact layer to the detection light can be reduced, so that most of the detection light can be transmitted to the first alignment structure. In this way, when most of the detection light is irradiated to the first alignment structure, the intensity of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 8 The present invention is a schematic diagram of the structure corresponding to each step of a power device;

[0029] Fig. 9 It is a structural schematic diagram corresponding to an embodiment of a power device of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, in the currently formed power devices, when the alignment structure is detected by the detection light, the alignment structure cannot be detected or the detection effect is poor. This is because:

[0031] During the formation of power devices, a thicker metal layer needs to be grown to meet the electrical parameter requirements of the power devices (for example, in some application scenarios, the power devices need to have higher withstand voltage and current values); and in subsequent processing, a thicker photoresist needs to be spin-coated on the metal layer to ensure that the surface of the metal layer will not be etched, thereby improving the integrity of the surface of the metal layer.

[0032] Thus, under the double blocking of thicker metal and thicker photoresist, only a small portion of the detection light can be transmitted to the alignment structure (or called alignment mark), thereby causing adverse effects on the alignment process and even making it impossible to effectively perform the alignment operation.

[0033] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate having an epitaxial layer; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer that contacts the top of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer to expose the first alignment structure; forming an anti-etching layer that fills the first opening and covers the metal contact layer, wherein the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light.

[0034] In the formation method provided by the present invention, since the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light, the blocking of the metal contact layer to the detection light can be reduced, so that most of the detection light can be transmitted to the first alignment structure. In this way, when most of the detection light is irradiated to the first alignment structure, the intensity of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0035] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are exemplarily described below in conjunction with the accompanying drawings.

[0036] Figures 1 to 8 The present invention is a schematic structural diagram corresponding to each step of a power device.

[0037] See also Figure 1 , providing a substrate 100 having an epitaxial layer 102 thereon.

[0038] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of the power device. Among them, the power device may include a longitudinal double diffused metal oxide semiconductor structure LDMOS and / or a vertical double diffused metal oxide semiconductor structure VDMOS. In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator. The material of the substrate can be a material suitable for process requirements or easy to integrate.

[0039] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover a portion of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0040] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0041] In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0042] In this embodiment, the material of the isolation structure may be silicon oxide.

[0043] The epitaxial layer 102 serves to improve the withstand voltage of the power device. The thicker the epitaxial layer 102 is, the greater the withstand voltage of the power device is.

[0044] In this embodiment, an epitaxial layer 102 is formed on the substrate 100 by an epitaxial process, wherein the thickness of the epitaxial layer 102 may be 4 μm.

[0045] In this embodiment, the material of the epitaxial layer 102 may be single crystal silicon. Figure 2 , a dielectric layer 104 is formed on the epitaxial layer 102 .

[0046] The dielectric layer 104 provides a spatial location for forming a first alignment structure and can achieve electrical isolation between adjacent devices.

[0047] In this embodiment, an atomic layer deposition (ALD) process may be used to form the dielectric layer 104 on the epitaxial layer 102. The thickness uniformity of the dielectric layer 104 may be improved through multiple atomic layer deposition cycles.

[0048] In some other embodiments, other deposition processes (such as chemical vapor deposition processes) may be used to form a dielectric layer on the epitaxial layer.

[0049] In this embodiment, the thickness of the dielectric layer 104 should not be too large or too small. If the thickness of the dielectric layer 104 is too large, the area of ​​the power device will increase, thereby increasing power consumption; if the thickness of the dielectric layer 104 is too small, when the detection light is used to detect the first alignment structure, the optical path of the detection light becomes longer, which may easily lead to the failure to detect the first alignment structure or the detection signal is weak when the first alignment structure is detected. Based on this, in this embodiment, the thickness of the dielectric layer 104 is 0.5μm to 0.7μm.

[0050] In one specific embodiment, the thickness of the dielectric layer 104 is 0.6 μm.

[0051] In this embodiment, the material of the dielectric layer 104 may be silicon doped with B / P. In some other examples, the material of the dielectric layer 104 may be other insulating materials such as silicon nitride and silicon oxide.

[0052] See also Figure 3 and Figure 4 , a first alignment structure 106 is formed in the dielectric layer 104 and contacts the top of the epitaxial layer 102 .

[0053] The first alignment structure 106 may be used as an alignment mark to determine the overlay accuracy between different film layers.

[0054] In this embodiment, the step of forming a first alignment structure 106 in the dielectric layer 104 and contacting the top of the epitaxial layer 102 includes:

[0055] See also Figure 3 , a trench G1 exposing the epitaxial layer 102 is formed in the dielectric layer 104 .

[0056] In this embodiment, an etching process (dry etching process and / or wet etching process) is used to remove a portion of the dielectric layer 104 until the top of the epitaxial layer 102 is exposed, and a trench G1 is formed in the dielectric layer 104 .

[0057] See also Figure 4 , a first alignment structure 106 contacting the top of the epitaxial layer 102 is formed in the trench G1.

[0058] Specifically, the step of forming a first alignment structure 106 in contact with the top of the epitaxial layer 102 in the groove G1 includes: forming an alignment mark material layer (not shown) filling the groove G1 on the top of the dielectric layer 104; performing a planarization process to remove the alignment mark material layer above the top of the dielectric layer 104, and retaining the alignment mark material layer in the groove G1 as the first alignment structure 106.

[0059] In this embodiment, after the planarization process is performed, the top of the first alignment structure 106 may be trimmed by ion beam etching or the like to reduce the roughness of the top of the first alignment structure 106 .

[0060] In this embodiment, the width w of the first alignment structure 106 should not be too large or too small. If the width w of the first alignment structure 106 is too large, the device power consumption will increase; if the width w of the first alignment structure 106 is too small, it means that the alignment area is too small, and when the first alignment structure 106 is detected by using detection light, it is difficult to detect the first alignment structure 106 or the detection signal is weak when the first alignment structure 106 is detected. Based on this, in this embodiment, the width w of the first alignment structure 106 is 1μm to 8.8μm.

[0061] In a specific embodiment, the width w of the first alignment structure 106 may be 8 μm. In this embodiment, the height of the first alignment structure 106 is the same as the height of the dielectric layer 104 , and the height of the first alignment structure 106 is 0.5 μm to 0.7 μm.

[0062] In a specific embodiment, the height of the first alignment structure 106 is 0.6 μm.

[0063] In this embodiment, the material of the first alignment structure 106 includes one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

[0064] In a specific embodiment, the material of the first alignment structure 106 may include W.

[0065] It should be noted that this embodiment is described by taking the example of forming two first alignment structures 106 in the dielectric layer 104. In some other embodiments, only one first alignment structure 106 may be formed in the dielectric layer 104, and this embodiment does not limit the number of first alignment structures 106.

[0066] See also Figure 5 , a metal contact layer 108 is formed on the dielectric layer 104 .

[0067] The metal contact layer 108 determines the withstand voltage of the power device. The thicker the metal contact layer 108 is, the greater the withstand voltage of the power device is.

[0068] In this embodiment, a physical vapor deposition process may be used to form the metal contact layer 108 on the dielectric layer 104 .

[0069] In this embodiment, the thickness of the metal contact layer 108 should not be too large or too small. If the thickness of the metal contact layer 108 is too large, the thickness of the subsequently formed anti-etching layer will be too large, which will increase the optical path of the detection light, making it difficult to detect the first alignment structure when the detection light is used to detect the first alignment structure, or the detection signal is weak when the first alignment structure is detected; if the thickness of the metal contact layer 108 is too small, the withstand voltage value of the power device will be reduced. Based on this, the thickness of the metal contact layer 108 is 3μm to 5μm.

[0070] In a specific embodiment, the thickness of the metal contact layer 108 is 4 μm.

[0071] In this embodiment, the material of the metal contact layer 108 may include one or more of Ni, W, Ti, TiN, Ta, Pt, Al, Cu, Ag, Au and Co.

[0072] In a specific embodiment, the material of the metal contact layer 108 is an alloy of Al and Cu.

[0073] See also Figure 6 and Figure 7 , a first opening K1 is formed in the metal contact layer 108 to expose the first alignment structure 106 .

[0074] The first opening K1 provides a process space for forming an etch stop layer.

[0075] In this embodiment, the step of forming the first opening K1 in the metal contact layer 108 to expose the first alignment structure 106 includes:

[0076] See also Figure 6 A mask structure 110 having a first pattern opening P1 is formed on the metal contact layer 108 , and along a normal direction of the surface of the substrate 100 , the first pattern opening P1 is arranged opposite to the first alignment structure 106 .

[0077] In this embodiment, the material of the mask structure 110 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon boron nitride.

[0078] In this embodiment, the mask structure 110 is a single-layer structure. In some other examples, the mask structure 110 may also be a stacked-layer structure.

[0079] See also Figure 7 , along the first pattern opening P1 , the metal contact layer 108 exposed by the first pattern opening P1 is removed, and a first opening K1 exposing the first alignment structure 106 is formed in the metal contact layer 108 .

[0080] Specifically, the mask structure 110 is used as a mask to perform photolithography and etching processes to remove the metal contact layer 108 exposed by the first pattern opening P1 until the first alignment structure 106 is exposed, so as to form a first opening K1.

[0081] The width of the first opening K1 is related to the width of the first alignment structure 106 . For example, the greater the width of the first alignment structure 106 , the greater the width of the first opening K1 .

[0082] In this embodiment, the process of removing the metal contact layer 108 exposed by the first pattern opening P1 includes: a dry etching process.

[0083] More specifically, the parameters of the dry etching process include: pressure of 7mTorr to 9mTorr, power of 1000wT to 1200wT, RF energy of 335wB to 410wB, etching gases of CL2 and BCL3, wherein the flow rate of CL2 is 220sccm to 270sccm, and the flow rate of BCL3 is 125sccm to 150sccm.

[0084] In this embodiment, the parameters of the dry etching process may further include processing time. For example, the processing time may be 8 minutes to 12 minutes.

[0085] In this embodiment, in the step of forming the first pattern opening P1, the first pattern opening P1 may also expose a portion of the top of the dielectric layer 104. That is, the width of the first pattern opening P1 is greater than the width of the first alignment structure 106.

[0086] In this embodiment, see Figure 7 After forming the first opening K1 , the mask structure 110 is removed.

[0087] In a specific implementation, the mask structure 110 is removed by an ashing process.

[0088] See also Figure 8 , forming an anti-etching layer 120 filling the first opening K1 and covering the top of the metal contact layer.

[0089] The anti-etching layer 120 is used to protect the surface of the channel structure layer 108, and the transmittance of the anti-etching layer 120 to the detection light is greater than the transmittance of the metal contact layer 108 to the detection light, which can reduce the blocking of the metal contact layer 108 to the detection light, so that most of the detection light can be transmitted to the first alignment structure 106. In this way, when most of the detection light is irradiated to the first alignment structure 106, the intensity of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0090] In this embodiment, the anti-etching layer 120 filling the first opening K1 and covering the top of the metal contact layer is formed by a deposition process (eg, a chemical vapor deposition process).

[0091] In this embodiment, the thickness Th of the anti-etching layer 120 should not be too large or too small. If the thickness Th of the anti-etching layer 120 is too large, it will take too long to open the anti-etching layer 120 when performing the subsequent photolithography process; if the thickness Th of the anti-etching layer 120 is too small, when performing the etching process in other areas above the substrate 100, the anti-etching layer 120 on the top of the metal contact layer 108 may be consumed, and then a part of the thickness of the metal contact layer 108 will be etched, reducing the electrical performance of the power device. Based on this, in this embodiment, the thickness Th of the anti-etching layer 120 is 4μm to 6μm.

[0092] In a specific embodiment, the thickness Th of the anti-etching layer 120 is 5 μm. In this embodiment, the anti-etching layer 120 includes: a first portion 121 covering the top of the metal contact layer, and a second portion 122 filling the first opening K1 and contacting the first alignment structure 106 .

[0093] In this embodiment, the material of the anti-etching layer 120 is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0094] In a specific embodiment, the anti-etching layer 120 is photoresist.

[0095] In the actual alignment process, the inventors further discovered that the more alignment structures are provided and the more they are distributed in different film layers, the better the alignment effect.

[0096] Based on this, continue to see Figure 6 and Figure 7 In the step of forming a first opening K1 in the metal contact layer 108 to expose the first alignment structure 106 , the method for forming a power device further includes: forming a second opening K2 in the metal contact layer 108 on one side of the first opening K1 to expose the top of the dielectric layer 104 .

[0097] The second opening K2 provides a process space for forming a second alignment mark.

[0098] In this embodiment, the formation process of the second opening K2 can refer to the description of the first opening K1, except that: the width of the second opening K2 is smaller than that of the first opening K1, that is, the width of the second graphic opening P2 is smaller than that of the first graphic opening P1.

[0099] In this embodiment, see Figure 8In the step of forming the anti-etching layer 120 filling the first opening K1 and covering the top of the metal contact layer 108 , the anti-etching layer 120 also fills the second opening K2 .

[0100] The method of forming the anti-etching layer 120 in the second opening K2 may refer to the above example.

[0101] In this embodiment, the anti-etching layer 120 located in the second opening K2 serves as a second alignment structure. Figure 8 The third portion 123 located in the metal contact layer 108 and in contact with the top of the dielectric layer 104 may serve as a second alignment structure.

[0102] It should be noted that, first, when forming the second opening K2, the second opening K2 is multiple (for example Figure 7 The two second openings K2 shown in the diagram) can subsequently form a dense pattern of light and dark in the metal contact layer 108, which is convenient for accurately finding the position of the alignment mark; secondly, because the metal contact layer 108 is thick, after etching, the sidewall smoothness of the second opening K2 formed is poor, which makes the topography of the formed second alignment structure poor and the detection effect is poor. Therefore, if the detection signal directly formed by the second alignment structure is used, it is easy to cause rework of a large number of wafers, so the first alignment structure is preferably used as the alignment mark in the embodiment of the present invention.

[0103] In the present embodiment, before the anti-etching layer 120 is formed to fill the first opening K1 and cover the top of the metal contact layer 108, the top of the metal contact layer 108 is exposed to the air. When the metal contact layer 108 is in a humid environment or an environment filled with corrosive gases, the flatness of the top surface of the metal contact layer 108 is easily destroyed, thereby reducing the performance of the power device.

[0104] Based on this, see Figure 8 Before forming the anti-etching layer 120 filling the first opening K1 and covering the top of the metal contact layer 108, the method for forming the power device further includes:

[0105] A protection layer 112 is formed on the metal contact layer 108 and in the first opening K1 , and a top height of the protection layer 112 in the first opening K1 is lower than a top height of the first opening K1 .

[0106] In this embodiment, a chemical vapor deposition process is used to form a protection layer 112 on the metal contact layer 108 and in the first opening K1 .

[0107] In this embodiment, the thickness of the protective layer 112 should not be too large or too small. If the thickness of the protective layer 112 is too large, the power consumption of the power device will increase; if the thickness of the protective layer 112 is too small, there may be a risk that the surface of the metal contact layer 108 will be exposed to the air again due to the consumption of the protective layer 112 in the subsequent process. Based on this, in this embodiment, the thickness of the protective layer 112 is 0.8 μm to 1 μm.

[0108] In a specific embodiment, the thickness of the protection layer 112 is 0.9 μm.

[0109] In the present embodiment, the material of the protection layer 112 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride oxycarbon, boron nitride and boron carbonitride.

[0110] In a specific embodiment, the material of the protection layer 112 is silicon nitride.

[0111] See next Figure 8 In the step of forming the anti-etching layer 120 filling the first opening K1 and covering the metal contact layer 108 , the anti-etching layer 120 also covers the top and part of the sidewall of the protection layer 112 .

[0112] For example, the first portion 121 and the third portion 123 of the anti-etching layer 120 cover the top of the protection layer 112 , and the second portion 122 of the anti-etching layer 120 covers the sidewall of the protection layer 112 .

[0113] Therefore, the method for forming the power device in the above example can reduce the corrected residual index (ROPI) of the power device. For example, the ROPI value in this embodiment is less than 40nm, while the ROPI value in the existing solution is close to 150nm. It can be seen that the method in the embodiment of the present invention can significantly improve the alignment accuracy.

[0114] The present invention also provides a power device, see Fig. 9 The schematic diagram of the structure corresponding to an embodiment of the power device of the present invention is shown in FIG. Fig. 9 As shown, the power device includes: a substrate 200 having an epitaxial layer 202 thereon; a dielectric layer 204 located on the epitaxial layer 202; a first alignment structure 206 located in the dielectric layer 204 and in contact with the top of the epitaxial layer 202; a metal contact layer 208 located on the dielectric layer 204; and an anti-etching layer 220, including a first portion 221 located on the metal contact layer 208, and a second portion 222 located in the metal contact layer 208 and in contact with the top of the first alignment structure 206.

[0115] In this embodiment, the substrate 200 can provide a process operation basis for the formation process of the power device, wherein the power device can include a longitudinal double diffused metal oxide semiconductor structure LDMOS and / or a vertical double diffused metal oxide semiconductor structure VDMOS.

[0116] In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0117] In some embodiments, the base may further include a substrate, a plurality of discrete fins located above the substrate, and an isolation structure located on the substrate where the fins are exposed. The isolation structure may cover a portion of the sidewalls of the fins, and the top of the isolation structure is lower than the top of the fins.

[0118] In this embodiment, the isolation structure serves to electrically isolate adjacent fins.

[0119] In some embodiments, the material of the isolation structure may be an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.

[0120] In this embodiment, the material of the isolation structure may be silicon oxide.

[0121] The epitaxial layer 202 serves to improve the withstand voltage of the power device. The thicker the epitaxial layer 202 is, the greater the withstand voltage of the power device is. For example, the thickness of the epitaxial layer 202 may be 4 μm.

[0122] In this embodiment, the material of the epitaxial layer 202 may be single crystal silicon.

[0123] The dielectric layer 204 provides a location space for forming a first alignment structure and can achieve electrical isolation between adjacent devices.

[0124] In this embodiment, the thickness of the dielectric layer 204 should not be too large or too small. If the thickness of the dielectric layer 204 is too large, the area of ​​the power device will increase, thereby increasing power consumption; if the thickness of the dielectric layer 204 is too small, when the detection light is used to detect the first alignment structure 206, the optical path of the detection light becomes longer, which may easily lead to the failure to detect the first alignment structure 206 or the detection signal is weak when the first alignment structure 206 is detected. Based on this, in this embodiment, the thickness of the dielectric layer 204 is 0.5μm to 0.7μm.

[0125] In one specific embodiment, the thickness of the dielectric layer 204 is 0.6 μm.

[0126] In this embodiment, the material of the dielectric layer 204 may be silicon doped with B / P. In some other examples, the material of the dielectric layer 204 may be other insulating materials such as silicon nitride and silicon oxide.

[0127] The first alignment structure 206 may be used as an alignment mark to determine the overlay accuracy between different film layers.

[0128] In this embodiment, the width w of the first alignment structure 206 should not be too large or too small. If the width w of the first alignment structure 206 is too large, the device power consumption will increase; if the width w of the first alignment structure 206 is too small, it means that the alignment area is too small, and when the first alignment structure 206 is detected by using detection light, it is difficult to detect the first alignment structure 206 or the detection signal is weak when the first alignment structure 206 is detected. Based on this, in this embodiment, the width w of the first alignment structure 206 is 1μm to 8.8μm.

[0129] In a specific embodiment, the width w of the first alignment structure 206 may be 8 μm.

[0130] In this embodiment, the height of the first alignment structure 206 is the same as the height of the dielectric layer 204 , and the height of the first alignment structure 206 is 0.5 μm to 0.7 μm.

[0131] In a specific embodiment, the height of the first alignment structure 206 is 0.6 μm.

[0132] In this embodiment, the material of the first alignment structure 206 includes one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

[0133] In a specific embodiment, the material of the first alignment structure 206 may include W.

[0134] It should be noted that this embodiment is described by taking the example of forming two first alignment structures 206 in the dielectric layer 204. In some other embodiments, only one first alignment structure 206 may be formed in the dielectric layer 204, and this embodiment does not limit the number of first alignment structures 206.

[0135] The metal contact layer 208 determines the withstand voltage of the power device. The thicker the metal contact layer 208 is, the greater the withstand voltage of the power device is.

[0136] In this embodiment, the thickness of the metal contact layer 208 should not be too large or too small. If the thickness of the metal contact layer 208 is too large, the thickness of the anti-etching layer 220 will be too large, which will increase the optical path of the detection light, making it difficult to detect the first alignment structure 206 when the detection light is used to detect the first alignment structure 206, or the detection signal is weak when the first alignment structure 206 is detected; if the thickness of the metal contact layer 208 is too small, the withstand voltage value of the power device will be reduced. Based on this, the thickness of the metal contact layer 208 is 3μm to 5μm.

[0137] In a specific embodiment, the thickness of the metal contact layer 208 is 4 μm.

[0138] In this embodiment, the material of the metal contact layer 208 may include one or more of Ni, W, Ti, TiN, Ta, Pt, Al, Cu, Ag, Au and Co.

[0139] In a specific embodiment, the material of the metal contact layer 208 is an alloy of Al and Cu.

[0140] The anti-etching layer 220 is used to protect the surface of the channel structure layer 208, and the transmittance of the anti-etching layer 220 to the detection light is greater than the transmittance of the metal contact layer 208 to the detection light, which can reduce the blocking of the metal contact layer 208 to the detection light, so that most of the detection light can be transmitted to the first alignment structure 206. In this way, when most of the detection light is irradiated to the first alignment structure, the intensity of the alignment signal can be improved, thereby improving the detection accuracy of the alignment structure.

[0141] In this embodiment, the thickness Th of the anti-etching layer 220 is 4 μm to 6 μm. In a specific embodiment, the thickness Th of the anti-etching layer 220 is 5 μm.

[0142] In this embodiment, the material of the anti-etching layer 220 is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

[0143] In a specific embodiment, the anti-etching layer 220 is photoresist.

[0144] In the actual alignment process, the inventors further discovered that the more alignment structures are provided and the more they are distributed in different film layers, the better the alignment effect.

[0145] Based on this, continue to see Fig. 9 The anti-etching layer 220 further includes a third portion 222 located in the metal contact layer 208 and in contact with the top of the dielectric layer 207 .

[0146] In this embodiment, the third portion 222 may serve as a second alignment structure.

[0147] In this embodiment, see Fig. 9 The power device further includes: a protection layer 212 located between the first portion 221 and the metal contact layer 208 , and between the second portion 222 and the first alignment structure 206 .

[0148] The protection layer 212 is used to protect the metal contact layer 208 to prevent or reduce the probability of the top of the metal contact layer 208 being damaged when the power device is in a humid environment or an environment full of corrosive gases.

[0149] In this embodiment, the thickness of the protective layer 212 should not be too large or too small. If the thickness of the metal contact layer 212 is too large, the power consumption of the power device will increase; if the thickness of the protective layer 212 is too small, it may not play the role of protecting the surface of the metal contact layer 208. Based on this, in this embodiment, the thickness of the protective layer 212 is 0.8 μm to 1 μm.

[0150] In a specific embodiment, the thickness of the protection layer 212 is 0.9 μm.

[0151] In the present embodiment, the material of the protection layer 212 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride and boron carbonitride.

[0152] In a specific embodiment, the material of the protection layer 212 is silicon nitride.

[0153] In this embodiment, when the power device includes a second alignment mark, the protection layer 212 is further located between the second alignment mark and the dielectric layer 204 .

[0154] It should be noted that the power device described in this embodiment can be formed by the formation method described in the previous embodiment, or by other formation methods. For the specific description of the power device described in this embodiment, reference can be made to the corresponding description in the previous embodiment, and this embodiment will not be repeated here.

[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a power device, characterized in that: include: providing a substrate having an epitaxial layer thereon; forming a dielectric layer on the epitaxial layer; forming a first alignment structure in the dielectric layer in contact with a top portion of the epitaxial layer; forming a metal contact layer on the dielectric layer; forming a first opening in the metal contact layer exposing the first alignment structure; An anti-etching layer is formed to fill the first opening and cover the top of the metal contact layer, wherein the transmittance of the anti-etching layer to the detection light is greater than the transmittance of the metal contact layer to the detection light.

2. The method for forming a power device according to claim 1, characterized in that: The first alignment structure has a width of 1 μm to 8.8 μm and a height of 0.5 μm to 0.7 μm.

3. The method for forming a power device according to claim 1 or 2, characterized in that: The material of the first alignment structure includes one or more of Ni, W, Ti, TiN, Ta, Pt and Co.

4. The method for forming a power device according to claim 1, characterized in that: The thickness of the metal contact layer is 3 μm to 5 μm.

5. The method for forming a power device according to claim 1, characterized in that: The step of forming a first opening in the metal contact layer to expose the first alignment structure comprises: Forming a mask structure having a first graphic opening on the metal contact layer, wherein the first graphic opening is arranged opposite to the first alignment structure along a normal direction of the substrate surface; Along the first graphic opening, removing the metal contact layer exposed by the first graphic opening, and forming a first opening in the metal contact layer to expose the first alignment structure; After forming the first opening, the mask structure is removed.

6. The method for forming a power device according to claim 5, characterized in that: The process of removing the metal contact layer exposed by the first pattern opening includes: a dry etching process; The parameters of the dry etching process include: pressure of 7mTorr to 9mTorr, power of 1000wT to 1200wT, RF energy of 335wB to 410wB, etching gases of CL2 and BCL3, wherein the flow rate of CL2 is 220sccm to 270sccm, and the flow rate of BCL3 is 125sccm to 150sccm.

7. The method for forming a power device according to claim 1 or 5, characterized in that: The step of forming a first opening in the metal contact layer to expose the first alignment structure further includes: forming a second opening in the metal contact layer on one side of the first opening to expose the top of the dielectric layer; In the step of forming an anti-etching layer filling the first opening and covering the top of the metal contact layer, the anti-etching layer also fills the second opening, wherein the anti-etching layer located in the second opening serves as a second alignment structure.

8. The method for forming a power device according to claim 1, characterized in that: The material of the anti-etching layer is one of photoresist, Si-ARC material, DARC material, BARC material, DUO material or ODL material.

9. The method for forming a power device according to claim 1, characterized in that: Before forming the anti-etching layer filling the first opening and covering the top of the metal contact layer, the method further includes: forming a protective layer on the metal contact layer and in the first opening, wherein a top height of the protective layer in the first opening is lower than a top height of the first opening; In the step of forming an anti-etching layer filling the first opening and covering the metal contact layer, the anti-etching layer also covers the top and a portion of the sidewall of the protection layer.

10. A power device, characterized in that: include: a substrate having an epitaxial layer thereon; a dielectric layer, located on the epitaxial layer; a first alignment structure located in the dielectric layer and in contact with a top portion of the epitaxial layer; a metal contact layer, located on the dielectric layer; The anti-etching layer includes a first portion located on the metal contact layer and a second portion located in the metal contact layer and in contact with the top of the first alignment structure.

11. The power device according to claim 10, characterized in that: Also includes: A protection layer is located between the first portion and the metal contact layer, and between the second portion and the first alignment structure.

12. The power device according to claim 10, characterized in that: The anti-etching layer further includes a third portion located in the metal contact layer and in contact with the top of the dielectric layer, wherein the third portion serves as a second alignment mark.

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