Low-temperature bonding method for chips

Abstract

The present invention relates to the field of semiconductor technology. Specifically, it relates to a low-temperature bonding method for a chip, which includes: preparing an upper chip with micro-bumps, where the micro-bumps include a low-temperature material containing Sn; preparing a lower chip with copper pillars and reducing the roughness of the bonding surface of the copper pillars; opposing the bonding surfaces of the micro-bumps and the copper pillars, and performing bonding in a vacuum environment at a temperature of 50-150 °C, a pressure of 10-40 MPa, and a pulsed voltage of 2-6 V. The low-temperature bonding method for the chip of the present invention can achieve low-temperature bonding, improve the stability of bonding, reduce the thermal damage caused by bonding, and improve the warping problem of the substrates of the upper chip and the lower chip after bonding.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly, to a low-temperature bonding method for chips. Background Art

[0002] With the rapid development of the semiconductor industry, the electronic packaging of integrated circuits is rapidly moving towards miniaturization, high performance, high density, and multi-chip. The development of miniaturized and multifunctional electronic products makes it easy to have problems of thermal damage and substrate warping during the packaging and assembly of devices.

[0003] In view of this, the present invention is specifically proposed. Summary of the Invention

[0004] The purpose of the present invention is to provide a low-temperature bonding method for chips, wherein the microbumps of the upper chip include a low-temperature material containing Sn, and the bonding surface of the copper pillar of the lower chip is roughened. After the microbumps of the upper chip and the bonding surface of the copper pillar of the lower chip are opposed, a spark plasma sintering method is used for bonding to achieve the purpose of bonding at low temperature, improve the stability of bonding, reduce the thermal damage caused by bonding, and improve the warping problem of the substrates of the upper chip and the lower chip after bonding.

[0005] The embodiments of the present invention are implemented as follows:

[0006] The present invention provides a low-temperature bonding method for chips, including:

[0007] Preparing an upper chip with microbumps, the microbumps including a low-temperature material containing Sn;

[0008] Preparing a lower chip with copper pillars and reducing the roughness of the bonding surface of the copper pillars;

[0009] Opposing the microbumps and the bonding surface of the copper pillars, and performing bonding at a temperature of 50 - 150°C, a pressure of 10 - 40 MPa, and a pulsed voltage of 2 - 6 V in a vacuum environment.

[0010] In an alternative embodiment, the vacuum degree of the vacuum environment is less than 10 Pa.

[0011] In an alternative embodiment, the bonding step specifically includes: heating the temperature to 50 - 150°C at a heating rate of 45 - 50°C / min for bonding.

[0012] In an alternative embodiment, the bonding time is 30 - 60 min.

[0013] In an alternative embodiment, the roughness of the bonding surface of the copper pillars is less than 0.5 nm, and the flatness of the bonding surface of the copper pillars is less than 5%.

[0014] In an alternative embodiment, the cooling after bonding is furnace cooling.

[0015] In an alternative embodiment, the low-temperature Sn-containing materials include: Sn-In materials, Sn-Bi materials, and Sn-Zn materials.

[0016] In an alternative embodiment, the bonding step specifically includes: separately assembling the upper chip and the lower chip on a bonding die, and then using the bonding die to make the bonding surfaces of the microbumps and the copper pillars face each other.

[0017] In an alternative embodiment, the bonding die includes two clamping members, each clamping member is provided with a recess, the two clamping members are spliced with each other, and the recesses of the two clamping members are spliced into a groove for placing the upper chip or the lower chip.

[0018] In an alternative embodiment, the flatness of the bottom of the groove is less than 1 nm, and the depth of the groove is less than the thickness of the upper chip and less than the thickness of the lower chip.

[0019] The beneficial effects of the low-temperature bonding method of the chip according to the embodiment of the present invention include: in the low-temperature bonding method of the chip provided by the embodiment of the present invention, microbumps including low-temperature Sn-containing materials are prepared on the upper chip. The low-temperature Sn-containing materials have a relatively low melting point, which is beneficial to reducing the bonding temperature required in subsequent bonding; the bonding surface of the copper pillar of the lower chip is roughened to reduce the roughness of the bonding surface, which is beneficial to improving the strength and stability after bonding. In particular, it helps to ensure the bonding stability and strength even when bonding at a relatively low temperature; the spark plasma sintering method is used during bonding, and a bonding pressure and a pulsed current are applied simultaneously, so as to reduce the temperature during bonding and ensure stable and reliable low-temperature bonding. In this way, the thermal damage caused by bonding can be effectively reduced through low-temperature bonding, and the warping problems of the substrates of the upper chip and the lower chip after bonding can be improved. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1 It is a cross-sectional view of the upper chip in the embodiment of the present invention;

[0022] Figure 2 It is a cross-sectional view of the lower chip in the embodiment of the present invention;

[0023] Figure 3Schematic diagram when the upper chip and the lower chip are bonded in the embodiment of the present invention;

[0024] Figure 4 Schematic diagram of the structure of the bonding die in the embodiment of the present invention;

[0025] Figure 5 Schematic diagram of the structure of the clamping member in the embodiment of the present invention.

[0026] Icons: 010 - bonding die; 100 - clamping member; 110 - base; 120 - indenter; 121 - depression; 122 - groove; 123 - blocking member; 200 - upper chip; 210 - micro bump; 300 - lower chip; 310 - copper pillar. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Those not specified in the embodiments are carried out according to conventional conditions or conditions recommended by the manufacturer. Those reagents or instruments not specified by the manufacturer can be obtained as conventional products through commercial purchase.

[0028] Please refer to Figure 1 、 Figure 2 and Figure 3 , the present disclosure provides a low-temperature bonding method for chips, which includes:

[0029] Prepare an upper chip 200 with micro bumps 210, and the micro bumps 210 include a low-temperature material containing Sn;

[0030] Prepare a lower chip 300 with copper pillars 310, and reduce the roughness of the bonding surface of the copper pillars 310;

[0031] Oppose the bonding surfaces of the micro bumps 210 and the copper pillars 310, and in a vacuum environment, at a temperature of 50 - 150 °C (for example: 50 °C, 70 °C, 90 °C, 110 °C, 130 °C, 150 °C, etc., not specifically limited here), a pressure of 10 - 40 MPa (for example: 10 MPa, 20 MPa, 30 MPa, 40 MPa, etc., not specifically limited here), and a pulsed voltage of 2 - 6 V (for example: 2 V, 3 V, 4 V, 5 V, 6 V, etc., not specifically limited here), perform bonding.

[0032] On the upper chip 200, micro-bumps 210 including a low-temperature Sn-containing material are fabricated. The low-temperature Sn-containing material has a relatively low melting point, which is beneficial to reducing the bonding temperature required in subsequent bonding. The bonding surface of the copper pillars 310 on the lower chip 300 is roughened to reduce the roughness of the bonding surface, which is beneficial to improving the strength and stability after bonding. In particular, it helps to ensure the stability and strength of bonding even when bonding at a relatively low temperature. During bonding, a spark plasma sintering method is adopted, and bonding pressure and pulsed current are applied simultaneously to facilitate reducing the temperature during bonding and ensuring stable and reliable low-temperature bonding. In this way, the thermal damage caused by bonding can be effectively reduced through low-temperature bonding, and the warping problems of the substrates of the upper chip 200 and the lower chip 300 after bonding can be improved.

[0033] It should be noted that the spark plasma sintering uses pulsed current, which can generate discharge plasma instantaneously when energized, causing Joule heat to be generated inside the sintered body and activating the surface, that is, it can activate the surfaces of the micro-bumps 210 and the copper pillars 310 that need to be bonded, so that reliable bonding can be carried out between the bonding surfaces of the micro-bumps 210 and the copper pillars 310, thus playing a role in reducing the bonding temperature, that is, it is not necessary to activate the bonding surfaces of the micro-bumps 210 and the copper pillars 310 by high temperature. On the other hand, the pulsed current can promote atomic diffusion, making the bonding strength more stable, that is, the pulsed current can make the atoms of the micro-bumps 210 and the atoms of the copper pillars 310 diffuse with each other to improve the bonding strength and stability between the two.

[0034] It should also be noted that the low-temperature bonding method of the chips in the present disclosure can further ensure the stability of low-temperature bonding and fully improve the problems of heat loss caused by bonding and warping of the chip substrates by combining the low-temperature material of the micro-bumps 210 and the spark plasma sintering method.

[0035] Optionally, the bonding can be carried out in a vacuum furnace. Among them, the vacuum degree of the vacuum environment is less than 10 Pa, for example: 9.5 Pa, 9 Pa, 8.5 Pa, 8 Pa, etc., and no specific limitation is made here. Optimizing the vacuum degree of the vacuum furnace can, on the one hand, ensure stable and reliable bonding at a relatively low temperature, and on the other hand, effectively improve the problems of damage and warping of the substrates of the upper chip 200 and the lower chip 300.

[0036] Optionally, during bonding, the temperature can be raised from room temperature to 50 - 150°C at a heating rate of 45 - 50°C / min (for example: 45°C / min, 46°C / min, 47°C / min, 48°C / min, 49°C / min, 50°C / min, etc., which are not specifically defined here) for bonding. Optimizing the heating rate during bonding can, on the one hand, play a certain preheating role during bonding, which is beneficial to evenly activating the atoms on the bonding surfaces of the microbumps 210 and the copper pillars 310, so as to ensure the uniform diffusion of atoms during bonding, and further ensure the stability and strength of the bond at low temperature. On the other hand, it ensures the controllability of the bonding temperature, improves the thermal damage caused by the rapid increase in the bonding temperature, and improves the warping problem of the substrates of the upper chip 200 and the lower chip 300.

[0037] Optionally, the bonding time is 30 - 60 min, for example: 30 min, 40 min, 50 min, 60 min, etc., which are not specifically defined here. Optimizing the bonding time can ensure the strength and stability of the bond, and improve problems such as chip damage and warping caused by bonding.

[0038] Optionally, after bonding in a vacuum furnace, the cooling method is to cool with the furnace to room temperature. In this way, the cooling rate can be slowed down. On the one hand, the residual temperature in the furnace can be used to further ensure the atomic diffusion between the bonding surfaces of the microbumps 210 and the copper pillars 310, so as to improve the strength and stability of the bond. On the other hand, it can avoid the problem of large stress generated by the large temperature difference of the bonded chips in a short time, and further improve problems such as cracks appearing at the bonding site, and ensure the strength and stability of the bond.

[0039] Optionally, the roughness of the bonding surface of the copper pillar 310 is less than 0.5 nm (for example: 0.45 nm, 0.4 nm, 0.35 nm, 0.3 nm, etc., which are not specifically defined here), and the flatness of the bonding surface of the copper pillar 310 is less than 5% (for example: 4.5%, 4%, 3.5%, 3%, etc., which are not specifically defined here). Reducing the roughness of the bonding surface of the copper pillar 310 can, on the one hand, make the atomic diffusion fast through the reduction of roughness, so as to improve the stability of the bond. On the other hand, it can also improve the problem of oxidation of the bonding surface, improve the stability of the bond, and ensure the bond strength, that is, avoid the reduction of the stability and strength of the bond caused by the oxidation of the bonding surface.

[0040] The preparation method of the lower chip 300 with the copper pillar 310 is similar to the related technology. For example, the lower chip 300 with the copper pillar 310 is obtained through processes such as sputtering, coating, exposure, development, dry stripping, electroplating, stripping, etching, reflow thinning, and dicing. The specific processes are not elaborated here.

[0041] The method for preprocessing the bonding surface of the copper pillar 310 is similar to the related art, for example: chemical mechanical polishing (CMP), plasma surface activation, surface wet chemical treatment, self-assembled molecular layer, etc. The specific process will not be elaborated here.

[0042] It should be noted that after reducing the roughness of the copper pillar 310, the lower chip 300 can also be purged and cleaned to make the surface of the lower chip 300 and its copper pillar 310 free of particles with a particle size of about 1 μm, improve the cleanliness, and solve the problem that the bonding stability is reduced due to the presence of particle impurities on the surface of the copper pillar 310.

[0043] Optionally, the method for fabricating the upper chip 200 with microbumps 210 is similar to the related art. For example, the upper chip 200 with microbumps 210 is fabricated through processes such as sputtering, photoresist coating, exposure, development, dry photoresist stripping, electroplating, photoresist stripping, etching, reflow thinning, and dicing. The specific processes will not be elaborated here.

[0044] Optionally, the low-temperature materials containing Sn include: Sn-In materials, Sn-Bi materials, and Sn-Zn materials; these materials have a melting point below 200°C, good wettability, good mechanical properties, and are not easily oxidized. By selecting the materials, the bonding strength and stability between the microbumps 210 and the copper pillar 310 can also be improved.

[0045] Furthermore, the Sn-In material can refer to Sn-52In with 52% indium by mass, etc., which is not specifically limited here; the Sn-Bi material can refer to Sn-58Bi with 58% bismuth by mass, etc., which is not specifically limited here; the Sn-Zn material can refer to Sn-8.9Zn with 8.9% zinc by mass, etc., which is not specifically limited here.

[0046] Please refer to Figure 3 , optionally, during bonding, the upper chip 200 and the lower chip 300 are respectively assembled on the bonding die 010, and then the bonding die 010 is used to make the bonding surfaces of the microbumps 210 and the copper pillar 310 face each other, and the bonding die 010 provides the pressure during bonding, that is, the upper chip 200 is assembled on one bonding die 010, and the microbumps 210 are exposed, the lower chip 300 is assembled on another bonding die 010, and the copper pillar 310 is exposed, the two bonding dies 010 are opposed to align the microbumps 210 and the copper pillar 310, and the bonding die 010 is used to apply pressure to tightly press the microbumps 210 and the copper pillar 310 together.

[0047] Furthermore, please refer to Figure 4, the bonding die 010 includes two clamping members 100. Each clamping member 100 is provided with a recess 121. The two clamping members 100 are spliced together, and the recesses 121 of the two clamping members 100 are spliced to form a groove 122. The groove 122 is used to place the upper chip 200 or the lower chip 300. With such a setting, the stability and operability of assembling the chip on the bonding die 010 can be ensured.

[0048] Optionally, please refer to Figure 4 and Figure 5 , the groove 122 formed by splicing the two clamping members 100 is located in the middle of the splicing structure of the two clamping members 100. In this way, the accuracy of alignment between the microbumps 210 provided on the upper chip 200 and the copper pillars 310 provided on the lower chip 300 can be ensured by using two bonding dies 010.

[0049] Optionally, the clamping member 100 includes a base 110 and a press head 120 detachably assembled to the base 110. The press head 120 is provided with a recess 121; the detachable connection method between the press head 120 and the base 110 includes but is not limited to threaded connection, snap connection, plug connection, etc. By configuring the press head 120 to be detachably connected to the base 110, different press heads 120 can be replaced as needed. For example: replace the press head 120 with different recess 121 sizes according to the size of the chip, or replace a new press head 120 when the press head 120 is damaged.

[0050] Furthermore, the press head 120 is further connected with a blocking member 123. The blocking member 123 is located at the recess 121 to block the chip placed in the groove 122 formed by splicing the two press heads 120 from detaching from the groove 122. That is, when the press heads 120 of the two clamping members 100 are spliced, the blocking member 123 is located at the notch of the groove 122 to block the chip placed in the groove 122 from detaching from the groove 122.

[0051] Optionally, the flatness of the bottom of the groove 122 is less than 1 nm, and the depth of the groove 122 is less than the thickness of the upper chip 200 and less than the thickness of the lower chip 300. By optimizing the flatness, it can be ensured that the upper chip 200 and the lower chip 300 are parallel during the bonding process, and the yield of bonding is improved.

[0052] The present invention will be further described in detail below in conjunction with embodiments.

[0053] Embodiment 1

[0054] Prepare an upper chip with microbumps. The microbumps are made of Sn-52In low-temperature material.

[0055] Prepare a lower chip with copper pillars. The roughness of the bonding surface of the copper pillars is 0.45 nm, and the flatness is 4.5%.

[0056] Align the bonding surfaces of the microbumps and the copper pillars; in a vacuum environment with a vacuum degree of 9 MPa, increase the temperature at a heating rate of 45 °C / min to a temperature of 50 °C, control the bonding pressure at 40 MPa, and simultaneously apply a pulsed voltage of 4 V for bonding for 50 min; after bonding, cool in the furnace.

[0057] Example 2

[0058] Fabricate an upper chip with microbumps, where the microbumps are made of Sn-58Bi low-temperature material.

[0059] Fabricate a lower chip with copper pillars, where the roughness of the bonding surface of the copper pillars is 0.40 nm and the flatness is 4.0%.

[0060] Align the bonding surfaces of the microbumps and the copper pillars; in a vacuum environment with a vacuum degree of 9.5 MPa, increase the temperature at a heating rate of 50 °C / min to a temperature of 150 °C, control the bonding pressure at 10 MPa, and simultaneously apply a pulsed voltage of 2 V for bonding for 30 min; after bonding, cool in the furnace.

[0061] Example 3

[0062] Fabricate an upper chip with microbumps, where the microbumps are made of Sn-8.9Zn low-temperature material.

[0063] Fabricate a lower chip with copper pillars, where the roughness of the bonding surface of the copper pillars is 0.42 nm and the flatness is 3%.

[0064] Align the bonding surfaces of the microbumps and the copper pillars; in a vacuum environment with a vacuum degree of 8 MPa, increase the temperature at a heating rate of 47 °C / min to a temperature of 80 °C, control the bonding pressure at 20 MPa, and simultaneously apply a pulsed voltage of 6 V for bonding for 60 min; after bonding, cool in the furnace.

[0065] Example 4

[0066] The difference between Example 4 and Example 1 is that the roughness of the bonding surface of the copper pillars is 0.1 nm, and other process parameters refer to Example 1.

[0067] Comparative Example 1

[0068] The difference between Comparative Example 1 and Example 1 is that the material of the microbumps on the upper chip is copper, and the bonding temperature is 400 °C; other process parameters refer to Example 1.

[0069] Comparative Example 2

[0070] The difference between Comparative Example 2 and Example 1 is that the bonding temperature is 160 °C; other process parameters refer to Example 1.

[0071] Comparative Example 3

[0072] The difference between Comparative Example 3 and Example 1 lies in that the pulse voltage during bonding is 1V; other process parameters refer to Example 1.

[0073] Comparative Example 4

[0074] The difference between Comparative Example 4 and Example 1 lies in that the temperature during bonding is 40°C and the pulse voltage is 8V; other process parameters refer to Example 1.

[0075] Comparative Example 5

[0076] The difference between Comparative Example 5 and Example 1 lies in that the vacuum degree during bonding is 10 Pa, the temperature during bonding is 40°C, the pressure is 5 MPa, and the pulse voltage is 8V; other process parameters refer to Example 1.

[0077] Comparative Example 6

[0078] The difference between Comparative Example 6 and Example 1 lies in that the bonding method is not spark plasma sintering, that is, the temperature, pressure, and time are controlled in the same way as in Example 1 during bonding, but no pulse current is provided; other process parameters refer to Example 1.

[0079] For the bonded chip structures provided in Examples 1 - 4 and Comparative Example 1, the substrate warpage of the upper chip 200 and the lower chip 300 was detected. The warpage detection was carried out using a wafer-level warpage tester; the detection results are shown in Table 1.

[0080] Table 1

[0081]

[0082] For the bonded chip structures provided in Examples 1 - 4 and Comparative Examples 1 - 6, the bonding strength was detected. The detection results are shown in Table 2.

[0083] Table 2

[0084]

[0085] According to the comparison of Examples 1 - 4 and Comparative Example 1 in Table 1, it can be seen that although high-temperature bonding can greatly improve the pull-out strength, the warpage increases significantly, resulting in a decrease in the qualified rate of the bonded chips.

[0086] According to the comparison of Examples 1 - 4 and Comparative Example 2 in Table 2, it can be seen that an appropriate bonding temperature can effectively improve the pull-out strength of the bonded chips. When the bonding temperature is too high, the bonding solder will melt and be extruded, resulting in a decrease in the bonding strength.

[0087] According to the comparison of Examples 1 - 4 and Comparative Example 3 in Table 2, it can be seen that using an appropriate pulse voltage can effectively improve the pull-out strength of the bonded chips.

[0088] According to Table 2, by comparing Examples 1 - 4 and Comparative Example 4, it can be seen that the bonding temperature and pulse voltage can synergistically improve the pulling strength after chip bonding.

[0089] According to Table 2, by comparing Examples 1 - 4 and Comparative Example 5, it can be seen that the vacuum degree, temperature, pressure and pulse voltage during bonding can synergistically improve the pulling strength after chip bonding.

[0090] According to Table 2, by comparing Examples 1 - 4 and Comparative Example 6, it can be seen that by using the method of spark plasma sintering, the pulling strength after chip bonding can be improved.

[0091] In summary, the low-temperature bonding method of the chip of the present invention can achieve low-temperature bonding, improve the bonding stability and pulling strength, reduce the thermal damage caused by bonding, and improve the warping problem of the substrates of the upper chip 200 and the lower chip 300 after bonding.

[0092] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, various modifications and changes can be made to the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A low temperature bonding method for a chip, characterized in that: include: Prepare an upper chip with micro-bumps, wherein the micro-bumps include a low-temperature material containing Sn, and the low-temperature material containing Sn includes: Sn-In material, Sn-Bi material and Sn-Zn material; preparing a lower chip having a copper pillar, and reducing the roughness of a bonding surface of the copper pillar; The bonding surfaces of the micro-bump and the copper pillar are placed opposite to each other, and the temperature is heated to 50-150° C. at a heating rate of 45-50° C. / min under a vacuum environment, and bonding is performed under the conditions of a pressure greater than 10 MPa and less than or equal to 40 MPa and a pulse voltage of 2-6 V; The cooling after bonding is furnace cooling.

2. The low temperature bonding method of a chip according to claim 1, characterized in that: The vacuum degree of the vacuum environment is less than 10Pa.

3. The low temperature bonding method of a chip according to claim 1, characterized in that: The bonding time is 30-60 minutes.

4. The low temperature bonding method of a chip according to claim 1, characterized in that: The roughness of the bonding surface of the copper column is less than 0.5 nm, and the flatness of the bonding surface of the copper column is less than 5%.

5. The low temperature bonding method of a chip according to claim 1, characterized in that: The bonding step specifically includes: assembling the upper chip and the lower chip on a bonding mold respectively, and then using the bonding mold to make the bonding surfaces of the micro-bumps and the copper pillars face each other.

6. The low temperature bonding method of a chip according to claim 5, characterized in that: The bonding mold includes two clamping parts, each of which is provided with a recess, and the two clamping parts are spliced ​​with each other, and the recesses of the two clamping parts are spliced ​​into a groove, and the groove is used to place the upper chip or the lower chip.

7. The low temperature bonding method of a chip according to claim 6, characterized in that: The flatness of the bottom of the groove is less than 1 nm, and the depth of the groove is less than the thickness of the upper chip and less than the thickness of the lower chip.

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