Reinforced packaging process of embedded storage chip

Abstract

The invention discloses a reinforced packaging process of an embedded storage chip, and relates to the field of chip packaging. The invention discloses a reinforcing and packaging process of an embedded storage chip. The reinforcing and packaging process comprises the following steps: S1, chip preprocessing; s2, applying a protective coating; s3, packaging layer processing; the chip pretreatment in the step S1 further comprises the following steps of plasma cleaning, ultraviolet irradiation and chemical cleaning, and the application of the protective coating in the step S2 further comprises the following steps of uniformly coating a layer of protective material after the pretreatment of the surface of the chip is completed to form a primary protective layer, and controlling the thickness of the protective coating to be 100-300nm; the surface of the chip is passivated, and a silicon nitride passivation layer is deposited on the surface of the chip by adopting a plasma enhanced chemical vapor deposition technology, so that the hardness and the corrosion resistance of the surface of the chip are enhanced, charge accumulation on the surface of the chip is reduced, and the chip is prevented from being damaged by electrostatic discharge.

Description

Technical Field

[0001] The invention belongs to the technical field of chip packaging, and in particular relates to a reinforced packaging process for an embedded storage chip. Background Art

[0002] In modern electronic devices, embedded memory chips play a vital role. They are not only the core components of data storage, but also the key nodes of data processing and information transmission. With the rapid development of science and technology, electronic devices have higher and higher performance requirements for memory chips, the storage capacity is constantly expanding, and the reading and writing speeds are continuously improving. As high-performance memory chips are miniaturized, due to their tiny size and complex usage environment, existing memory chips have a protective layer on the outside. The protective layer is relatively fragile, and memory chips are easily affected by physical damage, chemical corrosion, and multiple annular factors, which erode the chip protective layer and cause chip damage. Summary of the invention

[0003] The purpose of the present invention is to solve the problems in the prior art and to propose a reinforced packaging process for an embedded memory chip.

[0004] In order to solve the above technical problems, the basic concept of the technical solution adopted by the present invention is: A reinforcement packaging process for an embedded memory chip further includes the following steps: S1: Chip pretreatment; S2: Application of protective coating; S3: Packaging layer processing; S4: Packaging test.

[0005] Preferably, the chip pretreatment in S1 also includes the following methods: plasma cleaning, ultraviolet irradiation, and chemical cleaning.

[0006] Preferably, the application of the protective coating in S2 also includes the following method: after the chip surface is pretreated, a layer of protective material is evenly coated to form a preliminary protective layer, and the thickness of the protective coating is controlled to be 100-300 nm.

[0007] Preferably, the new protective material is a silicon nitride passivation layer, which is deposited using plasma enhanced chemical vapor deposition technology with a thickness of 100-200nm. The reaction temperature of the PECVD process is controlled at 300-400°C, the reaction pressure is 100-300mTorr, and the power is 100-500W.

[0008] Preferably, the packaging layer processing in S3 also includes the following steps: S301: packaging material preparation: selecting packaging materials and preparing metal wires for chip interconnection; S302: chip interconnection and bottom filling: mounting the chip on the packaging substrate, interconnecting the chip and the substrate through hot pressing bonding technology, and performing bottom filling and curing by vacuum assisted potting; S303: stacking of packaging layers: selecting two or more materials from the prepared packaging materials, and stacking and coating the selected materials on the outer wall on the basis of the protective coating of S2 to form a multi-layer composite protective structure; S304: packaging curing.

[0009] Preferably, the S304 encapsulation curing also includes the following steps: S3041: encapsulation layer curing: after the encapsulation layer stacking is completed, a curing treatment is required to make each layer of material cross-linked and cured to form a hard protective shell; S3042: encapsulation shell molding and curing: use injection molding technology to form a encapsulation shell around the cured encapsulation layer, and perform post-curing treatment, S3043: curing method; S3044: after curing is completed, sealing and protection treatment is required, a silicone rubber sealing layer is coated on the surface of the encapsulation shell, and an electromagnetic shielding tape is wrapped around the outside of the package.

[0010] Preferably, the thickness of the silicone rubber sealing layer in the S3044 is 0.5-1 mm, and the drying temperature is 80-120° C. The electromagnetic shielding tape is copper foil tape or nickel foil tape, with a thickness of 0.05-0.1 mm and 2-4 winding layers.

[0011] Preferably, the S4 packaging test further includes the following steps: S401: packaging layer detection; S402: packaging chip detection.

[0012] Preferably, the contents of the S401 packaging layer detection test are as follows: X-ray detection: using X-ray perspective to check whether there are defects in the internal structure of the packaging layer; ultrasonic detection: using the reflection characteristics of ultrasonic waves to detect the density and bonding strength of the packaging layer.

[0013] Preferably, the S402 packaged chip inspection contents are as follows: Reliability test: performing reliability tests such as high temperature aging test, low temperature storage test, temperature cycle test, humidity test, vibration test and impact test on the packaged chip; Electrical performance test: verifying whether the electrical performance of the packaged chip meets the standards through the electrical performance test.

[0014] After adopting the above technical solution, the present invention has the following beneficial effects compared with the prior art: the present invention; 1. This is a reinforced packaging process for embedded memory chips. Through the steps of chip surface pretreatment, protective coating, packaging layer stacking, curing treatment and quality inspection, the stability and durability of the memory chip are significantly improved. This process is suitable for the packaging needs of various memory chips, and can effectively improve the impact resistance, corrosion resistance and thermal stability of the chip, and reduce the failure rate caused by environmental factors; 2. This reinforced packaging process for embedded memory chips significantly improves the safety of product chips through triple protection of the initial protective layer, the stacked packaging layer and the packaging shell. At the same time, the chip is surface passivated and a silicon nitride passivation layer is deposited on the chip surface using plasma enhanced chemical vapor deposition technology to enhance the hardness and corrosion resistance of the chip surface, while reducing charge accumulation on the chip surface to prevent electrostatic discharge from damaging the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the attached picture: Figure 1 The present invention is a schematic diagram of the process flow of a reinforced packaging process for an embedded memory chip. DETAILED DESCRIPTION

[0016] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments so that those skilled in the art can implement the invention with reference to the description.

[0017] It should be understood that the terms such as “having”, “including” and “comprising” used herein do not exclude the existence or addition of one or more other elements or combinations thereof.

[0018] In the description of the present invention, the terms "lateral", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" etc. to indicate directions or positional relationships are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present invention and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.

[0019] Example 1: Reference Figure 1 , a reinforcement packaging process for an embedded memory chip, further comprising the following steps: S1: Chip pretreatment, chemical cleaning and ultrasonic cleaning of embedded memory chips; Specifically: Plasma cleaning: using the highly active chemical properties of plasma to effectively remove surface organic pollutants and inorganic impurities; Ultraviolet irradiation: high-energy ultraviolet irradiation can decompose surface organic matter and increase surface activity; Chemical cleaning: Use specific chemical cleaning agents to remove different types of pollutants. Chemical cleaning uses isopropyl alcohol and acetone as cleaning liquids. The ultrasonic cleaning frequency is 20kHz-50kHz, and the cleaning time is 5 to 10 minutes. Preferably: firstly, the chip is placed in an ultrasonic cleaning tank filled with isopropyl alcohol, cleaned at a frequency of 30kHz for 8 minutes, then rinsed with deionized water, then ultrasonically cleaned in acetone for 5 minutes, and finally dried with high-purity nitrogen; S2: Apply protective coating: After the chip surface is pretreated, a layer of protective material is evenly coated to form a preliminary protective layer. The thickness of the protective coating is controlled at 100-300nm. Specific: Common protective coatings: Silicon nitride passivation layer: A silicon nitride passivation layer is deposited on the surface of the chip to effectively isolate air and moisture, thereby preventing metal oxidation and corrosion and extending the service life of metal parts. The silicon nitride passivation layer is deposited using plasma enhanced chemical vapor deposition technology with a thickness of 100-200nm. The reaction temperature of the PECVD process is controlled at 300-400°C, the reaction pressure is 100-300mTorr, and the power is 100-500W; Preferably: a Si3N4 passivation layer with a thickness of 150 nm is deposited on the chip surface by PECVD technology, the flow ratio of the reaction gas silane and ammonia is 1:3, the reaction temperature is 350°C, the reaction pressure is 200mTorr, and the power is 300W; Silicone: has good elasticity and high temperature resistance, and can effectively buffer external impact; Epoxy resin: has excellent adhesion and chemical resistance, providing solid protection; Other polymer materials: such as polyimide, polystyrene, etc., selected according to specific needs; S3: encapsulation layer processing; The process includes: S301: preparing packaging materials: selecting packaging materials and preparing metal wires for chip interconnection; Packaging materials include: polymer materials: such as different types of epoxy resins, polyimide, etc., which provide good insulation and mechanical strength; Metal materials: such as copper and aluminum, which have good thermal conductivity and electromagnetic shielding effect; Ceramic materials: such as alumina, aluminum nitride, etc., have excellent high temperature resistance and chemical stability; Specifically: the stacked packaging layer uses alumina and polyimide as the basic materials of the packaging layer, and the metal wires for chip interconnection use gold (Au) wires or palladium silver (PdAg) alloy wires with a diameter of 20-50μm; The preferred metal wire for chip interconnection is Au wire with a diameter of 30 μm as the chip interconnection material; S302: Chip interconnection and bottom filling: mount the chip on the packaging substrate, realize the interconnection between the chip and the substrate through the hot pressing bonding technology, and use the vacuum assisted potting method for bottom filling and curing. The chip mounting accuracy is controlled within ±5μm; the hot pressing bonding temperature is 200-300°C, the pressure is 10-50g, and the time is 5-10 seconds; the bottom filling material curing temperature is 100-150°C, and the curing time is 1-2 hours; Preferably, a high-precision chip mounter is used to mount the chip on the package substrate, with a mounting accuracy of ±3 μm; The chip interconnection was performed using thermocompression bonding technology, with a thermocompression bonding temperature of 250°C, a pressure of 30g, and a time of 8 seconds. One end of the Au wire was bonded to the chip pin, and the other end was bonded to the substrate pad. The underfill material was injected into the gap between the chip and the substrate by vacuum-assisted potting, and then the package was placed in an oven at 120°C for 1.5 hours for curing; S303: Stacking of encapsulation layers: On the basis of the protective coating, encapsulation layers are stacked to form a multi-layer composite protective structure. The selection of each layer of encapsulation material needs to comprehensively consider its physical properties, chemical stability and process compatibility; During the stacking process, the thickness of each layer of material and the interlayer bonding strength must be precisely controlled to ensure the stability and reliability of the overall structure; S304: Packaging curing includes: S3041: Encapsulation layer curing: After the encapsulation layers are stacked, they need to be cured to cross-link and solidify the materials of each layer to form a hard protective shell; S3042: Package shell molding and curing: Use injection molding technology to form a package shell around the cured package layer, and perform post-curing treatment; Specifically: epoxy resin, 5% to 10% nano silicon dioxide and 3% to 8% nano aluminum oxide particles are added to the epoxy resin, and the epoxy resin is evenly dispersed by high-speed stirring and ultrasonic dispersion. The thickness of the packaging shell is 1-3 mm, the injection pressure is 50-100 MPa, the injection speed is 10-30 mm / s, the injection temperature is 150-200°C, the post-curing temperature is 120-180°C, and the post-curing time is 2-4 hours; Preferably: epoxy resin is selected as the base material, 8% of nano-SiO2 and 5% of nano-Al2O3 particles are added by mass fraction, stirred at a speed of 2000rpm for 30 minutes by a high-speed stirrer, and then dispersed at a frequency of 40kHz for 20 minutes by an ultrasonic disperser to make the nanoparticles uniformly dispersed in the epoxy resin, the modified epoxy resin is heated to 180°C to make it liquid, and then a packaging shell with a thickness of 2mm is formed around the chip and the substrate by injection molding, the injection pressure is 80MPa, the injection speed is 20mm / s, and after the injection molding is completed, the package is post-cured at 150°C for 3 hours; S3043: The curing methods include: Heat treatment: heating is used to cause the material to undergo a cross-linking reaction to form a stable solid structure; UV curing: Use ultraviolet radiation to initiate a photochemical reaction in the material to achieve rapid curing; Other appropriate curing methods: such as microwave curing, electron beam curing, etc., can be selected according to specific needs; It should be noted that during the curing process, the temperature, time and environmental conditions must be strictly controlled to ensure that the curing effect reaches the expected result; S3044: After curing, it needs to be sealed and protected. A silicone rubber sealing layer is applied to the surface of the package shell, and an electromagnetic shielding tape is wrapped around the outside of the package. Specifically: the thickness of the silicone rubber sealing layer is 0.5-1mm, and the drying temperature is 80-120°C; the electromagnetic shielding tape uses copper foil tape or nickel foil tape, with a thickness of 0.05-0.1mm and 2-4 layers of winding; Preferably: a 0.8 mm thick silicone rubber sealing layer is sprayed on the surface of the packaging shell, and then dried at 100° C. for 1 hour to solidify it; Wrap 3 layers of 0.08mm thick copper foil electromagnetic shielding tape around the outside of the package; S4: Packaging test: After the packaging process is completed, the packaged chips are strictly tested for quality to ensure that the packaging effect meets the predetermined quality standards. The test contents are as follows: S401: Encapsulation layer detection, the detection method is as follows: X-ray inspection: Use X-ray to check whether there are defects in the internal structure of the packaging layer; Ultrasonic testing: using the reflection characteristics of ultrasonic waves to detect the density and bonding strength of the packaging layer; S402: Packaged chip inspection, the inspection contents include: Reliability testing: Conduct reliability tests such as high temperature aging test, low temperature storage test, temperature cycle test, humidity test, vibration test and impact test on the packaged chips; Electrical performance test: Through electrical performance test, verify whether the electrical performance of the packaged chip meets the standard; Through comprehensive packaging quality testing, we ensure that each packaged chip has excellent reliability and stability; Specifically: various reliability tests were carried out on the packaged chips. The results of the high-temperature aging test showed that after the chip worked continuously at 125°C for 1000 hours, there was no obvious performance degradation, and data reading and writing were normal; after the low-temperature storage test, the chip was able to start and work normally after being stored at -40°C for 500 hours, and there was no data loss; after 500 temperature cycle tests, the electrical performance and structural integrity of the chip remained good; after 500 hours of humidity testing, there was no obvious sign of moisture inside the chip; after the vibration test and impact test, the chip pins were not broken, the electrical connection was normal, and the data storage and reading functions were not affected.

[0020] Working principle: First, put the chip into an ultrasonic cleaning tank filled with isopropanol, clean it at a frequency of 30kHz for 8 minutes, then rinse it with deionized water, put it into acetone for ultrasonic cleaning for 5 minutes, and finally blow it dry with high-purity nitrogen. A 150nm thick Si3N4 passivation layer will be deposited on the chip surface using PECVD technology. The flow ratio of the reaction gas silane and ammonia is 1:3, the reaction temperature is 350°C, the reaction pressure is 200mTorr, and the power is 300W; Epoxy resin was selected as the basic material of the package shell, and 8% nano-SiO2 and 5% nano-Al2O3 particles were added by mass fraction. The mixture was stirred at a speed of 2000 rpm for 30 minutes by a high-speed stirrer, and then dispersed at a frequency of 40 kHz by an ultrasonic disperser for 20 minutes to make the nano-particles evenly dispersed in the epoxy resin. The metal wire for chip interconnection selected Au wire with a diameter of 30 μm as the chip interconnection material. The chip was mounted on the package substrate using a high-precision chip mounter with a mounting accuracy of ±3 μm. The chip was interconnected using hot pressing bonding technology with a hot pressing bonding temperature of 250°C, a pressure of 30g, and a time of 8 seconds. One end of the Au wire was bonded to the chip pin and the other end was bonded to the substrate pad. The bottom filling material was injected into the gap between the chip and the substrate by vacuum assisted potting, and then the package was placed in an oven at 120°C for curing for 1.5 hours. Alumina and polyimide are selected as the basic materials of the encapsulation layer. After melting, they are stacked and coated on the outside of the Si3N4 passivation layer of the chip to form an encapsulation layer. The modified epoxy resin is heated to 180°C to make it liquid, and then a packaging shell with a thickness of 2mm is formed around the chip and the substrate by injection molding. The injection pressure is 80MPa and the injection speed is 20mm / s. After the injection molding is completed, the package is cured at 150°C for 3 hours to form a packaging protective shell; double protection is performed. After the packaging shell is cured, it needs to be sealed and protected. A layer of 0.8mm thick silicone rubber sealing layer is sprayed on the surface of the packaging shell, and then dried at 100°C for 1 hour to solidify it; 3 layers of 0.08mm thick copper foil electromagnetic shielding tape are wrapped around the outside of the package. The packaging is completed, and packaging detection is required after the packaging is completed; First, X-rays are used to check whether there are defects in the internal structure of the packaging layer. Then, the reflection characteristics of ultrasound are used to detect the density and bonding strength of the packaging layer. Then, reliability tests and electrical performance tests are carried out on the packaged chip performance.

[0021] Embodiment 2: It is basically the same as Embodiment 1, but further: First, the chip was placed in an ultrasonic cleaning tank filled with isopropyl alcohol and cleaned at a frequency of 30kHz for 8 minutes, then rinsed with deionized water, and then ultrasonically cleaned in acetone for 5 minutes, and finally dried with high-purity nitrogen. After the surface of the chip was cleaned, a layer of silica gel was evenly coated to form a preliminary protective coating with a thickness controlled at 200nm. Epoxy resin was selected as the basic material of the package shell, and 8% nano-SiO2 and 5% nano-Al2O3 particles were added by mass fraction. The mixture was stirred at a speed of 2000 rpm for 30 minutes by a high-speed stirrer, and then dispersed at a frequency of 40 kHz by an ultrasonic disperser for 20 minutes to make the nano-particles evenly dispersed in the epoxy resin. The metal wire for chip interconnection selected Au wire with a diameter of 30 μm as the chip interconnection material. The chip was mounted on the package substrate using a high-precision chip mounter with a mounting accuracy of ±3 μm. The chip was interconnected using hot pressing bonding technology with a hot pressing bonding temperature of 250°C, a pressure of 30g, and a time of 8 seconds. One end of the Au wire was bonded to the chip pin and the other end was bonded to the substrate pad. The bottom filling material was injected into the gap between the chip and the substrate by vacuum assisted potting, and then the package was placed in an oven at 120°C for curing for 1.5 hours. Aluminum nitride and epoxy resin are selected as the basic materials of the encapsulation layer, and the two are melted and stacked and coated on the outside of the initial protective coating of the chip to form an encapsulation layer; The modified epoxy resin is heated to 180°C to make it liquid, and then a packaging shell with a thickness of 2mm is formed around the chip and the substrate by injection molding. The injection pressure is 80MPa and the injection speed is 20mm / s. After the injection molding is completed, the package is cured for 3 hours after heat treatment at 150°C to form a packaging protective shell; double protection is performed. After the packaging shell is cured, it needs to be sealed and protected. A layer of 0.7mm thick silicone rubber sealing layer is sprayed on the surface of the packaging shell, and then dried at 100°C for 0.8 hours to cure it; 3 layers of 0.08mm thick copper foil electromagnetic shielding tape are wrapped around the outside of the package. The packaging is completed, and packaging detection is required after the packaging is completed; First, X-rays are used to check whether there are defects in the internal structure of the packaging layer. Then, the reflection characteristics of ultrasound are used to detect the density and bonding strength of the packaging layer. Then, reliability tests and electrical performance tests are carried out on the packaged chip performance.

[0022] Embodiment 3: It is basically the same as Embodiment 2, but further: First, the chip was placed in an ultrasonic cleaning tank filled with isopropyl alcohol and cleaned at a frequency of 30kHz for 8 minutes, then rinsed with deionized water, and then ultrasonically cleaned in acetone for 5 minutes, and finally dried with high-purity nitrogen. After the surface of the chip was cleaned, a layer of silica gel was evenly coated to form a preliminary protective coating with a thickness controlled at 150nm; Epoxy resin was selected as the basic material of the package shell, and 8% of nano-SiO2 and 5% of nano-Al2O3 particles were added by mass fraction. The mixture was stirred at a speed of 2000 rpm for 30 minutes by a high-speed stirrer, and then dispersed at a frequency of 40 kHz by an ultrasonic disperser for 20 minutes to make the nano-particles evenly dispersed in the epoxy resin. The metal wire for chip interconnection selected Au wire with a diameter of 30 μm as the chip interconnection material. The chip was mounted on the package substrate using a high-precision chip mounter with a mounting accuracy of ±3 μm. The chip was interconnected using hot pressing bonding technology with a hot pressing bonding temperature of 250°C, a pressure of 30g, and a time of 8 seconds. One end of the Au wire was bonded to the chip pin and the other end was bonded to the substrate pad. The bottom filling material was injected into the gap between the chip and the substrate by vacuum assisted potting, and then the package was placed in an oven at 150°C for curing for 1 hour. Aluminum nitride and epoxy resin are selected as the basic materials of the encapsulation layer, and the two are melted and stacked and coated on the outside of the initial protective coating of the chip to form an encapsulation layer; The modified epoxy resin is heated to 180°C to make it liquid, and then a packaging shell with a thickness of 2mm is formed around the chip and the substrate by injection molding. The injection pressure is 80MPa and the injection speed is 20mm / s. After the injection molding is completed, the package is cured at 150°C for 3 hours to form a packaging protective shell; double protection is performed. After the packaging shell is cured, it needs to be sealed and protected. A layer of 1mm thick silicone rubber sealing layer is sprayed on the surface of the packaging shell, and then dried at 100°C for 1.2 hours to solidify it; 3 layers of 0.05mm thick copper foil electromagnetic shielding tape are wrapped around the outside of the package. The packaging is completed, and packaging detection is required after the packaging is completed; First, X-rays are used to check whether there are defects in the internal structure of the packaging layer. Then, the reflection characteristics of ultrasound are used to detect the density and bonding strength of the packaging layer. Then, reliability tests and electrical performance tests are carried out on the packaged chip performance.

[0023] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which are equivalent modifications and improvements made to the above embodiments based on the essential technology of the present invention, and all of them belong to the protection scope of the present invention.

Claims

1. A reinforced packaging process for an embedded memory chip, characterized in that: The following steps are also included: S1: chip pretreatment; S2: Application of protective coating; S3: encapsulation layer processing; S4: Packaging test.

2. The reinforced packaging process of an embedded memory chip according to claim 1, characterized in that: The chip preprocessing in S1 also includes the following method: Plasma cleaning, ultraviolet irradiation and chemical cleaning are used.

3. The reinforced packaging process of an embedded memory chip according to claim 1, characterized in that: The application of the protective coating in S2 also includes the following method: After the chip surface is pretreated, a layer of protective material is evenly coated to form a preliminary protective layer. The thickness of the protective coating is controlled at 100-300nm.

4. The reinforced packaging process of an embedded memory chip according to claim 3, characterized in that: The protective material is a silicon nitride passivation layer, which is deposited using plasma enhanced chemical vapor deposition technology and has a thickness of 100-200nm. The reaction temperature of the PECVD process is controlled at 300-400°C, the reaction pressure is 100-300mTorr, and the power is 100-500W.

5. The reinforced packaging process of an embedded memory chip according to claim 1, characterized in that: The encapsulation layer processing in S3 further includes the following steps: S301: Packaging material preparation: Select packaging materials and prepare metal wires for chip interconnection; S302: Chip interconnection and bottom filling: mount the chip on the packaging substrate, interconnect the chip and the substrate through thermal compression bonding technology, and use vacuum assisted potting method to perform bottom filling and curing; S303: stacking of packaging layers: selecting two or more materials from the prepared packaging materials, and stacking and coating the selected materials on the outer wall of the protective coating in S2 to form a multi-layer composite protective structure; S304: Package curing.

6. The reinforced packaging process of an embedded memory chip according to claim 5, characterized in that: The S304 packaging curing also includes the following steps: S3041: Encapsulation layer curing: After the encapsulation layers are stacked, they need to be cured to cross-link and solidify the materials of each layer to form a hard protective shell; S3042: Package shell molding and curing: Use injection molding technology to form a package shell around the cured package layer, and perform post-curing treatment; S3043: Curing method; S3044: After curing, sealing and protection treatment is required. Apply a silicone rubber sealing layer on the surface of the package shell and wrap electromagnetic shielding tape around the outside of the package.

7. The reinforced packaging process of an embedded memory chip according to claim 6, characterized in that: The thickness of the silicone rubber sealing layer in the S3044 is 0.5-1 mm, and the drying temperature is 80-120° C. The electromagnetic shielding tape is made of copper foil tape or nickel foil tape, with a thickness of 0.05-0.1 mm and 2-4 layers of winding.

8. The reinforced packaging process of an embedded memory chip according to claim 1, characterized in that: The S4 packaging test also includes the following steps: S401: Encapsulation layer detection; S402: Packaged chip inspection.

9. The reinforced packaging process of an embedded memory chip according to claim 8, characterized in that: The S401 encapsulation layer detection test content is as follows: X-ray inspection: Use X-ray to check whether there are defects in the internal structure of the packaging layer; Ultrasonic testing: Use the reflection characteristics of ultrasound to detect the density and bonding strength of the packaging layer.

10. The reinforced packaging process of an embedded memory chip according to claim 9, characterized in that: The S402 packaged chip test content is as follows: Reliability test: The packaged chip is subjected to reliability tests such as high temperature aging test, low temperature storage test, temperature cycle test, humidity test, vibration test and impact test; Electrical performance test: Through electrical performance test, verify whether the electrical performance of the packaged chip meets the standards.

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