Low-thermal-resistance power module

Abstract

The invention provides a low thermal resistance power module, which comprises an insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, the insulating ceramic substrate comprises an upper bridge arm and a lower bridge arm which are arranged along a first direction, a part of chips are arranged on the upper bridge arm, and the other part of chips are arranged on the lower bridge arm. The plurality of chips arranged on the upper bridge arm and the plurality of chips arranged on the lower bridge arm are symmetrically arranged, every two adjacent chips in the first direction are arranged in a staggered mode in the second direction, and the first direction is perpendicular to the second direction. According to the low-thermal-resistance power module, the staggered chip layout is adopted, the thermal coupling effect between the chips can be reduced, the thermal resistance of the power module is reduced, and the power density of the module is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a low thermal resistance power module. Background Art

[0002] In the field of power semiconductors, after decades of development and utilization, the performance of traditional silicon devices has approached their physical limits. In recent years, with the advancement of semiconductor manufacturing technology, the third-generation wide bandgap power semiconductors have developed rapidly. Among them, silicon carbide is considered to be the best choice for replacing silicon materials to manufacture power semiconductor devices due to its superior material properties. Compared with silicon materials, silicon carbide has lower conduction loss and switching loss, and can achieve higher switching frequency and power density. As a key component of the electronic control system of new energy vehicles, power modules affect the energy density and work efficiency of new energy vehicles. Silicon carbide power modules can achieve higher power density due to their high efficiency and high switching frequency. However, high power density means a greater output heat flux density, which brings more stringent conditions to the heat dissipation design of the module. This poses a severe challenge to the thermal output characteristics of silicon carbide power modules. The traditional chip layout obviously cannot support its full application potential. Summary of the invention

[0003] The present application provides a low thermal resistance power module to solve at least some of the problems in the related art.

[0004] In a first aspect, the present application provides a low thermal resistance power module, comprising an insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, the insulating ceramic substrate comprising an upper bridge arm and a lower bridge arm arranged along a first direction, a part of the chips being arranged on the upper bridge arm, and another part of the chips being arranged on the lower bridge arm; the plurality of chips arranged on the upper bridge arm are symmetrically arranged with the plurality of chips arranged on the lower bridge arm, and two adjacent chips along the first direction are staggeredly arranged along the second direction; the first direction is perpendicular to the second direction.

[0005] Optionally, the upper bridge arm includes a first upper bridge arm and a second upper bridge arm arranged along the second direction; the first upper bridge arm and the second upper bridge arm are symmetrically arranged along the first direction, a plurality of chips located at the first upper bridge arm and a plurality of chips located at the second upper bridge arm are symmetrically arranged along the first direction, a plurality of chips located at the first upper bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction; a plurality of chips located at the second upper bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction.

[0006] Optionally, the lower bridge arm includes a first lower bridge arm and a second lower bridge arm arranged along the second direction; the first lower bridge arm and the second lower bridge arm are symmetrically arranged along the first direction, a plurality of chips located in the first lower bridge arm and a plurality of chips located in the second lower bridge arm are symmetrically arranged along the first direction, a plurality of chips located in the first lower bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction; a plurality of chips located in the second lower bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction.

[0007] Optionally, the chip includes a first surface and a second surface that are arranged opposite to each other, the first surface is connected to the insulating ceramic substrate, and the power module further includes a conductive member, which is respectively connected to the second surface and the insulating ceramic substrate by welding or sintering.

[0008] Optionally, the insulating ceramic substrate includes an insulating layer and a first metal layer, the first metal layer is disposed on one side surface of the insulating layer, and the chip is connected to the first metal layer.

[0009] Optionally, the insulating layer is a ceramic layer, and the first metal layer is a copper layer.

[0010] Optionally, the chip includes a first surface and a second surface that are arranged opposite to each other, and the first surface is connected to the first metal layer through a silver sintering process.

[0011] Optionally, a signal electrode is provided on the second surface, and the signal electrode is connected to the first metal layer through a wire.

[0012] Optionally, the insulating ceramic substrate further includes a second metal layer, which is disposed on a side of the insulating layer facing away from the chip, and the second metal layer is a copper layer.

[0013] Optionally, the power module further includes a heat dissipation substrate and a shell, wherein the heat dissipation substrate is disposed on a side of the insulating ceramic substrate facing away from the chip, the heat dissipation substrate is connected to the shell to form a receiving cavity, and the insulating ceramic substrate and the chip are disposed in the receiving cavity.

[0014] Optionally, the accommodating cavity is filled with silicone gel, and the insulating ceramic substrate and the chip are encapsulated in the silicone gel.

[0015] Optionally, the chip is a silicon carbide chip.

[0016] Optionally, the chip located at the upper bridge arm and the chip located at the lower bridge arm are oriented in the same or opposite directions.

[0017] The low thermal resistance power module provided by the present application includes an insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, the insulating ceramic substrate includes an upper bridge arm and a lower bridge arm arranged along a first direction, a part of the chips are arranged on the upper bridge arm, and another part of the chips are arranged on the lower bridge arm. The multiple chips arranged on the upper bridge arm are symmetrically arranged with the multiple chips arranged on the lower bridge arm, and two adjacent chips along the first direction are staggered along the second direction, and the first direction is perpendicular to the second direction. The low thermal resistance power module of the present application uses a staggered chip layout to reduce the thermal coupling effect between chips, reduce the thermal resistance of the power module, and improve the power density of the module.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] Figure 1 Shown is a schematic structural diagram of a power module according to an exemplary embodiment of the present application;

[0021] Figure 2 FIG. 1 is a schematic structural diagram of a power module according to another exemplary embodiment of the present application;

[0022] Figure 3 Shown is a schematic structural diagram of an insulating ceramic substrate of an exemplary embodiment of the present application;

[0023] Figure 4 Shown is a schematic structural diagram of an insulating ceramic substrate according to another exemplary embodiment of the present application;

[0024] Figure 5 FIG. 1 is a schematic structural diagram of an insulating ceramic substrate according to another exemplary embodiment of the present application;

[0025] Figure 6 Shown is a cross-sectional view of a power module according to an exemplary embodiment of the present application;

[0026] Figure 7 Shown Figure 6 A partial enlarged view of the cross-section of the power module shown. DETAILED DESCRIPTION

[0027] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0028] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. Unless otherwise defined, the technical terms or scientific terms used in this application should be understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar words used in the specification and claims of this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantitative limit, but indicate that there is at least one. "Multiple" or "several" means two or more. Unless otherwise specified, words such as "front", "rear", "lower" and / or "upper" are only for the convenience of explanation and are not limited to one position or one spatial orientation. Words such as "include" or "comprise" mean that the elements or objects appearing in front of "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect.

[0029] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0030] In the field of power semiconductors, after decades of development and utilization, the performance of traditional silicon devices has approached their physical limits. In recent years, with the advancement of semiconductor manufacturing technology, the third-generation wide bandgap power semiconductors have developed rapidly. Among them, silicon carbide is considered to be the best choice for replacing silicon materials to manufacture power semiconductor devices due to its superior material properties. Compared with silicon materials, silicon carbide has lower conduction loss and switching loss, and can achieve higher switching frequency and power density. As a key component of the electronic control system of new energy vehicles, power modules affect the energy density and work efficiency of new energy vehicles. Silicon carbide power modules can achieve higher power density due to their high efficiency and high switching frequency. However, high power density means a greater output heat flux density, which brings more stringent conditions to the heat dissipation design of the module. This poses a severe challenge to the thermal output characteristics of silicon carbide power modules. The traditional chip layout obviously cannot support its full application potential.

[0031] The low thermal resistance power module of the present application uses a staggered chip layout to reduce the thermal coupling effect between chips, lower the thermal resistance of the power module, and improve the power density of the module.

[0032] The present application provides a low thermal resistance power module. The low thermal resistance power module of the present application is described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0033] Figure 1 FIG. 1 is a schematic diagram of the structure of a power module 1 according to an exemplary embodiment of the present application. Figure 2 FIG. 1 is a schematic diagram of the structure of a power module 1 according to another exemplary embodiment of the present application. Figure 3 FIG. 4 is a schematic structural diagram of an insulating ceramic substrate 4 according to an exemplary embodiment of the present application. Figure 4 FIG. 4 is a schematic structural diagram of an insulating ceramic substrate 4 according to another exemplary embodiment of the present application. Figure 5 FIG. 4 is a schematic structural diagram of an insulating ceramic substrate 4 according to another exemplary embodiment of the present application. Figure 6 FIG. 1 is a cross-sectional view of a power module 1 according to an exemplary embodiment of the present application. Figure 7 Shown Figure 6 The cross-sectional view of the power module 1 is shown in FIG. Figures 1 to 7 The present application provides a low thermal resistance power module, comprising: an insulating ceramic substrate 4 and a plurality of chips 5 arranged on the insulating ceramic substrate 4, wherein the insulating ceramic substrate 4 comprises an upper bridge arm 7 and a lower bridge arm 6 arranged along a first direction X1, a portion of the chips 5 are arranged on the lower bridge arm 6, and another portion of the chips 5 are arranged on the upper bridge arm 7. The plurality of chips 5 arranged on the upper bridge arm 7 are symmetrically arranged with the plurality of chips 5 arranged on the lower bridge arm 6, and two adjacent chips 5 along the first direction X1 are arranged alternately, and the first direction X1 is perpendicular to the second direction X2.

[0034] The power module 1 of the present application is composed of three half-bridge units 3 to form a three-phase full-bridge power module. Figure 3 In the embodiment shown, the power module 1 includes an insulating ceramic substrate 4 and twelve chips 5. Six chips 5 are respectively provided on the lower bridge arm 6 and the upper bridge arm 7. The six chips 5 are symmetrically arranged in pairs along the first direction X1. The three chips 5 on the same side are staggered in the second direction X2 and are spaced apart along the first direction X1. Similarly, refer to Figure 4 and Figure 5 The chips 5 can also be arranged in a variety of staggered ways, and the present application does not limit the staggered arrangement of the chips 5. By staggering the chips 5, the gaps between the chips 5 can be increased, which promotes better heat dissipation, reduces the thermal coupling effect between the chips 5, and reduces the thermal resistance of the power module 1.

[0035] In some embodiments, the lower bridge arm 6 includes a first lower bridge arm 60 and a second lower bridge arm 61 arranged along a second direction X2, and the second direction X2 is perpendicular to the first direction X1. The first lower bridge arm 60 and the second lower bridge arm 61 are symmetrically arranged along the first direction X1, and the multiple chips 5 located in the first lower bridge arm 60 and the multiple chips 5 located in the second lower bridge arm 61 are symmetrically arranged along the first direction X1. The multiple chips 5 located in the first lower bridge arm 60 are spaced apart along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. The multiple chips 5 located in the second lower bridge arm 61 are spaced apart along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. Figures 1 to 5 In the embodiment shown, six chips 5 are arranged in the lower bridge arm 6, of which three chips 5 are arranged in the first lower bridge arm 60, and the remaining three chips 5 are arranged in the second lower bridge arm 61. The three chips 5 located in the first lower bridge arm 60 and the three chips 5 located in the second lower bridge arm 61 are symmetrically arranged along the first direction X1, and two adjacent chips 5 are arranged at intervals along the first direction X1 and staggered along the second direction X2. Figure 1 and Figure 3 , two non-adjacent chips 5 among the three chips 5 are arranged near the edge of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the middle of the insulating ceramic substrate 4. Figure 4 In the embodiment shown, two non-adjacent chips 5 of the three chips 5 located in the first lower bridge arm 60 are arranged near the middle of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the edge of the insulating ceramic substrate 4. Figure 3 The embodiment shown is consistent with the embodiment shown. Figure 5 In the embodiment shown, the arrangement and Figure 3The embodiment shown is consistent, two non-adjacent chips among the three chips 5 located in the second lower bridge arm 61 are arranged near the middle of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the edge of the insulating ceramic substrate 4. The chips 5 can also have a variety of staggered arrangements, and the present application does not limit the staggered arrangement of the chips 5. By increasing the gap between the chips 5, better heat dissipation can be promoted, the thermal coupling effect between the chips 5 can be reduced, the thermal resistance of the power module 1 can be reduced, and the module power density can be improved.

[0036] In some embodiments, the upper bridge arm 7 includes a first upper bridge arm 70 and a second upper bridge arm 71 arranged along a second direction X2, and the second direction X2 is perpendicular to the first direction X1. The first upper bridge arm 70 and the second upper bridge arm 71 are symmetrically arranged along the first direction X1, and the multiple chips 5 located in the first upper bridge arm 70 and the multiple chips 5 located in the second upper bridge arm 71 are symmetrically arranged along the first direction X1. The multiple chips 5 located in the first upper bridge arm 70 are spaced apart along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. The multiple chips 5 located in the second upper bridge arm 71 are spaced apart along the first direction X1, and two adjacent chips 5 are staggered along the second direction X1. Figures 1 to 5 In the embodiment shown, six chips 5 are arranged in the upper bridge arm 7, of which three chips 5 are arranged in the first upper bridge arm 70, and the remaining three chips 5 are arranged in the second upper bridge arm 71. The three chips 5 located in the first upper bridge arm 70 and the three chips 5 located in the second upper bridge arm 71 are symmetrically arranged along the first direction X1, and two adjacent chips 5 are arranged at intervals along the first direction X1 and staggered along the second direction X2. Figure 1 and Figure 3 , two non-adjacent chips 5 among the three chips 5 are arranged near the edge of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the middle of the insulating ceramic substrate 4. Figure 4 In the embodiment shown, two non-adjacent chips 5 of the three chips 5 located in the first upper bridge arm 70 are arranged near the middle of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the edge of the insulating ceramic substrate 4. Figure 3 The embodiment shown is consistent with the embodiment shown. Figure 5 In the embodiment shown, the arrangement and Figure 3 The embodiment shown is consistent, two non-adjacent chips among the three chips 5 located in the second upper bridge arm 71 are arranged near the middle of the insulating ceramic substrate 4, and the remaining chip 5 is arranged near the edge of the insulating ceramic substrate 4. The chips 5 can also have a variety of staggered arrangements, and the present application does not limit the staggered arrangement of the chips 5. By increasing the gap between the chips 5, better heat dissipation can be promoted, the thermal coupling effect between the chips 5 can be reduced, the thermal resistance of the power module 1 can be reduced, and the module power density can be improved.

[0037] In some embodiments, the chip 5 located on the upper bridge arm 7 and the chip 5 located on the lower bridge arm 6 face the same direction or opposite directions. Figure 4 In the embodiment shown, the chip 5 located on the upper bridge arm 7 and the chip 5 located on the lower bridge arm 6 face in opposite directions. Figure 5 In the illustrated embodiment, the chip 5 located at the upper bridge arm 7 and the chip 5 located at the lower bridge arm 6 have the same orientation, which is not limited in the present application.

[0038] In some embodiments, the insulating ceramic substrate 4 includes an insulating layer 40 and a first metal layer 41, the first metal layer 41 is disposed on one side of the insulating layer 40, and the chip 5 is connected to the first metal layer 41. The insulating ceramic substrate 4 also includes a second metal layer 42, which is disposed on the side of the insulating layer 40 facing away from the chip 5, and the second metal layer 42 is a copper layer. The first metal layer 41 is used to connect power devices and other electronic components. The insulating layer 40 is used to provide electrical isolation to ensure safe isolation between different voltages and prevent current short circuits. Reference Figure 7 In an embodiment of the present application, the insulating layer 40 is a ceramic layer, the first metal layer 41 is a copper layer, and the second metal layer 42 is a copper layer. Ceramics have high insulation and high temperature resistance, can effectively isolate circuits between different voltages, and can also avoid the degradation of insulation performance due to excessive temperature. In some embodiments, the insulating layer 40 can be a silicon nitride ceramic layer, and the active metal brazing copper cladding technology is used to achieve high-temperature metallurgical bonding of silicon nitride and copper. The silicon nitride ceramic layer has good thermal conductivity and high reliability.

[0039] exist Figure 3 In the illustrated embodiment, the chip 5 includes a first surface (not shown) and a second surface 50 that are arranged opposite to each other, and the first surface is connected to the insulating ceramic substrate 4. The power module 1 also includes a conductive member 10, and the conductive member 10 is respectively connected to the second surface 50 and the insulating ceramic substrate 4 by welding or sintering. In the embodiment of the present application, the conductive member 10 is a copper foil, one end of the conductive member 10 is connected to the second surface 50 of the chip 5, and the other end is connected to the first metal layer 41 of the insulating ceramic substrate 4. In other embodiments, the conductive member 10 can be a copper wire. Copper foil has a larger conductive cross-sectional area than copper wire, can provide lower resistance and higher current capacity, improve the reliability of signal transmission, and can also improve the stability and durability of the connection.

[0040] In some embodiments, the chip 5 includes a first surface and a second surface 50 disposed opposite to each other, and the first surface is connected to the first metal layer 41 through a silver sintering process, such as Figure 7 Compared with the traditional welding method, the thickness of the sintered layer is reduced, which can provide good electrical connectivity, mechanical strength and thermal conductivity, help improve the reliability, heat dissipation effect and service life of the power module 1, and can also simplify the packaging structure of the power module 1.

[0041] In some embodiments, the second surface 50 is provided with a signal electrode 11, and the signal electrode 11 is connected to the first metal layer 41 through a wire 12. The surface of the chip 5 is provided with a signal electrode 11 and is connected to the first metal layer 41 through a wire 12. The signal electrode 11 is used to input or output a signal. Figure 3 In the embodiment of the present application, the signal electrode 11 of the chip 5 and the first metal layer 41 are connected by aluminum wires and the aluminum wire bonding process is used to realize signal transmission and control circuit. Such a setting can ensure a reliable connection between the signal electrode 11 and the control circuit, and realize the functions of signal transmission and control circuit.

[0042] exist Figure 2 , Figure 6 and Figure 7 In the illustrated embodiment, the power module 1 further includes a heat dissipation substrate 13 and a housing 2. The heat dissipation substrate 13 is disposed on the side of the insulating ceramic substrate 4 facing away from the chip 5. The heat dissipation substrate 13 is connected to the housing 2 and forms a receiving cavity 14. The insulating ceramic substrate 4 and the chip 5 are disposed in the receiving cavity 14. The housing 2 provides mechanical support for the power module 1 and isolates the interior of the power module 1 from the external environment. The area of ​​the heat dissipation substrate 13 is larger than that of the insulating ceramic substrate 4. The insulating ceramic substrate 4 and the heat dissipation substrate 13 can be connected by a silver sintering process. The heat dissipation substrate 13 is usually made of copper or aluminum, has good thermal conductivity, and can effectively dissipate heat and reduce the temperature of the chip 5. In addition, it can also fix and support the chip 5 and other components, thereby enhancing the structural stability and reliability of the entire power module 1.

[0043] In some embodiments, a power terminal 8 is provided on the shell 2, and the positive electrode of the power terminal 8 is divided into two paths inside the shell 2 and connected to the left and right sides of the upper bridge arm 7, and the negative electrode of the power terminal 8 is connected to the lower bridge arm 6. The power terminal 8 can be connected to the interface of the external power supply and the load.

[0044] In some embodiments, a plurality of pin fins 15 may be provided at one end of the heat dissipation substrate 13 away from the housing 2, such as Figure 6 and Figure 7 The pin fins 15 are placed in a coolant for water cooling, thereby further improving the heat dissipation efficiency of the power module 1.

[0045] In some embodiments, the housing 2 includes a first housing 20 and a second housing 21. The first housing 20 is formed around the edge of the insulating ceramic substrate 4, and the power terminal 8 is disposed on the first housing 20. The second housing 21 is disposed on a side of the insulating ceramic substrate 4 close to the chip 5, and is used to seal the insulating ceramic substrate 4 and the chip 5.

[0046] In some embodiments, the accommodating cavity 14 is filled with silicone gel (not shown), and the insulating ceramic substrate 4 and the chip 5 are encapsulated in the silicone gel. The silicone gel has good insulation performance, which can prevent short circuits or electrical failures between electrical components in the accommodating cavity 14, and can also prevent dust, moisture or chemicals from damaging the electrical components.

[0047] In the embodiment of the present application, the chip 5 is a silicon carbide chip. Silicon carbide has lower conduction loss and switching loss, and can achieve higher switching frequency and power density.

[0048] In some embodiments, the insulating ceramic substrate 4 is provided with a plurality of signal terminals 16 for receiving control signals from a control circuit or an external control system, so as to control parameters such as the switch state, working mode, output voltage or current of the power module 1 .

[0049] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0050] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A low thermal resistance power module, characterized in that: include: An insulating ceramic substrate and a plurality of chips arranged on the insulating ceramic substrate, wherein the insulating ceramic substrate comprises an upper bridge arm and a lower bridge arm arranged along a first direction, a part of the chips are arranged on the upper bridge arm, and another part of the chips are arranged on the lower bridge arm; the plurality of chips arranged on the upper bridge arm are symmetrically arranged with the plurality of chips arranged on the lower bridge arm, and two adjacent chips along the first direction are staggered along a second direction, and the first direction is perpendicular to the second direction.

2. The low thermal resistance power module according to claim 1, characterized in that: The upper bridge arm comprises a first upper bridge arm and a second upper bridge arm arranged along the second direction; the first upper bridge arm and the second upper bridge arm are symmetrically arranged along the first direction, the multiple chips located in the first upper bridge arm and the multiple chips located in the second upper bridge arm are symmetrically arranged along the first direction, the multiple chips located in the first upper bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction; the multiple chips located in the second upper bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction; and / or The lower bridge arm includes a first lower bridge arm and a second lower bridge arm arranged along the second direction; the first lower bridge arm and the second lower bridge arm are symmetrically arranged along the first direction, the multiple chips located in the first lower bridge arm and the multiple chips located in the second lower bridge arm are symmetrically arranged along the first direction, the multiple chips located in the first lower bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction; the multiple chips located in the second lower bridge arm are spaced apart along the first direction, and two adjacent chips are staggered along the second direction.

3. The low thermal resistance power module according to claim 1, characterized in that: The chip includes a first surface and a second surface arranged opposite to each other, the first surface is connected to the insulating ceramic substrate, and the power module also includes a conductive member, which is respectively connected to the second surface and the insulating ceramic substrate by welding or sintering.

4. The low thermal resistance power module according to claim 1, characterized in that: The insulating ceramic substrate comprises an insulating layer and a first metal layer, wherein the first metal layer is arranged on one side surface of the insulating layer, and the chip is connected to the first metal layer.

5. The low thermal resistance power module according to claim 4, characterized in that: The insulating layer is a ceramic layer, and the first metal layer is a copper layer.

6. The low thermal resistance power module according to claim 4, characterized in that: The chip includes a first surface and a second surface that are opposite to each other, and the first surface is connected to the first metal layer through a silver sintering process.

7. The low thermal resistance power module according to claim 6, characterized in that: The second surface is provided with a signal electrode, and the signal electrode is connected to the first metal layer through a wire.

8. The low thermal resistance power module according to claim 4, characterized in that: The insulating ceramic substrate further includes a second metal layer, which is arranged on a side of the insulating layer facing away from the chip, and the second metal layer is a copper layer.

9. The low thermal resistance power module according to claim 1, characterized in that: The power module further comprises a heat dissipation substrate and a shell. The heat dissipation substrate is arranged on a side of the insulating ceramic substrate facing away from the chip. The heat dissipation substrate is connected to the shell to form a receiving cavity. The insulating ceramic substrate and the chip are arranged in the receiving cavity.

10. The low thermal resistance power module according to claim 9, characterized in that: The accommodating cavity is filled with silicone gel, and the insulating ceramic substrate and the chip are encapsulated in the silicone gel.

11. The low thermal resistance power module according to claim 1, characterized in that: The chip is a silicon carbide chip.

12. The low thermal resistance power module according to claim 1, characterized in that: The chip located at the upper bridge arm and the chip located at the lower bridge arm are oriented in the same or opposite directions.

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