Package structure and fabrication method thereof

Abstract

A method of fabricating a package structure includes stacking a second electronic component having a plurality of conductive bumps on a first electronic component configured with a positioning layer such that the conductive bumps are inserted into a plurality of positioning holes of the positioning layer, the second electronic component is bonded on the positioning layer and is electrically connected with the first electronic component through the plurality of conductive bumps, so that the hybrid bonding technology is replaced through the matching of the positioning hole and the conductive bumps, and the packaging cost is further reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging process, and in particular to a packaging structure with a positioning mechanism and a manufacturing method thereof. Background Art

[0002] In response to the trend of today's electronic products towards being thin, light, short and high-performance, three-dimensional integrated circuits (3D ICs) are a three-dimensional chip stacking integration model that can not only shorten the length of metal wires and connection resistance, but also reduce the chip area. With its small size, high integration, low power consumption and low cost, it is considered to be the next generation of semiconductor technology.

[0003] Figure 1 1 is a cross-sectional view of a conventional package structure 1. The package structure 1 joins two semiconductor chips 10, 11, and each of the semiconductor chips 10, 11 comprises a chip body 100, 110, a passivation layer 101, 111 formed on the chip body 100, 110, and a plurality of metal pads 102, 112 formed on the chip body 100, 110, so that the metal pads 102, 112 are exposed from the passivation layer 101, 111, and the two semiconductor chips 10, 11 are fixedly joined to each other by contacting and joining with their metal pads 102, 112. The two semiconductor chips 10, 11 are joined by hybrid bonding, wherein the metal pads 102, 112 are made of copper, and the passivation layers 101, 111 are made of silicon oxide (SiO2). The passivation layers 101, 111 of the two semiconductor chips 10, 11 are then brought into contact with each other (as shown in the contact surface S) and heated (approximately 100°C) to fuse the two passivation layers 101, 111 so that the metal pads 102, 112 of the two semiconductor chips 10, 11 are aligned. The metal pads 102, 112 are then heated (approximately 300°C) to expand and contact each other for electrical connection.

[0004] However, in the existing packaging structure 1, during the hybrid bonding operation, the passivation layers 101, 111 are inorganic insulating layers, and their surfaces need to be very flat and very clean so that the passivation layers 101, 111 of the two semiconductor chips 10, 11 can be completely close together, and the metal pads 102, 112 of the two semiconductor chips 10, 11 can be accurately docked and electrically connected. Therefore, the flattening and cleaning operations on the surfaces of the passivation layers 101, 111 require a lot of time for inspection, and also require the use of extremely high-precision special flattening equipment and special cleaning equipment for flattening and cleaning operations, resulting in the required process equipment being extremely expensive, and even requiring the use of special heating equipment (such as a heating function exceeding 300°C), resulting in the overall packaging cost of the packaging structure 1 using the hybrid bonding method being extremely expensive, and thus difficult to be widely used in electronic products.

[0005] Therefore, how to overcome the various problems of the above-mentioned prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the present invention provides a packaging structure and a manufacturing method thereof, which can at least partially solve the problems of the prior art.

[0007] The packaging structure of the present invention includes: a first electronic component having a plurality of first electrode pads; a positioning layer, which is arranged on the first electronic component and has a plurality of positioning holes exposed from the plurality of first electrode pads; and a second electronic component, which is arranged on the positioning layer and has a plurality of second electrode pads, wherein the plurality of second electrode pads have a plurality of conductive bumps accommodated in the plurality of positioning holes so that each of the conductive bumps contacts each of the first electrode pads, so that the second electronic component is electrically connected to the first electronic component through the plurality of conductive bumps.

[0008] The present invention also provides a method for manufacturing a packaging structure, comprising: providing a first electronic component having a plurality of first electrode pads and a second electronic component having a plurality of second electrode pads; forming a positioning layer on the first electronic component, and forming a plurality of conductive bumps on the second electrode pads of the second electronic component, wherein the positioning layer has a plurality of positioning holes exposed from the plurality of first electrode pads; inserting the second electronic component with its plurality of conductive bumps into the plurality of positioning holes, so that the second electronic component is bonded to the positioning layer, and the plurality of conductive bumps do not contact the plurality of first electrode pads in the plurality of positioning holes; and heating the plurality of conductive bumps so that each of the conductive bumps contacts each of the first electrode pads, so that the second electronic component is electrically connected to the first electronic component through the plurality of conductive bumps.

[0009] In the aforementioned packaging structure and manufacturing method thereof, a gap is formed between the conductive bump and the wall surface of the positioning hole after being heated.

[0010] In the aforementioned packaging structure and its manufacturing method, the conductive bump includes a conductive column for combining with the second electrode pad and a conductive bonding material formed on the conductive column. For example, the conductive bonding material is a solder material.

[0011] In the aforementioned packaging structure and its manufacturing method, the material forming the positioning layer is an organic insulating material.

[0012] As can be seen from the above, the packaging structure and manufacturing method of the present invention mainly use the positioning hole and the conductive bump to fix the second electronic component on top of the first electronic component, and then electrically connect the first and second electronic components through the multiple conductive bumps to replace the traditional hybrid bonding technology. Therefore, compared with the existing technology, the present invention only needs to use conventional equipment without using special equipment, thereby greatly reducing the packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A cross-sectional view of an existing packaging structure.

[0014] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing a packaging structure of the present invention.

[0015] Main component symbols

[0016] 1,2 Package structure

[0017] 10,11 Semiconductor Chips

[0018] 100,110 Chip body

[0019] 101,111 Passivation layer

[0020] 102,112 Metal pads

[0021] 20 Positioning layer

[0022] 200 Positioning hole

[0023] 21 First Electronic Components

[0024] 21a First working surface

[0025] 21b First non-active surface

[0026] 210 first electrode pad

[0027] 22 Second electronic component

[0028] 22a Second working surface

[0029] 22b Second non-active surface

[0030] 220 Second electrode pad

[0031] 23 Conductive bumps

[0032] 230 Conductive Column

[0033] 231 Conductive bonding material

[0034] 232 Under Bump Metal

[0035] d,r width

[0036] h1 Height

[0037] h2 Depth

[0038] t interval

[0039] S contact surface. DETAILED DESCRIPTION

[0040] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0041] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0042] FIG. 2A to FIG. 2E It is a cross-sectional schematic diagram of a method for manufacturing a packaging structure 2 of the present invention.

[0043] like Figure 2A As shown, a first electronic component 21 having a plurality of first electrode pads 210 is provided, and a positioning layer 20 covering the first electrode pads 210 is formed on the first electronic component 21 .

[0044] The first electronic component 21 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor. In this embodiment, the first electronic component 21 is a semiconductor chip or a wafer specification, and has a first active surface 21a and a first inactive surface 21b opposite to each other, and the first active surface 21a has a plurality of first electrode pads 210.

[0045] The positioning layer 20 can be formed on the first active surface 21 a of the first electronic component 21 by lamination or molding.

[0046] In this embodiment, the positioning layer 20 is an insulating layer, and its material is an organic insulating material, such as dielectric materials such as polybenzoxazole (PBO), polyimide (PI), prepreg (PP), Ajinomoto Build-up Film (ABF), etc., or solder resist materials such as green paint and graphite. Preferably, the thermal curing temperature of the positioning layer 20 is less than or equal to 200° C. It should be understood that there are many types of organic insulating materials, which can be selected according to needs and are not limited to the above.

[0047] like Figure 2B As shown, a patterning process is performed to form a plurality of positioning holes 200 on the positioning layer 20 , so that each of the first electrode pads 210 is correspondingly exposed in each of the positioning holes 200 .

[0048] In this embodiment, the patterning process forms the positioning holes 200 by laser drilling, machine drilling, etching, exposure and development or other methods.

[0049] like Figure 2C As shown, a second electronic component 22 having a plurality of second electrode pads 210 is provided, and a conductive bump 23 is formed on each of the second electrode pads 220 .

[0050] The second electronic component 22 is an active component, a passive component or a combination thereof, wherein the active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor and an inductor. In this embodiment, the second electronic component 22 is a semiconductor chip or a wafer specification, and has a second active surface 22a and a second inactive surface 22b opposite to each other, and the second active surface 22a has a plurality of second electrode pads 220.

[0051] The conductive bump 23 includes a conductive column 230 for combining with the second electrode pad 220 and a conductive combining material 231 formed on the conductive column 230 .

[0052] In this embodiment, the conductive pillar 230 is a metal pillar such as a copper pillar, and the conductive bonding material 231 is a solder material, and its reflow temperature is about 200-270° C. Preferably, an under bump metallization (UBM) layer 232 can be formed between the conductive pillar 230 and the second electrode pad 220, so that the second electrode pad 220 can be bonded to the conductive pillar 230 through the under bump metallization layer 232. There are many types of composition styles of the conductive pillar 230, such as a composite metal pillar of titanium / copper / nickel, but it is not limited to the above.

[0053] Furthermore, the conductive pillar 230 is formed by a patterning process, such as electroplating, etching, deposition, sputtering or other suitable methods, without particular limitation.

[0054] like Figure 2D As shown, the second electronic component 22 is inserted into the positioning hole 200 of the positioning layer 20 on the first electronic component 21 with the conductive bump 23 on the second electrode pad 220 thereof, so that the second active surface 22a of the second electronic component 22 is close to the positioning layer 20, so that the second electronic component 22 is stacked above the first electronic component 21, wherein the overall height h1 of the conductive bump 23 is less than the depth h2 of the positioning hole 200, so the conductive bump 23 has not yet contacted the first electrode pad 210 in the positioning hole 200.

[0055] In this embodiment, the width d of the conductive bump 23 is smaller than the width r of the positioning hole 200 , so as to facilitate the conductive bump 23 to be inserted into the positioning hole 200 .

[0056] Furthermore, the positioning layer 20 can be thermally cured by a first heating process, so that the second electronic component 22 is fixedly stacked on the first electronic component 21 , wherein the operating temperature of the first heating process is less than or equal to 200° C.

[0057] like Figure 2E As shown, a second heating process is performed to heat the conductive bump 23 so that the conductive bonding material 231 expands and contacts the first electrode pad 210, so that the first electronic component 21 is electrically connected to the second electronic component 22 through the conductive bump 23, wherein the conductive bump 23 does not fill the positioning hole 200, so that there is a gap t between the conductive bump 23 and the wall of the positioning hole 200.

[0058] In this embodiment, the second heating process reflows the conductive bonding material 231 of the conductive bump 23 , wherein the operating temperature of the reflow operation is between 220° C. and 270° C., such as 230° C.

[0059] Therefore, the manufacturing method of the present invention mainly uses organic insulating materials to make the positioning layer 20, and configures the positioning holes 200 for the conductive bumps 23 to cooperate with, so as to facilitate the conductive bumps 23 to dock with the first electrode pads 210 of the first electronic component 21. Therefore, compared with the hybrid bonding technology of the prior art, the manufacturing method of the present invention does not need to overly consider the surface flatness and cleanliness of the positioning layer 20, so conventional leveling equipment and conventional cleaning equipment suitable for the organic insulating material can be selected to help reduce the manufacturing cost. It should be noted that in the manufacturing method of the present invention, the surface flatness and cleanliness of the positioning layer 20 still need to meet the requirements, but do not need to meet the specifications of the surface flatness and cleanliness of the existing passivation layer, so the manufacturing method of the present invention does not need to use special leveling equipment and special cleaning equipment.

[0060] Furthermore, the manufacturing method of the present invention connects the first electronic component 21 and the second electronic component 22 through the conductive bumps 23, and selects the conductive bumps 23 containing solder material and conventional reflow equipment. Therefore, compared with the prior art, the manufacturing method of the present invention does not need to use special heating equipment, thereby greatly reducing the manufacturing cost.

[0061] The present invention also provides a packaging structure 2 , comprising: a first electronic component 21 having a plurality of first electrode pads 210 , a positioning layer 20 disposed on the first electronic component 21 , and a second electronic component 22 having a plurality of second electrode pads 220 .

[0062] The positioning layer 20 has a plurality of positioning holes 200 exposed from each of the first electrode pads 210 .

[0063] The second electronic component 22 is disposed on the positioning layer 20 , wherein the plurality of second electrode pads 220 have a plurality of conductive bumps 23 accommodated in each of the positioning holes 200 , so that each of the conductive bumps 23 contacts each of the first electrode pads 210 , so that the second electronic component 22 is electrically connected to the first electronic component 21 through the plurality of conductive bumps 23 .

[0064] In one embodiment, a gap t is formed between the conductive bump 23 and the wall of the positioning hole 200 .

[0065] In one embodiment, the conductive bump 23 includes a conductive column 230 for combining with the second electrode pad 220 and a conductive bonding material 231 formed on the conductive column 230. For example, the conductive bonding material 231 is a solder material.

[0066] In one embodiment, the material forming the positioning layer 20 is an organic insulating material.

[0067] In summary, the packaging structure and the manufacturing method thereof of the present invention can reduce the manufacturing cost mainly through the design of the positioning layer and the conductive bumps, so the present invention can be widely used in electronic products.

[0068] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A packaging structure, comprising: A first electronic component having a plurality of first electrode pads; A positioning layer, which is disposed on the first electronic element and has a plurality of positioning holes exposing the plurality of first electrode pads; as well as The second electronic component is arranged on the positioning layer and has a plurality of second electrode pads, wherein the plurality of second electrode pads have a plurality of conductive bumps accommodated in the plurality of positioning holes so that each of the conductive bumps contacts each of the first electrode pads, so that the second electronic component is electrically connected to the first electronic component through the plurality of conductive bumps.

2. The packaging structure according to claim 1, wherein: There is a gap between the conductive bump and the wall surface of the positioning hole.

3. The packaging structure according to claim 1, wherein: The conductive bump includes a conductive column for combining with the second electrode pad and a conductive combining material formed on the conductive column.

4. The packaging structure according to claim 3, wherein: The conductive bonding material is a solder material.

5. The packaging structure according to claim 1, wherein: The material forming the positioning layer is an organic insulating material.

6. A method for making a packaging structure, comprising: Providing a first electronic component having a plurality of first electrode pads and a second electronic component having a plurality of second electrode pads; A positioning layer is formed on the first electronic element, and a plurality of conductive bumps are formed on the plurality of second electrode pads of the second electronic element, wherein the positioning layer has a plurality of positioning holes exposing the plurality of first electrode pads; Inserting the second electronic component into the plurality of positioning holes with the plurality of conductive bumps, so that the second electronic component is bonded to the positioning layer, and the plurality of conductive bumps do not contact the plurality of first electrode pads in the plurality of positioning holes; and The plurality of conductive bumps are heated to make each of the conductive bumps contact each of the first electrode pads, so that the second electronic component is electrically connected to the first electronic component through the plurality of conductive bumps.

7. The method for manufacturing a packaging structure according to claim 6, wherein: After being heated, a gap is formed between the conductive bump and the wall surface of the positioning hole.

8. The method for manufacturing a packaging structure according to claim 6, wherein: The conductive bump includes a conductive column for combining with the second electrode pad and a conductive combining material formed on the conductive column.

9. The method for manufacturing a packaging structure according to claim 8, wherein: The conductive bonding material is a solder material.

10. The method for manufacturing a packaging structure according to claim 6, wherein: The material forming the positioning layer is an organic insulating material.

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