Antenna device

Abstract

The invention discloses an antenna device which comprises a transparent substrate, a thin film circuit structure, a redistribution structure, a plurality of wafers and a plurality of antenna electrodes. The thin film circuit structure is located on the first face of the transparent substrate and comprises a first thin film conducting layer. The redistribution structure is located on the thin film circuit structure and comprises a first redistribution layer. The thickness of the first thin film conductive layer is smaller than that of the first redistribution layer. A plurality of wafers are bonded to the redistribution structure. The plurality of antenna electrodes are located on a second surface, opposite to the first surface, of the transparent substrate. Each antenna electrode is respectively overlapped on a corresponding one of the wafers.

Description

Technical Field

[0001] The invention relates to an antenna device. Background Art

[0002] In modern life, the application of wireless communication technology is ubiquitous. In major cities or public spaces, providing wireless local area networks has become a necessary facility, and many people even set up their own wireless networks at home. With the advancement of wireless communication technology, many manufacturers are committed to developing antenna devices with better performance. At present, antenna devices have complex circuit designs inside, involving various different signals. If the distance between signal lines is too close, the signals are likely to interfere with each other, which in turn affects the performance of the antenna device. Summary of the invention

[0003] At least one embodiment of the present invention provides an antenna device, including a transparent substrate, a thin film circuit structure, a redistribution structure, a plurality of chips, and a plurality of antenna electrodes. The thin film circuit structure is located on a first surface of the transparent substrate and includes a first thin film conductive layer. The redistribution structure is located on the thin film circuit structure and includes a first redistribution layer. The thickness of the first thin film conductive layer is less than the thickness of the first redistribution layer. A plurality of chips are bonded to the redistribution structure. A plurality of antenna electrodes are located on a second surface of the transparent substrate opposite to the first surface. Each antenna electrode overlaps a corresponding one of the chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a top view schematically showing an antenna device according to an embodiment of the present invention.

[0005] Figure 2 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0006] Figure 3 is a top view schematically showing an antenna device according to an embodiment of the present invention.

[0007] Figure 4 This is a radio frequency signal transmission method of some antenna devices according to some embodiments of the present invention.

[0008] Figure 5 This is a radio frequency signal transmission method of some other antenna devices according to some embodiments of the present invention.

[0009] Figure 6 It is a schematic diagram of data writing / selection of an antenna device according to some embodiments of the present invention.

[0010] Figure 7 is a functional block diagram of an antenna device according to an embodiment of the present invention.

[0011] Figure 8 is a top view schematically showing an antenna device according to an embodiment of the present invention.

[0012] Fig. 9 is a cross-sectional schematic diagram of an antenna device according to an embodiment of the present invention.

[0013] Fig.10 is a top view schematically showing an antenna device according to an embodiment of the present invention.

[0014] Fig.11 It is a schematic diagram of data writing / selection of an antenna device according to some embodiments of the present invention.

[0015] Fig.12 is a functional block diagram of an antenna device according to an embodiment of the present invention.

[0016] Fig.13 is a circuit diagram of an antenna unit according to an embodiment of the present invention.

[0017] Fig.14 It is a circuit diagram of a memory circuit of an antenna unit according to an embodiment of the present invention.

[0018] Fig.15 is a functional block diagram of an antenna device according to an embodiment of the present invention.

[0019] Fig.16 is a functional block diagram of another antenna device according to an embodiment of the present invention.

[0020] Fig.17 is a functional block diagram of yet another antenna device according to an embodiment of the present invention.

[0021] Wherein, the reference numerals are:

[0022] 1A, 1B, 1C, 1D: Antenna device

[0023] 10A, 10C, 10C-1, 10C-2: Antenna unit

[0024] 100:Transparent substrate

[0025] 110,110-1,110-2: Antenna electrode

[0026] 120:Conductive through hole in substrate

[0027] 132: Grounding electrode

[0028] 132h: Opening

[0029] 134:Joint structure

[0030] 140: Buffer layer

[0031] 200,200C: Thin film circuit structure

[0032] 210: first thin film conductive layer

[0033] 211,221,D1,D2,D3,D4,D5,CLK',CLK_1,CLK_N,CLK_M,CS_1,CS_N,Data_1,Data_N:Signal lines

[0034] 220: first dielectric layer

[0035] 230: second thin film conductive layer

[0036] 240: Second dielectric layer

[0037] 250: Gate dielectric layer

[0038] 300: Rewiring structure

[0039] 310: First redistribution layer

[0040] 320: Insulation layer

[0041] 330: Second redistribution layer

[0042] 334: RF signal line

[0043] 410A,410C,410C-1,410C-2: Wafer

[0044] 412,432: Conductive connection structure

[0045] 420: Bottom filling material

[0046] 430,430-1,430-2: Up / down converter

[0047] 510,520:Printed circuit board

[0048] 610,620,630: Flexible printed circuit board

[0049] 710:GPS / Gravity Meter Module

[0050] 720: Field Programmable Logic Gate Array Module

[0051] 730: Modulator / Demodulator Module

[0052] 740: Digital to Analog Converter

[0053] 750:Analog-to-digital converter

[0054] 760: Power module

[0055] DR, DR1, DR2: Gate drive circuit

[0056] G: Gate

[0057] HVS: horizontal polarization / vertical polarization selection line

[0058] H1,H2,V1,V2:Line

[0059] LH1, LH2: Conductive through holes

[0060] LT: Light Transmission Zone

[0061] M1,M2,M3,M4,M5,M6,T: Thin Film Transistor

[0062] MC:Memory Circuit Module

[0063] MC1: First memory circuit

[0064] MC2: Second memory circuit

[0065] NTR: Non-transparent region

[0066] P: Pad

[0067] PALNA: Power Amplifier and / or Low Loss Amplifier Module

[0068] PC, PC1, PC2: Phase control module

[0069] PD: Passive Components

[0070] PH1, PH2: Contact part

[0071] RX: Receive beamforming processing

[0072] S1: Side 1

[0073] S2: Side 2

[0074] SCC:Signal Control Circuit Module

[0075] SD: Source / Drain

[0076] SM: Semiconductor layer

[0077] SW, SW1, SW2: Power divider

[0078] T1: First switch element

[0079] T2: Second switch element

[0080] TC:Signal control and memory circuit

[0081] TR: Transparent Area

[0082] TX: Transmit beamforming processing

[0083] VGPS: Variable Gain Amplifier and Phase Shifter Module DETAILED DESCRIPTION

[0084] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0085] Figure 1 is a top view of an antenna device 1A according to an embodiment of the present invention. Figure 1 The antenna device 1A includes a transparent substrate 100 and a plurality of antenna units 10A disposed on the transparent substrate 100. The antenna units 10A are arranged in an array, for example. In this embodiment, at least one printed circuit board 510, 520 is electrically connected to the array of antenna units 10A through at least one flexible circuit board 610, 620, 630. Each antenna unit 10A includes an antenna electrode 110 and a chip 410A electrically connected to the antenna electrode 110.

[0086] In this embodiment, the antenna device 1A includes printed circuit boards 510, 520 and flexible circuit boards 610, 620, 630. The printed circuit boards 510, 520 are electrically connected to the redistribution structure ( Figure 1 The printed circuit boards 510 and 520 are further electrically connected to the array of antenna units 10A. In the present embodiment, a plurality of chips are disposed on each printed circuit board 510 and 520. In some embodiments, the printed circuit boards 510 and 520 include a modulator / demodulator (MODEM), a field programmable gate array (FPGA), a digital to analog converter (DAC), an analog to digital converter (ADC), a power module (Power Module), a global positioning system (GPS), a gravity meter (G-sensor), etc., and the above components can be disposed in one or more chips.

[0087] In some embodiments, a modulator / demodulator is a device for encoding a digital signal (encoder) and then modulating it onto an analog signal for transmission, and demodulating (demodulating) the received analog signal and then decoding (decoder) it into a digital signal.

[0088] The printed circuit boards 510 , 520 are electrically connected to the array of antenna units 10A through flexible printed circuit boards 610 , 620 , 630 .

[0089] The chip 410A includes a beam former integrated circuit (BFIC) or other active / passive components. The chip 410A can be used to perform transmit beamforming processing (TX) and / or receive beamforming processing (RX).

[0090] In this embodiment, the antenna device 1A further includes an up / down converter (UDC) 430. The up / down converter 430 may be a chip connected to the rewiring structure on the transparent substrate 100 or a circuit directly made on the transparent substrate 100. The printed circuit board 510 is electrically connected to the up / down converter 430 through the flexible circuit board 620 and the rewiring structure on the transparent substrate 100, and the up / down converter 430 is electrically connected to the chip 410A of the antenna unit 10A through the rewiring structure on the transparent substrate 100. For example, the printed circuit board 510 provides a relatively low frequency signal (e.g., an intermediate frequency (IF) or low frequency signal with a frequency lower than 10 GHz (e.g., lower than 2 GHz)), and the signal is transmitted to the up / down converter 430 through the flexible circuit board 620, and then the up / down converter 430 increases the signal frequency to a high frequency radio frequency signal (e.g., a frequency of 10 to 300 GHz). In this embodiment, since the up / down converter 430 is disposed on the transparent substrate 100 instead of on the printed circuit board 510 , there is no need to dispose an SMA high-frequency cable connector (SMA Connector) on the transparent substrate 100 for transmitting radio frequency signals.

[0091] The antenna device 1A includes a transparent region TR and a non-transparent region NTR. In some embodiments, the printed circuit boards 510 and 520 are disposed in the non-transparent region NTR, and the antenna electrode 110 and the chip 410A of the antenna unit 10A are disposed in the transparent region TR. In some embodiments, the up / down converter 430 is also disposed in the transparent region TR. In some embodiments, the antenna device 1A can be applied to windows of transportation vehicles (such as sunroofs of cars), windows of buildings, etc.

[0092] Figure 21 is a cross-sectional schematic diagram of an antenna device 1A according to an embodiment of the present invention. The transparent substrate 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. In some embodiments, the material of the transparent substrate 100 includes glass, quartz, organic polymer or other applicable materials. In some embodiments, the thickness of the transparent substrate 100 is 0.15 mm to 1.1 mm. For example, the thickness of the transparent substrate 100 is 0.5 mm, 0.7 mm or 1.1 mm.

[0093] The antenna electrode 110 is disposed on the first surface S1 of the transparent substrate 100 .

[0094] The ground electrode 132 is disposed on the second surface S2 of the transparent substrate 100. In the present embodiment, the ground electrode 132 has at least one opening 132h, and each opening 132h has a bonding structure 134. The bonding structure 134 is electrically connected to the antenna electrode 110 through the substrate conductive through hole 120. Therefore, the antenna signal of the antenna electrode 110 can be transmitted through the bonding structure 134 and the substrate conductive through hole 120. In other embodiments, the substrate conductive through hole 120 can be omitted, and the antenna signal of the antenna electrode 110 is transmitted between the antenna electrode 110 and the driving electrode (not shown) overlapping the opening 132h by radiation.

[0095] In some embodiments, the width of the ground electrode 132 is greater than or equal to the width of the antenna electrode 110 .

[0096] In some embodiments, the materials of the antenna electrode 110, the ground electrode 132, the bonding structure 134, and the substrate conductive through hole 120 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials.

[0097] In some embodiments, the method of forming the substrate conductive via 120 includes a glass modification process and a process of filling a conductive material. For example, the glass modification process includes first forming a through hole on the transparent substrate 100 using a laser, and then expanding the through hole using a wet etching process to form a through hole extending from the first surface S1 to the second surface S2. Finally, a conductive material is filled into the through hole to form the substrate conductive via 120.

[0098] In some embodiments, the method of forming the antenna electrode 110, the ground electrode 132, the bonding structure 134 and the substrate conductive through hole 120 includes first forming a seed layer on the first surface S1 of the transparent substrate 100 and the second surface S2 and in the through hole of the transparent substrate 100 by sputtering, chemical plating or other suitable processes. Then, a metal layer is formed on the seed layer by an electroplating process. The resulting seed layer and metal layer can be patterned by a lithography process and an etching process to obtain the antenna electrode 110, the ground electrode 132 and the bonding structure 134. In other embodiments, the seed layer can be omitted.

[0099] The buffer layer 140 is located on the transparent substrate 100, the ground electrode 132 and the bonding structure 134. In some embodiments, the buffer layer 140 includes a transparent material, such as an organic material (such as polyimide, polyethylene terephthalate, epoxy resin, etc.) or an inorganic material (such as silicon nitride, silicon oxide, etc.) or a combination of the above materials. In some embodiments, since the thickness of the antenna electrode 110, the ground electrode 132 and the bonding structure 134 is 2 microns to 10 microns. In order to achieve the effect of planarization, the thickness of the buffer layer 140 is preferably 2 microns to 15 microns, and the thickness of the buffer layer 140 is not less than the thickness of the ground electrode 132. For example, the thickness of the buffer layer 140 is 1.3 times the thickness of the ground electrode 132. In order to achieve this thickness to obtain the effect of planarization, the buffer layer 140 is preferably made of an organic material.

[0100] The thin film circuit structure 200 is located on the ground electrode 132 and the bonding structure 134. In this embodiment, the thin film circuit structure 200 is located on the buffer layer 140. In some embodiments, the overall thickness of the thin film circuit structure 200 is less than 10 micrometers.

[0101] The thin film circuit structure 200 includes a first thin film conductive layer 210, a first dielectric layer 220, a second thin film conductive layer 230, and a second dielectric layer 240 deposited in sequence. In some embodiments, at least one contact portion PH1 of the second thin film conductive layer 230 passes through the first dielectric layer 220 and is electrically connected to the first thin film conductive layer 210. In some embodiments, the thin film circuit structure 200 may further include more conductive layers and dielectric layers, and the present invention does not limit the number of conductive layers and dielectric layers in the thin film circuit structure 200.

[0102] In some embodiments, the materials of the first thin film conductive layer 210 and the second thin film conductive layer 230 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. The first thin film conductive layer 210 and the second thin film conductive layer 230 each have a single-layer structure or a multi-layer structure. For example, the first thin film conductive layer 210 and the second thin film conductive layer 230 each have a molybdenum / aluminum / molybdenum stacked structure, a titanium / aluminum / titanium stacked structure, or a stacked structure composed of other conductive materials.

[0103] In some embodiments, the material of the first dielectric layer 220 and the second dielectric layer 240 includes an organic polymer (such as polyimide, polyethylene terephthalate, etc.) or an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, hafnium oxide or other suitable materials or combinations of the above materials).

[0104] In some embodiments, before forming the second thin film conductive layer 230, a lithography process and an etching process are used to form an opening in the first dielectric layer 220 to expose the first thin film conductive layer 210, and then the second thin film conductive layer 230 is deposited in the opening to form a contact portion PH1 of the second thin film conductive layer 230 so that the second thin film conductive layer 230 contacts the first thin film conductive layer 210.

[0105] The redistribution structure 300 is located on the thin film circuit structure 200. In this embodiment, the redistribution structure 300 is located on the second dielectric layer 240. In some embodiments, the overall thickness of the redistribution structure 300 is 14 micrometers to 150 micrometers.

[0106] The redistribution structure 300 includes a first redistribution layer 310, an insulating layer 320, and a second redistribution layer 330 that are sequentially deposited. In some embodiments, at least one contact portion PH2 of the first redistribution layer 310 passes through the second dielectric layer 240 and is electrically connected to the second thin film conductive layer 230. In some embodiments, the first redistribution layer 310 and / or the second redistribution layer 330 are electrically connected to the ground electrode 132 and the bonding structure 134 through a conductive via LH1. The conductive via LH1 passes through the thin film circuit structure 200 and the buffer layer 140, and optionally passes through the insulating layer 320. In some embodiments, the second redistribution layer 330 is electrically connected to the first redistribution layer 310 through at least one conductive via LH2 in the insulating layer 320. The redistribution structure 300 may further include more conductive layers and insulating layers, and the present invention does not limit the number of conductive layers and insulating layers in the redistribution structure 300.

[0107] In some embodiments, the materials of the first redistribution layer 310 and the second redistribution layer 330 include copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), tungsten (W), conductive oxides (such as indium tin oxide, indium zinc oxide, etc.) or other suitable materials or combinations of the above materials. In some embodiments, the first redistribution layer 310 and the second redistribution layer 330 each include a seed layer and a metal layer formed thereon. The seed layer is formed by, for example, sputtering, chemical plating or other suitable methods, and the metal layer is formed by electroplating. In some embodiments, the seed layer can be omitted.

[0108] In some embodiments, the material of the insulating layer 320 includes an organic material (e.g., polyimide, polyethylene terephthalate, epoxy resin, etc.) or an inorganic material (e.g., silicon nitride, silicon oxide, etc.) or a combination of the above materials. In some embodiments, the method of forming the insulating layer 320 includes attaching a dry film to the first redistribution layer 310 or coating a liquid organic material (e.g., liquid polyimide (PI) material) on the first redistribution layer 310.

[0109] In some embodiments, the insulating layer 320 has high transmittance and low dissipation factor (Df). For example, the transmittance of the insulating layer 320 for light with a wavelength of 400nm to 800nm ​​is greater than or equal to 90%. In some embodiments, the dielectric constant (Dk) of the insulating layer 320 is less than 4, and the dielectric loss is less than 0.004.

[0110] In some embodiments, the first rewiring layer 310 of the rewiring structure 300 is configured to transmit a ground signal, and the second rewiring layer 330 is configured to transmit a chip power signal and a radio frequency (RF) signal (e.g., a radio frequency input signal (RF_in)). In some embodiments, the first thin film conductive layer 210 and the second thin film conductive layer 230 of the thin film circuit structure 200 include a digital signal line and an analog signal line, and the digital signal line and the analog signal line are respectively configured to transmit a digital signal and an analog signal for controlling the chip 410A or the circuit in the thin film circuit structure 200. Since the operating frequency of the digital signal and the analog signal transmitted in the thin film circuit structure 200 is relatively low, even if the film thickness of the first thin film conductive layer 210, the first dielectric layer 220, the second thin film conductive layer 230 and the second dielectric layer 240 in the thin film circuit structure 200 is relatively thin, the signal will not be significantly lost. In contrast, since the rewiring structure 300 is used to transmit a high frequency RF signal, the insulating layer 320 in the rewiring structure 300 needs to be thicker. Therefore, the thickness of the insulating layer 320 is greater than the thickness of each of the first dielectric layer 220 and the second dielectric layer 240. In some embodiments, the thickness of the insulating layer 320 is 10 microns to 60 microns. In some embodiments, the thickness of each of the first dielectric layer 220 and the second dielectric layer 240 is 0.03 microns to 1 micron, for example, 0.5 microns to 1 micron or 0.7 microns to 1 micron. In some embodiments, the thickness of each of the first thin film conductive layer 210 and the second thin film conductive layer 230 is less than the thickness of each of the first redistribution layer 310 and the second redistribution layer 330. In some embodiments, the thickness of each of the first thin film conductive layer 210 and the second thin film conductive layer 230 is 0.01 microns to 0.7 microns, for example, 0.01 microns to 0.3 microns or 0.01 microns to 0.05 microns. In some embodiments, the thickness of each of the first redistribution layer 310 and the second redistribution layer 330 is 2 microns to 10 microns.

[0111] In some embodiments, before forming the first redistribution layer 310, a lithography process and an etching process are used to form an opening in the second dielectric layer 240 to expose the second thin film conductive layer 230, and then the first redistribution layer 310 is deposited in the opening to form a contact portion PH2 of the first redistribution layer 310 so that the first redistribution layer 310 contacts the second thin film conductive layer 230.

[0112] In some embodiments, a laser drilling process is performed before forming the first redistribution layer 310 and / or before forming the second redistribution layer 330. For example, a laser drilling process is performed to form a laser hole, and then the first redistribution layer 310 or the second redistribution layer 330 is filled in the laser hole to form a conductive via LH1 or a conductive via LH2. In this embodiment, the conductive via LH2 passes through the insulating layer 320, and the second redistribution layer 330 contacts the first redistribution layer 310 through the conductive via LH2. The conductive via LH1 passes through the insulating layer 320, the second dielectric layer 240, the first dielectric layer 220 and the buffer layer 140, and the second redistribution layer 330 contacts the ground electrode 132 and the bonding structure 134 through the conductive via LH1. In this embodiment, since the formation methods of the contact portions PH1 and PH2, the formation methods of the conductive vias LH1 and LH2, and the formation methods of the sidewalls of the substrate conductive via 120 are different, the three have different sidewall inclination angles.

[0113] The chip 410A and the up / down converter 430 are bonded to the second redistribution layer 330. Each antenna electrode 110 overlaps a corresponding one of the chips 410A. In some embodiments, the width of the antenna electrode 110 is greater than or equal to the width of the chip 410A.

[0114] In some embodiments, the chip 410A and the up / down converter 430 are bonded to the second redistribution layer 330 through conductive connection structures 412 and 432, respectively. The conductive connection structures 412 and 432 are, for example, solder, conductive glue or other suitable structures. In some embodiments, the surface of the second redistribution layer 330 may be treated with electroless nickel immersion gold (ENIG), immersion silver plating, etc. to improve the yield of the chip bonding process. In some embodiments, before the chip bonding process, an organic material such as an organic solderability preservative (OSP) may be formed on the second redistribution layer 330, which can protect the metal pads from rusting (e.g., sulfide or oxidation) due to contact with air, so as to improve the yield of the chip bonding process.

[0115] An underfill material 420 is formed between the chip 410A and the second redistribution layer 330 and between the up / down converter 430 and the second redistribution layer 330. In some embodiments, the underfill material 420 may include a thermal interface material (TIM) to facilitate heat dissipation of the chip 410A and the up / down converter 430. For example, the thermal conductivity of the underfill material 420 is greater than 0.3 W / m K.

[0116] In this embodiment, compared to a single chip corresponding to multiple antenna units, each chip 410A corresponds to one antenna unit 10A, which can disperse the heat source and reduce the temperature of the antenna device 1A. Therefore, it is not necessary to install an additional heat dissipation structure on the chip 410A. In some embodiments, when the output power of the chip 410A is 60mW and 70mW, the surface temperature of the chip 410A is lower than 82 degrees Celsius and lower than 85.5 degrees Celsius, respectively.

[0117] By omitting the heat dissipation structure, the weight and thickness of the antenna device 1A can be greatly reduced while maintaining light transmittance, so that the antenna device 1A can be more easily combined with the vehicle sunroof.

[0118] In some embodiments, the chip 410A includes a beamformer integrated circuit (BFIC) or other active / passive components. In some embodiments, the beamformer integrated circuit includes a variable gain amplifier (VGA), a phase shifter (PS), a signal control and memory circuit, a power amplifier (PA) and / or a low noise amplifier (LNA). In some embodiments, the circuit including the active components can be disposed in the thin film circuit structure 200, thereby reducing the circuit required to be disposed in the chip 410A, thereby reducing the size of the chip 410A. For example, the signal control and memory circuit in the beamformer integrated circuit can be disposed in the thin film circuit structure 200. In some embodiments, by making the antenna unit 10A each include a BFIC, the signal path between the BFIC and the antenna electrode 110 can be shortened. If one BFIC provides a signal to multiple antenna electrodes 110, a longer signal path will need to be set, thereby reducing the light penetration area of ​​the antenna device. In other words, in this embodiment, by making each antenna unit 10A include one chip 410A, the area of ​​the light transmission region LT of the antenna device 1A can be increased.

[0119] The printed circuit board 510 is electrically connected to the redistribution structure 300 through the flexible circuit board 620. For example, the flexible circuit board 620 is bonded to the pad P of the second redistribution layer 330 through solder, conductive glue or other suitable structures. The up / down converter 430 is electrically connected to the printed circuit board 510 and the chip 410A. The up / down converter 430 can be used to convert a relatively low frequency signal from the printed circuit board 510 into a high frequency radio frequency signal (RF signal), and the high frequency radio frequency signal is further transmitted to the chip 410A for processing.

[0120] In some embodiments, the thin film circuit structure 200 and the redistribution structure 300 are configured to transmit various signals. For example, ground signals (such as AGND, DGND, RF_GND, etc.), power signals (such as AVDD, DVDD, etc.), radio frequency signals (RFsignal), radio frequency enable signals (RF_en), reference voltage signals (Vref), bias adjustment signals (Rbias), circuit control signals (such as CS, CLK, SDI, SDO, PDI, etc.), antenna signals (such as horizontal polarized electric field antenna signals (RF_out_H), vertical polarized electric field antenna signals (RF_out_V), etc.). In some embodiments, at least a portion of the power signals and circuit control signals are provided by the printed circuit board 510.

[0121] In some embodiments, the usage descriptions of various signals and the main transmission layers are shown in Table 1.

[0122] Table 1

[0123]

[0124]

[0125] In some embodiments, at least one of the first redistribution layer 310 and the second redistribution layer 330 includes one or more RF signal lines 334, and the RF signal lines 334 are configured to transmit RF signals to the chip 410A. For example, each RF signal line 334 is configured to transmit RF signals to a plurality of chips 410A arranged in a row (e.g., Figure 4 Alternatively, the RF signal line 334 is configured to transmit the RF signal to a plurality of chips 410A arranged in a row (such as Figure 5 shown).

[0126] In some embodiments, at least one of the first thin film conductive layer 210 and the second thin film conductive layer 230 includes one or more signal lines 211, 221 for transmitting low frequency signals. The low frequency signal may be an analog signal or a digital signal, and may include a power signal (e.g., DVDD), a radio frequency enable signal (RF_en), a reference voltage signal (Vref), a bias adjustment signal (Rbias), and a circuit control signal (e.g., CS, CLK, SDI, SDO, PDI, etc.). In some embodiments, the signal lines 211, 221 may also be referred to as analog signal lines and / or digital signal lines. The thickness of the radio frequency signal line 334 is greater than the thickness of the signal lines 211, 221.

[0127] Herein, low frequency signals refer to signals with operating frequencies below 500 MHz, while high frequency signals refer to signals with operating frequencies above 500 MHz (eg, 10 GHz to 300 GHz or 10 GHz to 500 GHz). High frequency signals include, for example, radio frequency signals (RFsignal) and antenna signals (RF_out).

[0128] Figure 3 FIG. 1 is a top view of an antenna device 1B according to an embodiment of the present invention. In this embodiment, the antenna device 1B includes a plurality of antenna units 10A arrayed on a transparent substrate 100 . Figure 3 The wafer 410A in the antenna unit 10A is shown, and other structures in the antenna unit 10A are omitted. Figure 3 In , a line segment can be used to represent a single signal line or multiple signal lines close together.

[0129] In some embodiments, the wavelength λ0 is the wavelength of the wireless signal that the antenna unit 10A is intended to receive or send in the air. The pitch d of each antenna unit 10A is approximately one-half of λ0. The range of the array of antenna units 10A can be defined by two parallel lines V1 and V2 and another two parallel lines H1 and H2. The parallel lines H1 and H2 are perpendicular to the lines V1 and V2.

[0130] Please refer to Figure 3 , the flexible circuit boards 610, 620, and 630 are respectively bonded to corresponding pads P, and are used to transmit signals provided by one or more printed circuit boards (not shown) to the thin film circuit structure and / or the redistribution structure located on the transparent substrate 100. In this embodiment, the flexible circuit boards 610 and 620 are located on one side of the transparent substrate 100, and the flexible circuit board 630 is located on the other side of the transparent substrate 100, but the present invention is not limited thereto. In other embodiments, the flexible circuit boards 610, 620, and 630 are located on the same side of the transparent substrate 100.

[0131] In some embodiments, the flexible circuit board 610 is used to transmit the digital signal and / or power signal provided by the printed circuit board to the chip 410A of the antenna unit 10A. The aforementioned digital signal and / or power signal is transmitted, for example, via the thin film circuit structure 200 (e.g., the digital signal line and / or power signal line in the thin film circuit structure 200).

[0132] The flexible printed circuit board 620 is used to transmit the intermediate frequency (IF) or low frequency signal provided by the printed circuit board to the rewiring structure and the up / down converter 430. The signal is converted into a radio frequency signal (RF signal) after being processed by the up / down converter 430 and transmitted to the chip 410A of the antenna unit 10A through the rewiring structure. The aforementioned radio frequency signal is transmitted, for example, through the second rewiring layer 330 of the rewiring structure 300 (for example, the radio frequency signal line in the second rewiring layer 330).

[0133] In some embodiments, the flexible circuit boards 610 and 620 are disposed between the lines V1 and V2, and the line H1 defines a side of the array of antenna units 10A close to the flexible circuit boards 610 and 620. In some embodiments, the RF signal line is designed to have equal impedance from the up / down converter 430 to the line H1 (i.e., each point from the up / down converter 430 to the line H1 has equal impedance). In some embodiments, the RF signal line is optionally distributed from the up / down converter 430 to different antenna units 10A via one or more power dividers (not shown).

[0134] The flexible circuit board 630 is used to transmit the power signal (e.g., AVDD) and the ground signal (e.g., AGND) provided by the printed circuit board to the chip 410A of the antenna unit 10A. For example, the power signal AVDD is transmitted through the second redistribution layer 330 of the redistribution structure 300 (e.g., the power signal line in the second redistribution layer 330). The ground signal AGND is transmitted through the first redistribution layer 310 of the redistribution structure 300 (e.g., the ground signal line in the second redistribution layer 330).

[0135] In some embodiments, in the array of antenna units 10A (ie, within the range between line H1 and line H2 ), the power signal line, digital signal line, and radio frequency signal line extend in a horizontal direction.

[0136] Figure 4 This is a radio frequency signal transmission method of an antenna device according to some embodiments of the present invention. Figure 5 This is a radio frequency signal transmission method of some other antenna devices according to some embodiments of the present invention. Figure 4 In the embodiment of FIG. 4 , each RF signal line 334 is configured to transmit RF signals to a plurality of chips 410A arranged in a row by serial feeding. Figure 5 In the embodiment of the present invention, each RF signal line 334 is configured to transmit the RF signal to a plurality of chips 410A arranged in a row in a daisy chain manner.

[0137] Please refer to Figure 4 and Figure 5The chip 410A adopts, for example, a time division duplex (TDD) technology or a frequency division duplex (FDD) technology.

[0138] When the chip 410A adopts FDD technology, the transmit beamforming processing TX and the receive beamforming processing RX are performed by different antenna unit arrays, for example, where the chip 410A in one antenna unit array performs the transmit beamforming processing TX of the RF signal, and the chip 410A in another antenna unit array performs the receive beamforming processing RX.

[0139] When the chip 410A adopts the TDD technology, when performing the transmit beamforming process TX, the RF signal line 334 provides the RF signal to the chip 410A. When performing the receive beamforming process RX, the chip 410A provides the RF signal to the RF signal line 334. In the TDD technology, the chip 410A in the same antenna element array performs the transmit beamforming process TX and the receive beamforming process RX at different times.

[0140] Figure 6 FIG. 1 is a schematic diagram of data writing / selection of an antenna device 1A according to some embodiments of the present invention. The antenna units 10A are arranged in an array consisting of N rows and M columns.

[0141] The signal lines Data_1 to Data_N are electrically connected to the first to N-th rows of antenna units 10A (e.g., wafer 410A of antenna units 10A), respectively. The signal lines CLK_1 to CLK_N are electrically connected to the first to N-th rows of antenna units 10A (e.g., wafer 410A of antenna units 10A), respectively. The signal lines CS_1 to CS_N are electrically connected to the first to N-th rows of antenna units 10A (e.g., wafer 410A of antenna units 10A), respectively.

[0142] In some embodiments, the signal lines Data_1 to Data_N are used to transmit at least one of the circuit control signals SDI and SDO, the signal lines CLK_1 to CLK_N are used to transmit the circuit control signal CLK, and the signal lines CS_1 to CS_N are used to transmit the circuit control signal CS.

[0143] In this embodiment, data is written / selected to M columns of antenna units 10A in sequence according to step 1, step 2, step 3, ... to step M, which can be achieved by the circuit control signal CLK (i.e., clock signal) transmitted by the signal lines CLK_1 to CLK_N. For example, after the first column of antenna units 10A are simultaneously turned on by the signal lines CLK_1 to CLK_N so that the signal lines Data_1 to Data_N transmit signals to the first column of antenna units 10A, the signal lines CLK_1 to CLK_N then transmit signals to the second column of antenna units 10A, and the second column of antenna units 10A are turned on so that the signal lines Data_1 to Data_N transmit signals to the second column of antenna units 10A.

[0144] After executing step M, the antenna array is activated using a clock signal provided by another signal line CLK_M+1 (not shown) and a radio frequency enable signal RF_en provided by a radio frequency enable signal line (not shown) to generate radiation.

[0145] In some embodiments, the circuit control signals are transmitted to all chips 410A in a serial feed manner. The circuit control signals transmitted to the chip 410A include, for example, SDI, SDO, CLK, CS, etc.

[0146] In some embodiments, the circuit control signal PDI, the RF input signal RF_in, the RF enable signal RF_en, the power signal AVDD, the power signal DVDD, the ground signal AGND and the ground signal RF_GND are input to all chips 410A in parallel.

[0147] Figure 7 FIG. 4 is a functional block diagram of an antenna device 1A according to an embodiment of the present invention. In this embodiment, each antenna unit 10A includes a chip 410A, and the chip 410A includes a BFIC.

[0148] In this embodiment, ground signals (e.g., AGND, RF_GND, etc.), power signals (e.g., AVDD, DVDD, etc.), radio frequency signals (RFsignal), radio frequency enable signals (RF_en), reference voltage signals (Vref), and various circuit control signals (e.g., CS, CLK, SDI, SDO, PDI, etc.) are connected to chip 410A.

[0149] In this embodiment, the circuit control signal is provided to the signal control circuit module SCC and the memory circuit module MC in the chip 410A. The signal control circuit module SCC provides a signal to the variable gain amplifier and phase shifter module VGPS.

[0150] In this embodiment, the radio frequency signal RFsignal is processed by a power divider and then provided to a variable gain amplifier and phase shifter module VGPS. The variable gain amplifier and phase shifter module VGPS provides a signal to a power amplifier and / or a low loss amplifier module PALNA.

[0151] The power amplifier and / or low-loss amplifier module PALNA provides a first antenna signal (eg, a horizontally polarized electric field antenna signal (RF_out_H)) and a second antenna signal (eg, a vertically polarized electric field antenna signal (RF_out_V)) to the antenna electrode 110 .

[0152] In some embodiments, other passive components PD, such as inductors, capacitors and / or resistors, may be additionally disposed in the antenna unit 10A. The passive components PD are connected to the power amplifier and / or low-loss amplifier module PALNA of the chip 410A.

[0153] Figure 8 1 is a top view of an antenna device 1C according to an embodiment of the present invention. It must be noted that: Figure 8 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0154] Please refer to Figure 8 , the antenna device 1C includes a transparent substrate 100 and a plurality of antenna units 10C disposed on the transparent substrate 100. The antenna units 10C are arranged in an array, for example. In the present embodiment, at least one printed circuit board 510, 520 is electrically connected to the array of antenna units 10C through at least one flexible circuit board 610, 620, 630. Each antenna unit 10C includes an antenna electrode 110 and a chip 410C electrically connected to the antenna electrode 110. In the present embodiment, the gate drive circuit DR connects a plurality of antenna units 10C in series. For example, the gate drive circuit DR provides a gate signal to a signal control and memory circuit in the antenna unit 10C, and the signal control and memory circuit provides a signal to the chip 410C.

[0155] Fig. 9 is a top view of an antenna device 1C according to an embodiment of the present invention. Fig. 9 The antenna device 1C includes a transparent substrate 100 and a plurality of antenna units 10C disposed on the transparent substrate 100. The antenna units 10C are arranged in an array, for example, and light transmission areas LT are provided between the antenna units 10C.

[0156] The thin film circuit structure 200C includes a plurality of thin film transistors T. For example, in this embodiment, a gate dielectric layer 250 is further provided between the first dielectric layer 220 and the buffer layer 140. A plurality of semiconductor layers SM are further provided between the gate dielectric layer 250 and the buffer layer 140.

[0157] The first thin film conductive layer 210 is located on the gate dielectric layer 250 and includes a gate G overlapping the semiconductor layer SM. The first dielectric layer 220 covers the gate G. The second thin film conductive layer 230 is located on the first dielectric layer 220 and includes a plurality of source / drain electrodes SD. In the present embodiment, each thin film transistor T includes a corresponding semiconductor layer SM, a corresponding gate G, and a corresponding source / drain electrode SD. In the present embodiment, the thin film transistor T is a top gate thin film transistor, but the present invention is not limited thereto. In other embodiments, the thin film transistor T is a bottom gate thin film transistor, a double gate thin film transistor, or other types of thin film transistors.

[0158] The thin film transistor T is electrically connected to the chip 410C and the signal line 221 (eg, a digital signal line) in the thin film circuit structure 200C. The thickness of the signal line 221 is smaller than the thickness of the RF signal line 334. The signal line 221 is used to transmit any digital signal described in the previous embodiments.

[0159] Fig.10 1 is a top view schematic diagram of an antenna device 1D according to an embodiment of the present invention. It must be noted here that: Fig.10 The implementation examples are used Figure 3 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0160] In this embodiment, the antenna device 1D includes a plurality of antenna units 10C arrayed on a transparent substrate 100 . Fig.10 The wafer 410C in the antenna unit 10C is shown, and other structures in the antenna unit 10C are omitted. Fig.10 In , a line segment can be used to represent a single signal line or multiple signal lines close together.

[0161] In some embodiments, the flexible circuit board 610 is used to transmit the digital signal and / or power signal provided by the printed circuit board to the chip 410C of the antenna unit 10C. The aforementioned digital signal and / or power signal is transmitted, for example, via the thin film circuit structure 200 (e.g., the digital signal line and / or power signal line in the thin film circuit structure 200). In addition, the flexible circuit board 610 is also electrically connected to the gate drive circuit DR, and provides a clock signal (or gate signal) to the antenna unit 10C through the gate drive circuit DR and a plurality of signal lines CLK' (or clock signal lines or gate signal lines).

[0162] In some embodiments, the RF signal line is optionally distributed to different rows of antenna units 10C via one or more power dividers SW from the up / down converter 430. The RF signal line is designed with equal impedance from the power divider SW to line H1 (i.e., each point from the power divider SW to line H1 has equal impedance).

[0163] Fig.11 FIG. 1 is a schematic diagram of data writing / selection of an antenna device 10C according to some embodiments of the present invention. The antenna units 10C are arranged in an array consisting of N rows and M columns.

[0164] The signal lines Data_1 to Data_N are electrically connected to the antenna units 10C in the first row to the antenna units 10C in the Nth row (eg, signal control and memory circuits of the antenna units 10C), respectively.

[0165] In some embodiments, the signal lines Data_1 to Data_N are used to transmit at least one of the circuit control signals SDI and SDO.

[0166] The signal lines CLK_1 to CLK_M are electrically connected to the first to Mth columns of antenna units 10C (eg, signal control and memory circuits of the antenna units 10C), respectively.

[0167] In this embodiment, according to step 1, step 2, step 3 ... to step M, data is written / selected to M columns of antenna units 10C in sequence. This can be achieved by the clock signal transmitted by the signal line CLK_1 to the signal line CLK_M (in some embodiments, it can be a gate signal for controlling a transistor). The signal line CLK_1 to the signal line CLK_M are electrically connected to the gate drive circuit DR (please refer to Fig.10 ).

[0168] After executing step M, the antenna array is activated using a clock signal provided by another signal line CLK_M+1 (not shown) and a radio frequency enable signal RF_en provided by a radio frequency enable signal line (not shown) to generate radiation.

[0169] In some embodiments, the circuit control signal is transmitted to the antenna units 10C in the same row along the horizontal direction. The aforementioned circuit control signal includes, for example, SDI, SDO, CLK, CS, etc.

[0170] The clock signal (which may be referred to as a gate signal in some embodiments) is input to the antenna units 10C in the same column (eg, the signal control and memory circuit or chip 410C of the antenna unit 10C) along the vertical direction.

[0171] In some embodiments, the circuit control signal PDI, the RF enable signal RF_en, the RF input signal RF_in, the power signal AVDD, the power signal DVDD, the ground signal AGND and the ground signal RF_GND are input to all chips 410C in parallel.

[0172] Fig.12 1 is a functional block diagram of an antenna device 1C according to an embodiment of the present invention. In this embodiment, each antenna unit 10C includes a chip 410C and a phase control module PC (including, for example, signal control and memory circuits). The chip 410C includes a BFIC. The phase control module PC is disposed in a thin film circuit structure 200C (see Fig. 9 ) and includes multiple thin film transistors T (or called switching elements).

[0173] In this embodiment, ground signals (such as AGND, RF_GND, etc.), power signals (such as AVDD, etc.), radio frequency signals (RFsignal) and reference voltage signals (Vref) are connected to the chip 410C, and various circuit control signals (such as SDI, SDO, PDI, etc.), radio frequency enable signals (RF_en) and power signals (such as DVDD, etc.) are connected to the phase control module PC. The signal line CLK' is respectively connected to the phase control modules PC of the antenna units 10C in different columns.

[0174] In this embodiment, the circuit control signal is provided to the phase control module PC. The phase control module PC provides a signal to the chip 410C, such as the variable gain amplifier and phase shifter module VGPS in the chip 410C.

[0175] In this embodiment, the radio frequency signal RFsignal is processed by a divider and then provided to the variable gain amplifier and phase shifter module VGPS. The variable gain amplifier and phase shifter module VGPS provides a signal to the power amplifier and / or the low loss amplifier module PALNA.

[0176] The power amplifier and / or low-loss amplifier module PALNA provides a first antenna signal (eg, a horizontally polarized electric field antenna signal (RF_out_H)) and a second antenna signal (eg, a vertically polarized electric field antenna signal (RF_out_V)) to the antenna electrode 110 .

[0177] In some embodiments, other passive components PD, such as inductors, capacitors and / or resistors, may be additionally disposed in the antenna unit 10C. The passive components are connected to the power amplifier and / or low-loss amplifier module PALNA of the chip 410C.

[0178] Fig.13 is a circuit diagram of an antenna unit according to an embodiment of the present invention. It must be noted here that: Fig.13 The implementation examples are used Fig.12 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0179] Please refer to Fig.13 In this embodiment, the signal control and memory circuit TC (ie Fig.12 The phase control module PC) includes a plurality of first switch elements T1, a plurality of first memory circuits MC1, a plurality of second switch elements T2, and a plurality of second memory circuits MC2. The first switch elements T1 are electrically connected to the first memory circuits MC1, respectively. Each second switch element T2 is electrically connected to a corresponding one of the first memory circuits MC1 and a corresponding one of the second memory circuits MC2. The second memory circuit MC2 of the signal control and memory circuit TC is electrically connected to the chip 410C.

[0180] The signal lines D1 to D5 are connected to the plurality of first switch elements T1. In some embodiments, each of the signal lines D1 to D5 is connected to two corresponding first switch elements T1. The horizontal polarization / vertical polarization selection line HVS is electrically connected to the gates of the first switch elements T1 and provides a gate signal to the gates of the first switch elements T1 to control the switching of the first switch elements T1. In some embodiments, Fig.13Among the 10 first switch elements T1 shown, the top 5 first switch elements T1 correspond to the first memory circuit MC1 associated with the horizontal polarization electric field antenna signal (RF_out_H), and the bottom 5 first switch elements T1 correspond to the first memory circuit MC1 associated with the vertical polarization electric field antenna signal (RF_out_V). By making the top 5 first switch elements T1 and the bottom 5 first switch elements T1 include transistors of different types, for example, the top 5 first switch elements T1 are one of n-type transistors and p-type transistors, and the bottom 5 first switch elements T1 are the other of n-type transistors and p-type transistors. Through such a design, the top 5 first switch elements T1 and the bottom 5 first switch elements T1 have different conduction (on) voltages. In some embodiments, the number of first switch elements T1 can be adjusted according to demand.

[0181] The RF enable signal line is electrically connected to the gate of the second switch element T2 , and provides the RF enable signal RF_en to the gate of the second switch element T2 to control the switching of the second switch element T2 .

[0182] In some embodiments, the horizontal polarization / vertical polarization selection line HVS, the RF enable signal line, the signal lines D1 to D5, the first switch element T1, the first memory circuit MC1, the second switch element T2 and the second memory circuit M1 are disposed in the thin film circuit structure 200C (please refer to Fig. 9 For example, at least one of the first thin-film conductive layer 210 and the second thin-film conductive layer 220 includes a horizontal polarization / vertical polarization selection line HVS and a radio frequency enabling signal line.

[0183] In some embodiments, the circuit control signal CLK (i.e., clock signal) provided by the signal line CLK' is used to control the storage of the first memory circuit MC1, and the first memory circuit MC1 can be used to preload the data to be written next. The radio frequency enable signal RF_en is used to control the second memory circuit MC2, and the second memory circuit MC2 is used to maintain the current radiation state. Fig.13 The signal line CLK' corresponds to Fig.11 The gate driving circuit is electrically connected to the first memory circuit MC1 and the second memory circuit MC2 through the signal line CLK_1 to the signal line CLK_M.

[0184] In some embodiments, the circuit layout of each of the first memory circuit MC1 and the second memory circuit MC2 is as follows: Fig.14Each memory circuit includes thin film transistors M1, M2, M3, M4, M5, and M6. The thin film transistors M1, M2, M3, M4, M5, and M6 are disposed in the thin film circuit structure 200C (see Fig. 9 ). In some embodiments, a power signal DVDD is provided to the thin film transistors M2 and M4 of the memory circuit, and a circuit control signal CLK (i.e., a clock signal) is provided to the thin film transistors M5 and M6 of the memory circuit. In some embodiments, the thin film transistors M1 and M3 are connected to a ground signal.

[0185] Fig.15 7 is a functional block diagram of an antenna device according to an embodiment of the present invention. The non-transparent region NTR of the antenna device includes a global positioning system / gravimeter module 710, a field programmable logic gate array module 720, a modulator / demodulator module 730, a digital-to-analog converter 740, an analog-to-digital converter 750, and a power module 760. The global positioning system / gravimeter module 710, the field programmable logic gate array module 720, the modulator / demodulator module 730, the digital-to-analog converter 740, the analog-to-digital converter 750, and the power module 760 are, for example, disposed on a printed circuit board (e.g., Figure 1 On the printed circuit boards 510, 520 shown.

[0186] In this embodiment, since the antenna device is installed on a vehicle, the vehicle computer system can provide a signal to the modulator / demodulator module 730 , and the vehicle power system can provide a DC power to the power module 760 .

[0187] Data / circuit control signals are transmitted between the GPS / gravity meter module 710 and the field programmable logic gate array module 720, between the GPS / gravity meter module 710 and the modulator / demodulator module 730, between the field programmable logic gate array module 720 and the digital-to-analog converter 740, and between the field programmable logic gate array module 720 and the analog-to-digital converter 750.

[0188] In some embodiments, the FPGA module 720 can perform digital signal processing and timing management. The FPGA module 720 can transmit data to the DAC 740 in the form of digital signals, or receive data from the ADC 750 in the form of digital signals.

[0189] The power module 760 provides a DC signal to the field programmable logic gate array module 720, the modulator / demodulator module 730, the digital-to-analog converter 740, and the analog-to-digital converter 750. In addition, the power module 760 also provides a DC signal to the up / down converter 430 and the antenna unit 10C disposed in the transparent region TR. The DC signal includes, for example, a ground signal (such as AGND, DGND, RF_GND, etc.), a power signal (such as AVDD, DVDD, etc.), a reference voltage signal (Vref), or other similar signals.

[0190] The transparent region TR of the antenna device includes a gate drive circuit DR, an up / down converter 430, a power divider SW1, and an antenna unit 10C. In this embodiment, the antenna unit 10C includes a chip 410C, a phase control module PC (e.g., Fig.13 The signal control and memory circuit TC), the power divider SW2 and the antenna electrode 110 are shown.

[0191] The up / down converter 430 receives the intermediate frequency signal from the digital-to-analog converter 740, or transmits the intermediate frequency signal to the analog-to-digital converter 750. In some embodiments, the frequency of the intermediate frequency signal is less than 10 GHz. The up / down converter 430 can convert the intermediate frequency signal into a high-frequency radio frequency signal, or convert the high-frequency radio frequency signal into an intermediate frequency signal. In some embodiments, the frequency of the radio frequency signal is greater than or equal to 10 GHz.

[0192] The RF signal is transmitted to the chip 410C via the power divider SW1 and processed in the chip 410C. It must be noted here that Fig.15 The chip 410C in the chip adopts TDD technology and can perform transmit beamforming processing TX and receive beamforming processing RX.

[0193] The gate drive circuit DR provides a circuit control signal (e.g., a gate signal or a clock signal) to the phase control module PC, and the field programmable logic gate array module 720 provides a circuit control signal (e.g., a clock signal) to the phase control module PC. The phase control module PC outputs the circuit control signal to the chip 410C and performs a transmit beamforming process TX and a receive beamforming process RX. In some embodiments, the gate drive circuit DR and the phase control module PC may be disposed in a thin film circuit structure 200C (see Fig. 9 ). In some embodiments, the phase control module PC can be integrated into the chip 410C. In some embodiments, the gate drive circuit DR can be disposed in other chips and bonded to the rewiring structure 300 (please refer to Fig. 9 ).

[0194] The power divider SW2 distributes the radio frequency signal between the chip 410C and the antenna electrode 110. In some embodiments, the power divider SW2 can be integrated into the chip 410C or disposed in the thin film circuit structure 200C (see Fig. 9 )middle.

[0195] In this embodiment, the GPS / gravimeter module 710, the field programmable logic gate array module 720, the modulator / demodulator module 730, the digital-to-analog converter 740, the analog-to-digital converter 750, and the power module 760 are disposed in the non-transparent region NTR, but the present invention is not limited thereto. In other embodiments, one or more of the GPS / gravimeter module 710, the field programmable logic gate array module 720, the modulator / demodulator module 730, the digital-to-analog converter 740, the analog-to-digital converter 750, and the power module 760 are disposed in the transparent region TR, that is, disposed on the transparent substrate 100, such as Fig.16 shown.

[0196] Fig.17 is a functional block diagram of another antenna device according to an embodiment of the present invention. It must be noted here that Fig.17 The implementation examples are used Fig.15 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0197] Fig.17 The antenna device and Fig.15 The difference between the antenna devices is: Fig.17 The chip in the antenna device adopts FDD technology, and uses different antenna unit arrays to perform transmit beamforming processing TX and receive beamforming processing RX.

[0198] In the array formed by the antenna unit 10C-1, the up / down converter 430-1 provides a radio frequency signal to the chip 410C-1 and performs a transmit beamforming process TX. The antenna 110-1 outputs a corresponding radiation signal. In some embodiments, the gate drive circuit DR1 provides a circuit control signal (such as a gate signal or a clock signal) to the phase control module PC1, and the field programmable logic gate array module 720 provides a circuit control signal (such as a clock signal) to the phase control module PC1. The phase control module PC1 outputs the circuit control signal to the chip 410C-1 and performs a transmit beamforming process TX.

[0199] In the array formed by the antenna unit 10C-2, the antenna 110-2 receives the corresponding radiation signal. The chip 410C-2 performs the receive beamforming process RX. The up / down converter 430-2 receives the RF signal from the chip 410C-2. In some embodiments, the gate drive circuit DR2 provides a circuit control signal (such as a gate signal or a clock signal) to the phase control module PC2, and the field programmable logic gate array module 720 provides a circuit control signal (such as a clock signal) to the phase control module PC2. The phase control module PC2 outputs the circuit control signal to the chip 410C-2 and performs the receive beamforming process RX.

[0200] In some embodiments, the array formed by the antenna units 10C- 1 and the array formed by the antenna units 10C- 2 may be arranged in different areas on the same transparent substrate 100 , or may be arranged on two transparent substrates 100 respectively.

[0201] In summary, the antenna device of the present invention includes a thin film circuit structure, and the thin film conductive layer in the thin film circuit structure can be used to transmit circuit control signals. Since the thickness of the thin film conductive layer is thin, the overall thickness of the antenna device can be reduced. In addition, since each antenna unit includes a chip, the heat source of the antenna device can be dispersed.

[0202] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. An antenna device, characterized in that: include: a transparent substrate; A thin film circuit structure is located on a first surface of the transparent substrate and includes a first thin film conductive layer; a redistribution structure located on the thin film circuit structure and comprising a first redistribution layer, wherein the thickness of the first thin film conductive layer is less than the thickness of the first redistribution layer; A plurality of chips bonded to the redistribution structure; and A plurality of antenna electrodes are located on a second surface of the transparent substrate opposite to the first surface, and each of the antenna electrodes overlaps a corresponding one of the chips.

2. The antenna device according to claim 1, characterized in that The thin film circuit structure includes a signal control and memory circuit, wherein the signal control and memory circuit is electrically connected to one of the chips.

3. The antenna device according to claim 2, characterized in that The signal control and memory circuit includes a plurality of first switch elements and a plurality of first memory circuits, and the first switch elements are electrically connected to the first memory circuits respectively.

4. The antenna device according to claim 3, characterized in that One of the gate driving circuits is electrically connected to the first memory circuits.

5. The antenna device according to claim 3, characterized in that The signal control and memory circuit further includes a plurality of second switch elements and a plurality of second memory circuits, each of the second switch elements being electrically connected to a corresponding one of the first memory circuits and a corresponding one of the second memory circuits.

6. The antenna device according to claim 5, characterized in that The thin film circuit structure further includes a second thin film conductive layer, wherein one of the first thin film conductive layer and the second thin film conductive layer includes a radio frequency enabling signal line, and the radio frequency enabling signal line is electrically connected to the gates of the second switch elements.

7. The antenna device according to claim 1, characterized in that Also includes: At least one printed circuit board and at least one flexible circuit board, the at least one printed circuit board is electrically connected to the redistribution structure through the at least one flexible circuit board, wherein the at least one printed circuit board is arranged in a non-transparent area of ​​the antenna device, and the antenna electrodes and the chips are arranged in a transparent area of ​​the antenna device.

8. The antenna device according to claim 7, characterized in that The at least one printed circuit board includes a field programmable logic gate array module.

9. The antenna device according to claim 7, characterized in that: Also includes: An up / down converter is electrically connected to the at least one printed circuit board and the chips, and the up / down converter is disposed in the transparent area.

10. The antenna device according to claim 1, wherein: The redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more RF signal lines, wherein the one or more RF signal lines are configured to transmit RF signals to multiple of the chips via a daisy chain.

11. The antenna device according to claim 1, wherein: The redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more RF signal lines, wherein the one or more RF signal lines are configured to transmit RF signals to multiple of the chips via serial feeding.

12. The antenna device according to claim 1, wherein: The invention further comprises a field programmable logic gate array module which is arranged on the transparent substrate.

13. The antenna device according to claim 1, wherein: The thin film circuit structure includes a second thin film conductive layer, wherein at least one of the first thin film conductive layer and the second thin film conductive layer includes one or more digital signal lines, and the redistribution structure further includes a second redistribution layer, wherein at least one of the first redistribution layer and the second redistribution layer includes one or more RF signal lines, wherein the thickness of the one or more RF signal lines is greater than the thickness of the one or more digital signal lines, and wherein the one or more RF signal lines are configured to transmit RF signals to multiple of the chips.

14. The antenna device according to claim 13, characterized in that The one or more digital signal lines are configured to transmit digital signals to the plurality of chips.

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