Balancing temperature of power supply stages of multiphase switching converter

Abstract

A power stage of a multiphase switching converter includes a pair of power switches, a temperature sensor, a comparator, and a current sensing block. The power switch is operated by a phase controller of the converter to be turned on or off to drive an inductor current through the inductor. The temperature sensor generates a temperature signal indicative of a temperature of the power stage. The temperature signals are coupled to be indicated on a common path indicating to the phase controller a first temperature derived from all the temperature signals from all the working power supply stages of the converter. The comparator compares the temperature signal with the magnitude of the first temperature. If the result indicates that the magnitudes are not equal, the current sensing block reports a first magnitude different from the actual magnitude of inductor current to the phase controller to tend the temperature to the first temperature.

Description

[0001] priority

[0002] This patent application is related to and claims priority to the co-pending provisional Indian patent application titled “SPS Dynamic Thermal Balancing”, serial number 202341077645, filed on November 15, 2023, attorney file number AURA-349-INPR, which is incorporated herein in its entirety to the extent not inconsistent with the description herein. Technical Field

[0003] Embodiments of the present invention relate to power supply circuits, and more particularly, to balancing the temperature of power stages of a multi-phase switching converter. Background Art

[0004] A switching converter refers to a component known in the related art that generates a regulated direct current (DC) voltage from an input power source by using one or more switches. Typically, a switching converter converts the voltage of an input power source (input supply voltage) into a pulse voltage by operating a switch, and then uses capacitors, inductors, and other components to smooth the pulse voltage to generate a regulated DC voltage. By opening and closing switches (e.g., metal oxide semiconductor field effect transistors (MOSFETs)), power is supplied from the input terminal to the output terminal to generate and regulate the desired voltage. As known in the related art, switching converters are used in components such as regulated power supplies, which in turn are used in devices such as computers and mobile phones.

[0005] A switching converter typically includes a pair of switches that drive an inductor. Each power switch (switch) is typically implemented as a transistor (e.g., a metal oxide semiconductor field effect transistor (MOSFET)), and the switches are connected in series between an input supply voltage and a reference terminal (e.g., ground). The switch that is coupled closer to the input voltage (the converter's input supply) is called the high-side switch, while the other is called the low-side switch. The switches are operated by a control circuit that turns on the transistors for consecutive non-overlapping durations so that the currently turned-on switch drives the inductor for the corresponding duration.

[0006] The multiphase switching converter includes a plurality of such switch pairs, and associated circuits for each switch pair. As is known in the relevant art, each switch pair is typically operated in a corresponding phase of a phase sequence, wherein these switch pairs operate together to generate a desired regulated voltage (power rail) and can support higher load currents with higher efficiency and provide other advantages. Each of these switch pairs and associated circuits are referred to as a power supply stage of the power supply rail provided by the multiphase switching converter. The phase controller is used to control the specific time when each power supply stage of the power supply rail generates the desired output voltage.

[0007] All power stages of a track are typically expected to operate at substantially the same temperature. However, one or more factors may cause the temperatures of the power stages to be (substantially) unequal. Therefore, it is desirable to balance the temperatures of the power stages. Balancing typically refers to equalizing the temperatures of the operating power stages or bringing the temperatures of the operating power stages within a desired variation band, e.g., a maximum temperature variation of 5% among all operating power stages.

[0008] Some aspects of the invention relate to balancing the temperature of power stages of a multi-phase switching converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the present invention will be described with reference to the accompanying drawings which are briefly described below.

[0010] Figure 1 is a block diagram of an example system in which aspects of the invention may be implemented.

[0011] Figure 2 is a block diagram showing details of a voltage regulation module (VRM) in an embodiment of the present invention.

[0012] Figure 3 is a diagram showing implementation details of relevant parts of a temperature monitor block according to the prior art.

[0013] Figure 4 is a diagram showing implementation details of a power supply stage in an embodiment of the present invention.

[0014] Figure 5 is a diagram showing implementation details of a temperature monitor for a power supply stage in an embodiment of the present invention.

[0015] Figure 6 is a diagram showing an example implementation of a portion of a current sensing block of a power stage in an embodiment of the present invention.

[0016] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0017] 1. Overview

[0018] The power stage provided according to several aspects of the present invention is one of a plurality of power stages that jointly generate a supply voltage on a power rail of a multiphase switching converter. A phase controller of the multiphase switching converter controls the operation of the plurality of power stages. The power stage includes a high-side power switch and a low-side power switch to periodically drive an inductor, respectively, in a first interval and a second interval based on a control signal received from the phase controller. The actual magnitude of the current flowing through the inductor is determined by the conduction duration of the high-side switch and the low-side switch set by the control signal.

[0019] The power stage also includes a temperature sensor, a comparator, and a current sensing block. The temperature sensor generates a temperature signal indicating the temperature of the power stage. The temperature is positively correlated to the actual magnitude of the current through the inductor. The temperature signal is coupled to be indicated on a common path that indicates to the phase controller a first temperature derived from all temperature signals provided by the plurality of power stages.

[0020] The comparator generates a comparison result comparing the magnitude of the temperature signal with the first temperature. The current sensing block reports information representing the first magnitude of the current flowing through the inductor to the phase controller. The phase controller sets the conduction duration of the two power switches based on the first magnitude.

[0021] According to one aspect of the invention, if the comparison result indicates that the magnitudes are not equal, the current sensing block reports a first magnitude that is inconsistent with the actual magnitude to cause the temperature of the power stage to tend toward the first temperature.

[0022] In one embodiment, the first temperature is a maximum temperature of temperatures generated by each of the plurality of power stages.If the temperature represented by the temperature signal is less than the temperature represented by the signal on the common path, the current sensing block reports the first magnitude as less than the actual magnitude.

[0023] Some aspects of the present invention are described below with reference to examples for illustration. However, those skilled in the relevant art will recognize that the present invention can be practiced without one or more specific details or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown in detail to avoid obscuring the features of the present invention. In addition, the described features / aspects can be practiced in various combinations, although for the sake of brevity, only some combinations are described herein.

[0024] 2. Example System

[0025] Figure 1 1 is a block diagram of an example system in which aspects of the present invention may be implemented. System 100 includes a power supply 110, a central processing unit (CPU) 120, a storage device 130, a network interface 140, and peripherals 150. In one embodiment, system 100 corresponds to a computer (desktop, laptop, etc.), although in other embodiments system 100 may represent other types of systems. It should be understood that system 100 may include, for example, a computer system (e.g., a desktop computer, a laptop computer, etc.). Figure 1 More or fewer blocks as shown.

[0026] CPU 120 generally represents a processor or system on a chip (SoC), and is shown as receiving a pair of supply voltages (Va and Vb) from power supply 110 on respective paths 112A and 112B. As an example, Va can be a smaller voltage than Vb and can be used to power the core portion of the CPU, which can include an arithmetic logic unit (ALU), a microprogram sequencer, registers, etc. Vb can be used to power the rest of CPU 120, for example, input / output (I / O) units, I / O buffers, on-chip peripherals, etc. CPU 120 provides various signals (all considered to be included in path 121) to power supply 110 that specifically specify its power requirements. Examples of such signals can be signals that specify a particular operating mode (in terms of power consumption), such as PS1, PS2, PS3, etc., which refer to "power saving states for improved efficiency."

[0027] Storage device 130 represents a memory that may include both volatile and non-volatile memory. For example, in a personal computer, the storage device may include magnetic storage (hard disk) as well as solid-state storage (RAM, flash memory, etc.). Storage device 130 is shown as receiving a supply voltage on path 113 for powering various circuits and blocks therein.

[0028] The network interface 140 is used to provide two-way communication between the system 100 and a computer network or the general Internet. The network interface 140 implements the use of a specific physical layer and data link layer standard (such as Ethernet or Wi-Fi TM ) for communicating with the CPU 120. The network interface 140 may also include a network protocol stack to allow communication with other computers on the same local area network (LAN) and large-scale network communication through routable protocols such as the Internet Protocol (IP). The network interface 140 receives power on path 114 for powering internal circuits and blocks. The network interface 140 receives / sends from / to external systems and the CPU 120 on paths 141 and 124, respectively.

[0029] Peripheral device 150 represents one or more peripheral circuits, such as a speaker, a microphone, a user interface device, etc. Peripheral device 150 receives power on path 115 and communicates with external devices on path 151 .

[0030] The power supply 110 receives power from one or more power sources (e.g., batteries) on path 101 and is used to provide the desired power supply voltage on paths 112A, 112B, 113, 114, and 115. In one embodiment, the power supply 110 is designed to include one or more multi-phase DC-DC converters to generate the power supply voltage. The power supply 110 receives a signal received on path 121 from the CPU 120, which may indicate the power mode in which the CPU 120 will operate for a specific duration, which power mode indicates the amount of power that the CPU 120 may need / consume from the power supply 110. The power supply 110 responds to the signal by controlling the multi-phase converter to reduce / increase the current output based on a specific power mode signal (e.g., PS1, PS2, and PS3).

[0031] In an embodiment, the power supply 110 is a voltage regulation module (VRM), sometimes also referred to as a processor power module (PPM), and includes one or more step-down switching converters to generate one or more smaller voltages from a higher voltage power supply. However, in other embodiments, other types of DC-DC converters, such as boost, buck-boost, hysteresis converters, etc., may be implemented in place of the buck converter. Using the VRM, multiple devices / ICs requiring different supply voltages can be installed on the same platform, such as a computer motherboard of a personal computer (PC). Accordingly, for example, Figure 2 The depicted VRM continues.

[0032] 3. Voltage Regulator Module (VRM)

[0033] Figure 2 1 is a block diagram showing details of a VRM in an embodiment of the present invention. Figure 1 ) is a voltage regulation module implemented in the form of a multiphase switching converter that generates two regulated voltages, i.e., two supply rails (power rails), i.e., Va (240) (rail A) and Vb (250) (rail B). Nodes 240 and 250 can also be considered as power rails, respectively. Figure 2 , the power supply used to obtain Va and Vb is numbered 201 and has a voltage Vin. In the embodiment of VRM 110, an example value of Vin is about 21 volts (V). The power supply voltage Vcc (202) shown can be provided by the phase controller 210 and can be used to power the blocks within each power stage mentioned below.

[0034] The VRM 110 is shown having a phase controller 210, smart power stages (SPS) (or "power stages") SPSA-1 (220-1) to SPSA-3 (220-3), SPSB-1 ​​(230-1) to SPSB-4 (230-4), inductors 225A-1 to 225A-3 and 227B-1 to 227B-4, and capacitors 226A-1 to 226A-3 and 228B-1 to 228B-4. The power supply Va (240) (rail A) is generated by a 3-phase buck converter (there are three, SPSE-220-1 to 220-3), while the power supply Vb (250) (rail B) is generated by a 4-phase buck converter (there are four, SPSE-230-1 to 230-4). The nodes / paths 240 and 250 may correspond to Figure 1 For simplicity, Figure 2 Not shown are other power supply circuits that generate power on paths 113, 114, and 115. In alternative embodiments, VRM 110 may have more or fewer power rails and power levels for each rail.

[0035] In an embodiment of the present invention, each of the power stage and the phase controller is implemented as a separate integrated circuit (IC). However, in other embodiments, the implementation of the power stage and the phase controller may be different.

[0036] The phase controller 210 operates in combination with one or more power stages of the rail to produce a regulated voltage as an output. Figure 2 In the example of , the phase controller 210 operates in combination with one or more of the power supply stages SPSA-1 to SPSA-3 to generate a regulated voltage Va (240). Similarly, the phase controller 210 operates in combination with one or more of the power supply stages SPSB-1 ​​to SPSB-4 to generate a regulated voltage Vb (250). Thus, Va (240) and Vb (250) are provided as inputs to the phase controller 210 to enable operation of one or more feedback loops within the phase controller 210 to regulate the voltages Va and Vb. The phase controller 210 also receives inductor current information (regarding the current flowing through each inductor) from each SPSes to implement various operations such as current mode control of voltage regulation, current limiting, short circuit protection, and balancing the current generated by each SPS of the same converter (or "rail") so that the current magnitudes from each SPS of the rail are substantially equal. Other signals flowing between the phase controller 210 and the SPSes are described below.

[0037] The combination of phase controller 210 (corresponding circuitry therein), the SPS, and corresponding inductors and capacitors form one "phase" of the rail. Thus, for example, SPSA-1, inductor 225A-1, capacitor 226A-1, and corresponding portions within phase controller 210 form a single buck converter and one phase of a 3-phase buck converter. It should be noted here that while each phase is shown as having its own separate capacitor (e.g., 226A-1), in another embodiment, only a single larger capacitor (larger capacitance value) may be employed at node 240 (and 250). In other embodiments, multiple capacitors are placed close to a load powered by a corresponding supply voltage. For simplicity, a single SPS is also referred to as one phase of the power rail.

[0038] Each SPS (or generally "power stage") may be implemented with a high-side switch, a low-side switch, gate drive circuits for both switches, a temperature monitoring circuit, and an inductor current sensing circuit / block to provide information indicating the magnitude of the inductor current to the phase controller 210. Although the high-side switch and the low-side switch of the SPS may be viewed as "driving" the inductor, the current supplied by the SPS and the corresponding inductor current generally depends on the load current drawn from the supply voltage. Each SPS receives a power supply (which may all be the same power supply) as an input connected to the high-side switch (shown in detail in the following section).

[0039] Each SPS communicates with the phase controller 210 via respective signals PWM, SYNC, CS and TMP. Thus, SPSA-1 is connected to the phase controller 210 via signals / paths PWMA-1 (211), SYNC-A (212), CSA-1 (213) and TEMPA (214). SPSA-6 communicates with the phase controller 210 via the PWMA-6 signal, the SYNC-A signal, the CSA-6 signal and the TEMPA signal (214), although in Figure 2 The corresponding connections of the signals PWMA-6, SYNC-A and CSA-6 to the phase controller 210 are not shown. Similarly, SPSB-1 ​​is connected to the phase controller 210 via the signals / paths PWMB-1 (216), SYNC-B (217), CSB-1 (218) and TEMPB (219). SPSB-3 communicates with the phase controller 210 via the PWMB-3 signal, the SYNC-B signal, the CSB-3 signal and the TEMPB (219) signal, although in Figure 22 , the corresponding connections of the PWMB-3 signal, the SYNC-A signal, and the CSB-3 signal to the phase controller 210 are not shown. The other SPSes have similar connections to the phase controller 210. Generally, when implemented as an IC, each SPS has PWM, SYNC, CS, and TEMP pins for the above corresponding connections, and the signals to / from the power stage from / to the phase controller 210 can generally be referred to as the PWM, SYNC, CS, and TEMP signals corresponding to the power stage.

[0040] The PWM signal is an input from the phase controller 210 to the SPS and represents a pulse width modulation (PWM) signal. The PWM signal can be generated to have a logic high state, a logic low state, or a high impedance (Hi-Z) state. Typically, the logic high and logic low states of the PWM signal correspond to the voltages of the positive and negative rails of the power supply of the circuit generating the PWM signal, respectively (within the error / noise tolerance), and the Hi-Z state corresponds to the mid-rail voltage of the power supply (or a voltage window around the mid-rail voltage), which is well known in the relevant art. However, it is obvious to a person skilled in the relevant art that other conventions may be adopted for the three states of the PWM signal.

[0041] The PWM signal controls the opening and closing of the high-side switch and the low-side switch of the phase / power stage via logic high and logic low states. Typically, the logic high state is used to turn on (i.e., close) the high-side switch and turn off (i.e., open) the low-side switch (the corresponding duration can be referred to as the "first interval"), while the logic low state is used to turn on the low-side switch and turn off the high-side switch (the corresponding duration can be referred to as the "second interval"). Each cycle of the PWM signal has a corresponding "first interval" and "second interval".

[0042] The Hi-Z state of the PWM signal indicates to the power stage that the power stage is not operating, i.e., "inactive", when generating the output voltage. Therefore, when the PWM is in the Hi-Z state, both the high-side and low-side switches of the stage are turned off, and the power stage can enter a low power / power-down mode. Typically, the phase controller 210 is designed to generate the PWM signal in a manner that can indicate three states, one of which indicates that the corresponding power stage will be inactive. It will be apparent to those skilled in the relevant art that this three-state capability can be implemented in other ways. As an example, the phase controller 210 can be implemented to generate PWM as a conventional binary signal, where the power stage is implemented to recognize the Hi-Z state if the PWM signal is turned off (i.e., not generated at all).

[0043] The duty cycle of the PWM signal is set by the phase controller 210 and is designed to produce the desired supply voltage and / or control / change the current provided by that phase. For example, PWMA-1 has a duty cycle required by the Va and the magnitude of the current provided by SPSA-1. The magnitude of the current flowing through the inductor corresponding to the power stage is determined by the on-time of the high-side switch and the low-side switch of the stage, and is set by the PWM input (or general control signal) of the stage.

[0044] As is well known in the related art, the PWM signals to each SPS of the same converter can be staggered, i.e., delayed in phase with respect to each other, so that generally no two rails of the high-side switches (i.e., in the corresponding SPS) are turned on at the same time. This technique is employed, for example, to ensure that the peak instantaneous current drawn from Vin is always relatively low.

[0045] The SYNC signal is an input to the SPS and can be used by the phase controller 210 to wake up the SPS when the power supply 110 is powered on and indicate the power mode (e.g., PS2, PS3) of the multi-phase converter, i.e., the output current requirement. Typically, all SPSs of the same converter share a single SYNC signal (e.g., SYNC-A 212).

[0046] The CS (current sense) signal is an input from the SPS / phase to the phase controller 210 and contains information about the magnitude of the inductor current for that phase. This information can be in the form of current, voltage, digital value, etc., depending on the specific implementation of the power stage and the phase controller 210. The CS block in the SPS implements the current sensing operation and sends the CS signal to the phase controller 210.

[0047] In an embodiment of the present invention, the current sensing block of the power stage sends the sensed inductor current information to the phase controller 210 in the form of a current, which may have the same magnitude as the inductor current or (more typically) be a scaled-down version (in terms of magnitude) of the inductor current. Accordingly, in an embodiment, the phase controller 210 is designed to receive information in the form of a current, where when scaling is used, the scaling factor is known to the phase controller 210 and the (corresponding) power stage.

[0048] The TEMP pins (or nodes) of all stages of the track are wired together, providing only a single TEMP input to the phase controller 210, such as Figure 2As shown. For example, corresponding to Rail B, a single connection TEMPB (219) is provided to the phase controller 210 based on the temperature reported by each power stage of Rail B. This approach is generally taken to minimize the number of wires / PCB (printed circuit board) tracks (and therefore signals) from the rail to the power stages of the phase controller 210, as well as to reduce the pinout (number of pins) of the phase controller 210. The temperature of the power stage is proportional to (positively correlated to) the magnitude of the inductor current of the power stage.

[0049] In the present embodiment, the power supply stages are designed in such a way that the single TEMP input provided to the phase controller 210 automatically (through operation of corresponding circuitry) takes a value which is the maximum of the temperatures recorded in each of the power supply stages. Figure 3 FIG. 1 shows circuit details of the relevant portion of a temperature monitor block according to the prior art. Figure 3 , four power supply stages of rail B according to a prior art embodiment are shown. The four prior art stages are labeled B1 (390-1), B2 (390-2), B3 (390-3) and B4 (390-4). The output pins P31, P32, P33 and P34 of the respective power supply stages are all connected and the common connection / path is provided to the phase controller as TMPB (314). TMPB (314) corresponds to Figure 2 Common path TEMPB (219) is shown as being terminated by resistor 350 (approximately 50 kilo-ohms) and capacitor 360 (approximately 10 nanofarads).

[0050] Power stage B1 includes an amplifier 310-1, a P-channel MOSFET (metal oxide semiconductor field effect transistor) (or "PMOS") 320-1, and a current sink 330-1. Power stage B1 also includes a temperature sensor (not shown) that generates a voltage (temperature signal) on path 311-1 that indicates the sensed temperature of B1. When implemented as an integrated circuit (IC), the temperature sensor senses the temperature of the semiconductor die of B1. In alternative embodiments of B1, such as using discrete components, the temperature sensor can be designed to sense the temperature at or near the power switch of B1. Other methods suitable for the specific implementation of B1 can also be used. Amplifier 310-1 receives the voltage on path 311-1 at its inverting (-) terminal and receives the voltage on the "temperature reporting" output pin P31 at its non-inverting (+) terminal. The output of amplifier 310-1 is connected to the gate terminal of PMOS 320-1. Current sink 330-1 can be implemented as a weak pull-down (5 microamps). VDD ( 301 ) represents a power supply terminal received from an external source, such as the phase controller 210 .

[0051] The amplifier 310-1, the PMOS 320-1, and the current sink 330-1 operate together to "drive" the voltage received on the path 311-1 (representing the sensed temperature) to the output pin P31, so the combination of the amplifier 310-1, the PMOS 320-1, and the current sink 330-1 can be regarded as a "driver circuit." The corresponding circuits of the other three power supply stages can also be regarded as corresponding driver circuits.

[0052] If the pin P31 is disconnected from the common path TMPB (314), the voltage on the pin P31 is equal to the voltage of the temperature signal 311-1. In other words, the temperature signal is forwarded as is (without any change) on the temperature reporting pin P31.

[0053] However, in the case where the pin P31 (and the pins P32, P33, and P34) are connected to the common path TMPB (314), due to the operation of the corresponding driver circuit, the voltage on the common path TMPB (314) is equal to the maximum value (highest value) of the four temperature signals 311-1, 311-2, 311-3, and 311-4. Figure 3 In the driver circuit of B1 shown, if the voltage on the non-inverting terminal (the same path as TMPB (314)) is greater than the voltage on path 311-1, the output of amplifier 310-1 is high enough to turn off PMOS 320-1. If the voltage on TMPB (314) is less than or equal to the voltage on the inverting terminal, the output of amplifier 310-1 will have an output voltage that turns on PMOS 320-1 through a resistor, so that the voltage on the non-inverting terminal becomes equal to the voltage on path 311-1.

[0054] The other three stages B2-B4 have similar circuits to those in B1 and also operate in a similar manner. Therefore, paths 311-2, 311-3, and 311-4 correspond to path 311-1 and receive voltage outputs generated by corresponding temperature sensors in corresponding stages, respectively. Similarly, amplifiers 310-2, 310-3, and 310-4 correspond to amplifier 310-1, PMOS transistors 320-2, 320-3, and 320-4 correspond to PMOS 320-1, and current sinks 330-2, 330-3, and 330-4 correspond to current sink 330-1.

[0055] Figure 3 The effect of the combined operation of the circuits shown in is that the maximum value of the voltage output by the respective temperature sensor (on the respective paths 311-1 to 311-4) appears at TMPB (314).

[0056] Typically, the above-mentioned existing power supply stage can be designed with a circuit to make the common path ( Figure 3The temperature signal generated on the TMPB 314 in the example of FIG. 1 is derived from (for example, Figure 3 311-1 to 311-4 in the example of ) are all temperature signals generated in each operating power supply stage (e.g., are mathematical functions thereof). Figure 3 In the illustration of , the derived signal is the "maximum value" of the individual signals. In other embodiments, the derived signals may be of different types. As another example, the derived signal on the common path may be the average value of the individual temperature signals.

[0057] As described above, one or more factors may cause the power stages of a track to have different operating temperatures. For example, even if the power stages are all operated by the phase controller to provide the same current, there may be a current mismatch between the power stages. Another factor may be that the power stages may be physically located on the PCB such that one or more of the power stages operate at different ambient temperatures (e.g., a power stage closer to the processor has a higher ambient temperature), causing their temperatures to also be different.

[0058] One disadvantage of using a single common path is that the phase controller 210 obtains only a derived signal (e.g., the maximum value of the individual temperature signals). Therefore, the phase controller 210 cannot balance the temperature of the power stages and is limited to actions such as forcing all power stages to reduce their inductor currents if the maximum temperature indicated on the common path exceeds a safe upper limit. Alternatively, if the highest temperature exceeds a safe upper limit, the phase controller may cut off all power stages of the track. Ultimately, the VRM 110 operates at a reduced performance level and is able to support only a lower power mode of the CPU 120.

[0059] Embodiments of the present invention are designed to overcome the above-mentioned problems, as described below.

[0060] 4. Power supply stage (SPS)

[0061] Figure 4 is a diagram showing implementation details of a power supply stage in an embodiment of the present invention. Figure 2 The power supply stage 230-1 (SPSB-1) is Figure 4 , which includes a gate driver 410 , a high-side (HS) switch 420 , a low-side (LS) switch 430 , a temperature monitor 440 , and a current sensing block 450 . Figure 4Also shown in FIG. 4 are inductor 227B-1 and capacitor 228B-1 corresponding to the power stage. When implemented as an IC, P41 to P46 represent the pins of SPSB-1. Current "IL" represents the inductor current flowing through inductor 227B-1, and current "Ics" represents the sensed inductor current reported by power stage 230-1 on output pin P42, which is connected to phase controller 210 via path CSB-1 (218). Vcc 202 is used to power blocks 410, 440, and 450. The drain terminal of HS switch 420 is connected to Vin 201.

[0062] The power stage 230-1, in combination with the inductor 325 and the capacitor 326 and the phase controller 210, provides a regulated voltage (Vb) as an output at the node 250. Although not shown in the figure for the sake of brevity, Figure 3 4, but the power stage 300 may include various other blocks / circuits, such as a level shifter for the gate driver 410, etc. For simplicity, the pins / circuits in the power stage 230-1 that are connected to handle the synchronous input signal are not shown.

[0063] Figure 2 All other power stages (Rail B and optionally Rail A) are similar to Figure 4 The power stage 230 - 1 is implemented as described below.

[0064] The gate driver 410 receives the PWM signal PWMB-1 (216) (from the phase controller 210), and in response to the logic level of the PWM signal, generates appropriate voltages to turn on and off the HS switch 420 and the LS switch 430 in the corresponding intervals indicated by the logic level of the PWM signal. The HS switch 420 and the LS switch 430 are N-channel MOSFETs (metal oxide semiconductor field effect transistors), and the gate driver 410 drives the gate terminals of the MOSFETs. The switches may be implemented in other possible ways. Figure 4 In the example of , when PWMB-1 is logic high, the gate driver 410 generates corresponding appropriate voltages on paths 412 (en-HS) and 413 (en-LS) to turn on MOSFET 420 and turn off MOSFET 430. When PWMB-1 is logic low, the gate driver 410 generates corresponding appropriate voltages on paths 412 and 413 to turn off MOSFET 420 and turn on MOSFET 430. When PWMB-1 is Hi-Z (high impedance or mid-rail) state, the gate driver 410 generates corresponding appropriate voltages on paths 412 and 413 to turn off MOSFET 420 and 430. The gate driver 410 can be implemented in a known manner.

[0065] The current sensing block 450 is used to determine the magnitude (e.g., instantaneous magnitude) of the inductor current through the inductor 227B-1 and provide information indicating the magnitude of the inductor current on an output pin P42, which is connected to the phase controller 210 via a path CSB-1 (218). The current sensing block 450 can determine the magnitude of the inductor current in one of several known ways. For example, in Figure 4 , the current sensing block 450 is shown as receiving inputs 425 and 435 from the HS switch 420 and the LS switch 430, respectively. In one embodiment, the signals 425 and 435 represent the respective voltage drops across the HS and LS switches when the corresponding switches are turned on and current flows through the HS switch 420 and the LS switch 430 and the inductor 227B-1. The current sensing block 450 obtains the instantaneous magnitude of the inductor current (or a scaled-down version thereof) based on the voltage drop. In another embodiment, the current sensing block 450 employs sensing the voltage drop across the LS switch 430 to directly obtain the inductor current magnitude (or a scaled-down version thereof) when the LS switch is turned on, and "constructs" (or simulates) the inductor current magnitude when the HS switch 420 is turned on.

[0066] In one embodiment, the current sensing block 450 provides / reports the inductor current information in the form of a (copy) current (indicated as Ics) having a magnitude that is scaled down relative to the instantaneous inductor current magnitude. However, in alternative embodiments, the current sensing block 450 may be implemented to provide information in the form of a voltage or digital value. As described below, the current sensing block 450 receives an input signal 445 from the temperature monitor 440.

[0067] Temperature monitor 440 includes a temperature sensor that can generate a "temperature" signal (e.g., in the form of a voltage) that indicates the temperature (e.g., die temperature) of power stage 230-1. An example relationship between temperature and the voltage generated by the temperature sensor, or in other words, the "gain" of the temperature sensor, is 10 millivolts (mV) per degree Celsius (°C), or 10 mV / °C. Other relationships may be used.

[0068] The temperature monitor 440 includes a circuit (driver circuit) that receives a temperature signal from a temperature sensor and drives the temperature signal to an output pin P43. The temperature signal is driven to the output pin P43 in such a way that when P43 is connected to a common path TEMP (219) (which will also be connected to the corresponding output pins of other power supply stages of the same rail, i.e., SPSB-2 to SPSB-4), the signal on the common path TEMP (219) automatically obtains a magnitude derived from (and is a function of its expectation of) all temperature signals of the corresponding power supply stages SPSB-1 ​​to SPSB-4. In an embodiment of the present invention, the derived magnitude is the maximum value of all temperature signals of the corresponding power supply stages. Therefore, the signal on the common path TEMPB (219) represents the maximum value of each temperature of each power supply stage. However, it is noted here (and further described below) that in alternative embodiments, the driver circuit can be implemented in a different manner so that the derived magnitude is another function (e.g., an average value) of all temperature signals.

[0069] According to one aspect of the present invention, the temperature monitor 440 compares the magnitude of the temperature signal generated by the internal temperature sensor with the magnitude of the signal on the common path TEMPB (219). The temperature monitor 440 transmits the comparison result on the path 445 to the current sensing block 450. If the comparison result indicates that the temperature signal is less than the predetermined value of the signal TEMPB (219) (which itself can be zero or non-zero, for example, 2.4mV in the embodiment), the current sensing block 450 underreports the actual inductor current magnitude to the phase controller 210 via the path CSB-1 (218). In other words, the sensed current information generated by the current sensing block 450 on the path CSB-1 (218) is intentionally reported as having a smaller magnitude than its original magnitude (if the two magnitudes are equal or within a predetermined range of each other, for example, + / -2.4mV).

[0070] Therefore, the phase controller 210 generates PWMB-1 (216) in a manner that causes the power stage SPSB-1 ​​to increase its inductor current, thereby driving the temperature of the power stage SPSB-1 ​​toward the temperature indicated by the signal on TEMPB (219). Alternatively, the phase controller 210 generates corresponding PWM signals provided to the other power stages (i.e., SPSB-2, SPSB-3, and SPSB-4) to cause those power stages to reduce or increase their corresponding inductor currents (depending on the corresponding sensed inductor currents they report), thereby driving the temperatures of all four power stages toward equalization.

[0071] The specific magnitude of the sensed inductor current underreported by the current sensing block 450 may be predetermined by design in the current sensing block 450, for example, typically based on the specific operating requirements / environment of the circuit / IC of Rail B and VRM 110. Similarly, the degree to which the phase controller 210 increases or decreases the inductor current of one or more of the power stages may be predetermined based on similar considerations.

[0072] Next, an example temperature imbalance that can be corrected by the power stage is briefly described. In the case of a package (IC package) thermal resistance of 10°C / W, an increase of 1 ampere (1A) in the inductor current can increase the temperature of the power stage by 1.5 degrees Celsius (°C). In order to correct a temperature imbalance of 7.5 degrees Celsius, that is, to increase the temperature of the power stage by 7.5°C, the inductor current needs to be increased by 5A. The above underreporting can be determined accordingly.

[0073] In one embodiment, if the inductor current of the SPSB-1 ​​stage is to increase by 1A, the current sensing block 450 is designed to underreport Ics (the sensed inductor current) by 10 microamperes (uA), and the minimum value (resolution) that the current sensing block 450 can underreport Ics is set to 1uA.

[0074] It should be noted here that thermal feedback is typically very slow. That is, when the inductor current changes, the corresponding change in the temperature of the corresponding power stage may take several milliseconds. Therefore, any update of signal 445 may need to be very small and only be performed at a maximum rate of, for example, once per millisecond (ms).

[0075] Due to the underreporting of current sensing block 450, the current balancing loop (the loop used to maintain substantially equal inductor currents for all power stages of the track) operating within phase controller 210 will generate PWMB-1 with a larger duty cycle (to cause HS switch 420 to conduct for a longer time in each PWM cycle), resulting in a larger inductor current for SPSB-1. This in turn will increase the temperature of power stage SPSB-1 ​​until it becomes equal to (or at least substantially equal to) the temperature indicated by the signal on path TEMPB (219). Alternatively, the current balancing loop in phase controller 210 can generate corresponding PWM signals provided to other power stages (i.e., SPSB-2, SPSB-3, and SPSB-4) with relatively shorter duty cycles to cause those power stages to reduce or increase their respective inductor currents.

[0076] Therefore, eventually the temperatures of all four power stages will reach equilibrium.

[0077] With all power stages SPSB-1 ​​to SPSB-4 implemented and operated as described above, the temperatures of the power stages will be balanced. It is noted here that even if not all four power stages, but only a subset are operated as described above, a degree of temperature balance can be achieved.

[0078] Reference below Figure 6 Portions / circuits of the current sense block 450 are described that cause the current sense block 450 to operate as described above in response to a signal received on path 445 .

[0079] Implementation details of the temperature monitor 440 in an embodiment of the present invention are provided below.

[0080] 5. Temperature monitor

[0081] Figure 5 is a diagram showing the implementation details of the temperature monitor 440 in an embodiment of the present invention. The temperature monitor 440 shown includes a temperature sensor 540, an amplifier 510, PMOS 520 and 525, current sinks 530 and 535, and an inverter 550. The gate terminal of each PMOS is connected to the output of the amplifier 510, and the source terminal of each PMOS is connected to Vcc (202). The components PMOS 525, current sink 535 and inverter 550 together constitute a "current comparator". Current sinks 530 and 535 can be designed to operate as weak pull-downs. The specific implementation details of the temperature monitor 440 are shown and described only by way of illustration. After reading the disclosure of this article, other ways to implement the temperature monitor 440 will be obvious to those skilled in the relevant art.

[0082] Temperature sensor 540 generates a voltage "tsns" representing the sensed temperature of power stage SPSB-1. When implemented as an integrated circuit (IC), temperature sensor 540 senses the temperature of the semiconductor die of power stage SPSB-1. In alternative embodiments, such as those using discrete components, temperature sensor 540 may be designed to sense the temperature at or near power switches 420 and 430. Other methods suitable for a particular embodiment of SPSB-1 ​​may also be used.

[0083] Amplifier 510, PMOS 520, and current sink 530 may be considered together as a "driver circuit," similar to the above description of Figure 3 The power stage B1 of the circuit "drives" tsns onto the output pin P43 in the manner described.

[0084] If the voltage TEMPB (219) is greater than the voltage "tsns" by a predetermined amount (as described above), the current comparator generates a logic high output on path 445, otherwise it generates a logic low output. Signal 445 causes the current sensing block 450 ( Figure 4 )Operate as described above. Figure 6 is a diagram illustrating a current sensing block 450 ( Figure 4 ) is shown in a diagram of an example implementation of a portion of the present invention and is briefly described below.

[0085] Figure 6 The controllable current source 620, current sinks 610 and 630, and a flip-flop (FF) 640 are shown. The currents generated by the current sources 620 and 630 are controlled by the respective outputs of a differential output amplifier (not shown), wherein the input of the amplifier (which may also be differential) receives the voltage drop across the HS switch 420 when PWMB-1 is high, and receives the voltage drop across the LS switch when PWMB-1 is low. The differential voltage output of the amplifier controls the current generated by the current source 620 and the current sink 630, so that the voltage on one of the pair of outputs controls the current generated by the current source 620, and the voltage on the other of the pair of outputs controls the current generated by the current sink 630. As the voltage drop across the amplifier input increases, the current generated by the current source 620 is correspondingly greater than the current generated by the current sink 630. The difference of the two currents flows as IC into pin P52 and path CSB-1 (218). Control of the current source 620 and the current sink 630 can be achieved in a known manner. For example techniques, readers can refer to U.S. Patent Application Publication No.: US2024 / 0030811 Figure 4 , entitled “EMULATING CURRENT FLOWING THROUGH AN INDUCTOR DRIVEN BY A COMBINATION OF HIGH-SIDE SWITCH AND A LOW-SIDE SWITCH INA SWITCHING CONVERTER”, the contents of which are incorporated herein by reference. Figure 4 The transistors 420 and 421 correspond to the current source 620 and the current sink 630. Although the high-side switch current is simulated in this disclosure, the high-side switch current can also be sensed by obtaining the voltage drop across the HS switch as described above. Figure 4 It can also be modified accordingly in a known manner.

[0086] FF 640 receives signal 445 at its D input and transmits the logic value of signal 445 to its Q output at each rising edge of clock 642, which in one embodiment is internally generated in power supply stage SPSB-1 ​​with a period of one millisecond (1ms). When signal 445 is logic high, Q output 641 becomes logic high and turns on current sink 610. Therefore, current sink 610 absorbs a fixed current (e.g., on the order of 1 to 10 microamperes) from pin P62, thereby reducing Ics accordingly. When signal 445 is logic low, Q output 641 becomes logic low and turns off current sink 610.

[0087] The power stages of the rails implemented as described above can achieve temperature balancing without requiring a separate path from each power stage to the phase controller 210. Furthermore, it can be appreciated that the operation of thermal balancing (i.e., temperature balancing) can be performed in real time and continuously over the duration of operation of the VRM 110. Thus, the balancing technique can achieve thermal balancing across all load current and temperature distributions, and thus can be superior to static one-time thermal balancing.

[0088] It should be noted here that due to the phase controller 210 operating the automatic phase management (APM) based on, for example, the load current requirement, one or more power switches of the track may be cut off. The PWM input of the corresponding power stage will be in a high impedance state. Based on this state, the above-mentioned thermal balancing operation is disabled in such a power stage. Therefore, the operation for thermal balancing can be enabled only when the power stage is activated. Therefore, each power stage is designed to include a circuit to determine the state of its PWM input. For example, the gate driver 410 of the power stage SPSB1 can be implemented to make such a determination and provide a corresponding indication to the current sensing block 450, which will perform under-reporting / over-reporting to achieve temperature balance only when its PWM input is not in a high impedance state.

[0089] Furthermore, thermal balancing operation may only be enabled if the temperature of one or more power stages of the track exceeds a predetermined temperature limit (e.g., 100 degrees C.) Thus, the temperature monitor 440 or phase controller is implemented to include circuitry to perform such a check in a known manner, although not shown in the figure.

[0090] Furthermore, as described above, any updates of signal 445 need to be very small and only occur at a maximum rate of, for example, once per millisecond (ms). This slow update rate is achieved by clocking FF 640 at a 1 ms rate using 1 ms clock 642.

[0091] In alternative embodiments, the driver circuits in each power stage may be implemented differently so that the derived magnitude is some other function of all temperature signals (rather than a "maximum value"). The current sensing block 450 will over-report or under-report accordingly when reporting the sensed inductor current to cause the inductor current to decrease or increase, thereby causing the temperatures of the operating power stages to tend toward equality.

[0092] For example, the derived magnitude may be the average of all temperature signals for the various power stages. Depending on the different magnitudes of the temperature signal and the signal TEMPB, the current sensing block 450 under-reports or over-reports the sensed inductor current in order to balance the temperatures of the power stages. Accordingly, the phase controller 210 will generate PWMB-1 (216) in a manner that causes the power stage SPSB-1 ​​to increase or decrease its inductor current, thereby pushing the temperature of the power stage SPSB-1 ​​toward the temperature indicated by the signal on TEMPB (219). Other details and operations as described above with respect to the embodiment in which the common path TEMPB is the maximum of all temperature signals may be applied / performed accordingly.

[0093] 6. Conclusion

[0094] Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

[0095] Although in Figures 1 to 6 In the illustrations of , although the terminals / nodes are shown as being directly connected (i.e., "connected") to various other terminals, it should be understood that additional components (as appropriate to the particular environment) may also be present in the path and, therefore, the connections may be viewed as being "electrically coupled" to the same connection terminals.

[0096] It should be understood that the specific types of transistors (e.g., NMOS, PMOS, etc.) mentioned above are for illustration purposes only. However, alternative embodiments using different configurations and transistors will be apparent to those skilled in the relevant art by reading the disclosure provided herein. For example, an NMOS transistor can be replaced with a PMOS (P-type MOS) transistor while also swapping the connections to the power supply terminal and the ground terminal.

[0097] Therefore, in the present invention, the power supply and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of the transistor (through which a current path is provided when turned on and through which an open path is provided when turned off) are referred to as current terminals, and the gate (base) terminal is referred to as a control terminal.

[0098] Although various embodiments of the present invention have been described above, it should be understood that these embodiments are only exemplary and not limiting. Therefore, the breadth and scope of the present invention should not be limited by any of the above embodiments, but should only be defined in accordance with the following claims and their equivalents.

Claims

1. A power supply stage in a plurality of power supply stages that jointly generate a supply voltage on a power rail of a multi-phase switching converter, wherein a phase controller controls operation of the plurality of power supply stages, the power supply stage comprising: a high-side switch and a low-side switch for periodically driving an inductor in a first interval and a second interval, respectively, based on a control signal received from a phase controller of the multi-phase switching converter, wherein an actual amount of current flowing through the inductor is determined by an on-time duration of the high-side switch and the low-side switch set by the control signal; a temperature sensor for generating a temperature signal indicative of a temperature of the power stage, wherein the temperature is positively correlated with the actual magnitude, wherein the temperature signal is coupled to be indicated on a common path, the common path indicating to the phase controller a first temperature derived from all temperature signals provided by the plurality of power stages; a comparator, configured to generate a comparison result of comparing the magnitude of the temperature signal with the first temperature; and a current sensing block for reporting a first magnitude of the current flowing through the inductor to the phase controller, wherein the phase controller determines the on-time based on the first magnitude, wherein if the comparison indicates that the magnitudes are not equal, the current sensing block reports the first magnitude as inconsistent with the actual magnitude to cause the temperature to trend toward the first temperature.

2. The power stage of claim 1 , wherein the first temperature is a maximum temperature of temperatures generated by each of the plurality of power stages; in, If the temperature represented by the temperature signal is less than the first temperature, the current sensing block reports that the first magnitude is less than the actual magnitude.

3. The power stage of claim 2 , wherein in response to receiving the first magnitude when the first magnitude is reported as less than the actual magnitude, the phase controller adjusts the control signal to increase the on-duration of the high-side switch, thereby causing the temperature to increase.

4. The power stage according to claim 2, wherein: The current sensing block reports that the first magnitude is less than the actual magnitude only when the temperature represented by the temperature signal exceeds a predetermined limit.

5. The power stage according to claim 2, wherein: Only when the power stage is active does the current sensing block report that the first magnitude is less than the actual magnitude.

6. The power stage of claim 2, wherein the temperature sensor and the comparator are included in a temperature monitor of the power stage, wherein the temperature monitor further comprises a driver circuit, the driver circuit being designed to drive the temperature signal onto a first output pin of the power stage, the first output pin being coupled to the common path; in, The driver circuit provides the temperature signal on the first output pin if the temperature represented by the temperature signal is greater than or equal to the first temperature, otherwise the driver circuit decouples the temperature signal from the first output pin.

7. The power stage of claim 6, wherein the driver circuit comprises: a differential amplifier coupled to receive the temperature signal at a non-inverting terminal, an inverting terminal of the differential amplifier coupled to the first output pin; a first weak current sink coupled between the non-inverting terminal and a first constant reference potential; and a first P-channel MOSFET transistor PMOS, wherein a control terminal of the first PMOS is coupled to the output of the differential amplifier, wherein a first current terminal of the first PMOS is coupled to a second constant reference potential, and a second current terminal of the first PMOS is coupled to the non-inverting terminal of the differential amplifier.

8. The power stage of claim 7, wherein the comparator comprises: a second PMOS, wherein a control terminal of the second PMOS is coupled to the output of the differential amplifier, wherein a first current terminal of the second PMOS is coupled to the second constant reference potential; a second weak current sink coupled between a second current terminal of the second PMOS and the first constant reference potential; and an inverter having an input terminal coupled between a junction of the second PMOS and a second weak current sink, wherein an output terminal of the inverter is coupled to the current sensing block to enable the current sensing block to report the first magnitude to the phase controller; If the temperature represented by the temperature signal is greater than or equal to the first temperature, the output terminal of the inverter has a first logic value, otherwise the output terminal of the inverter has a second logic value.

9. The power stage of claim 8, wherein the current sensing block comprises: a flip-flop, wherein a D input of the flip-flop is coupled to the output terminal of the inverter, wherein a clock input of the flip-flop is coupled to receive a clock signal; and a third current sink coupled between a second output pin of the power stage and the first constant reference potential, wherein the current sensing block reports the first magnitude to the phase controller via the second output pin, wherein the output terminal of the inverter is coupled to the third current sink; Wherein the second logic value on the output terminal of the inverter turns on the third current sink and sinks a fixed current from the second output pin, thereby causing the current sensing block to report that the first magnitude is less than the actual magnitude.

10. The power stage of claim 1, wherein the first temperature is an average temperature of temperature signals generated by each of the plurality of power stages; in, If the magnitude of the temperature signal is greater than the average temperature, the current sensing block reports that the first magnitude is greater than the actual magnitude.

11. A multiphase switching converter, comprising: Multiple power stages that work together to generate a regulated supply voltage on the power rail; and a phase controller for controlling operation of each of the plurality of power stages to produce the regulated supply voltage; Wherein a first power supply stage among the plurality of power supply stages comprises: a high-side switch and a low-side switch for periodically driving an inductor in a first interval and a second interval, respectively, based on a control signal received from a phase controller of the multi-phase switching converter, wherein an actual amount of current flowing through the inductor is determined by an on-time duration of the high-side switch and the low-side switch set by the control signal; a temperature sensor for generating a temperature signal indicative of a temperature of the power stage, wherein the temperature is positively correlated to the actual magnitude, wherein the temperature signal is coupled to be indicated on a common path, the common path indicating to the phase controller a first temperature derived from all temperature signals provided by the plurality of power stages; a comparator, configured to generate a comparison result of comparing the magnitude of the temperature signal with the first temperature; a current sensing block for providing information representative of a first magnitude of current flowing through the inductor to the phase controller, wherein the phase controller determines the on-time based on the first magnitude, wherein if the comparison indicates that the magnitudes are not equal, the current sensing block reports that the first magnitude is inconsistent with the actual magnitude, so that the phase controller causes the temperature to tend toward the first temperature.

12. The multiphase switching converter according to claim 11, wherein: the first temperature being a maximum temperature of temperatures produced by each of the plurality of power stages; Wherein, if the temperature represented by the temperature signal is less than the first temperature, the current sensing block reports that the first magnitude is less than the actual magnitude.

13. The multiphase switching converter of claim 12, wherein in response to receiving the first magnitude when the first magnitude is reported as less than the actual magnitude, the phase controller adjusts the control signal to increase the on-time of the high-side switch, thereby causing the temperature to increase.

14. The multi-phase switching converter of claim 12, the current sensing block reports the first magnitude as being less than the actual magnitude only when the temperature represented by the temperature signal exceeds a predetermined limit.

15. The multi-phase switching converter of claim 12, the current sensing block reports that the first magnitude is less than the actual magnitude only when the power stage is active.

16. The multiphase switching converter of claim 12, wherein the temperature sensor and the comparator are included in a temperature monitor of the power stage, wherein the temperature monitor further comprises a driver circuit, the driver circuit being designed to drive the temperature signal onto a first output pin of the power stage, the first output pin being coupled to the common path; in, The driver circuit provides the temperature signal on the first output pin if the temperature represented by the temperature signal is greater than or equal to the first temperature, otherwise the driver circuit decouples the temperature signal from the first output pin.

17. The multiphase switching converter of claim 16, wherein the driver circuit comprises: a differential amplifier coupled to receive the temperature signal at a non-inverting terminal, an inverting terminal of the differential amplifier coupled to the first output pin; a first weak current sink coupled between the non-inverting terminal and a first constant reference potential; and a first P-channel MOSFET transistor PMOS, wherein a control terminal of the first PMOS is coupled to the output of the differential amplifier, wherein a first current terminal of the first PMOS is coupled to a second constant reference potential, and a second current terminal of the first PMOS is coupled to the non-inverting terminal of the differential amplifier.

18. The multi-phase switching converter of claim 17, wherein the comparator comprises: a second PMOS, wherein a control terminal of the second PMOS is coupled to the output of the differential amplifier, wherein a first current terminal of the second PMOS is coupled to the second constant reference potential; a second weak current sink coupled between a second current terminal of the second PMOS and the first constant reference potential; and an inverter having an input terminal coupled between a junction of the second PMOS and a second weak current sink, wherein an output terminal of the inverter is coupled to the current sensing block to enable the current sensing block to report the first magnitude to the phase controller; If the temperature represented by the temperature signal is greater than or equal to the first temperature, the output terminal of the inverter has a first logic value, otherwise the output terminal of the inverter has a second logic value.

19. The multi-phase switching converter of claim 18, wherein the current sensing block comprises: a flip-flop, wherein a D input of the flip-flop is coupled to the output terminal of the inverter, wherein a clock input of the flip-flop is coupled to receive a clock signal; and a third current sink coupled between a second output pin of the power stage and the first constant reference potential, wherein the current sensing block reports the first magnitude to the phase controller via the second output pin, wherein the output terminal of the inverter is coupled to the third current sink; Wherein the second logic value on the output terminal of the inverter turns on the third current sink and sinks a fixed current from the second output pin, thereby causing the current sensing block to report that the first magnitude is less than the actual magnitude.

20. The multiphase switching converter of claim 11, wherein the first temperature is an average temperature of temperature signals generated by each of the plurality of power stages, in, If the magnitude of the temperature signal is greater than the average temperature, the current sensing block reports that the first magnitude is greater than the actual magnitude.

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