A charge pump boost circuit

Abstract

This invention discloses a charge pump boost circuit, relating to the field of brushed motor technology, to solve the problem of low boost efficiency in existing charge pump boost circuits built into brushed motors. The charge pump boost circuit includes: a logic control module, a current source module, a drive module, and a boost module; the current source module provides a stable voltage to the drive module; the drive module includes at least a pull-up PMOS transistor; the logic control module generates two non-overlapping clock signals based on an input clock source, and generates a first switching signal and a second switching signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include a first clock signal and a second clock signal; the logic control module controls the switching of the drive module based on the two non-overlapping clock signals, the first switching signal, and the second switching signal, so that the drive module uses the pull-up PMOS transistor to drive the boost module to output a target voltage. This improves boost efficiency.

Description

Technical Field

[0001] This invention relates to the field of brushed motor technology, and more particularly to a charge pump boost circuit. Background Technology

[0002] Currently, the built-in charge pumps in brushed motors often suffer from low boost efficiency. Brushed motor driver chips with H-bridges often need to consider the boosting of the high-side switch gate voltage. Most solutions use external bootstrap capacitors and Schottky diodes to boost the high-side switch gate voltage to a value higher than the supply voltage VCC.

[0003] To avoid using external components and reduce chip output ports, most eSOP8 packaged motor driver chips employ an internal charge pump to provide power to the high-side switch driver. For example... Figure 1 However, the boost efficiency of this type of charge pump is often affected by parasitic capacitance, dead time, and the switching speed of power devices, resulting in a lower boost voltage. Furthermore, the output voltage of the charge pump determines the gate-source voltage and on-resistance of the high-side switches in the H-bridge; a lower output voltage leads to higher on-resistance, increasing the heat dissipation of the power transistors. Simultaneously, its transient power consumption is significant; if it shares a ground line with other digital-analog circuits, this transient current can cause substantial interference on the ground line.

[0004] The current structure diagram of the built-in charge pump in motor driver chips is as follows: Figure 1 As shown, a detailed circuit structure diagram is as follows: Figure 2 As shown, a high-frequency clock source (typically 10MHz), after being level-shifted, controls a push-pull mechanism to charge and discharge a capacitor. One end of the capacitor is connected to a reference voltage source, and the other end is connected to the output of the push-pull mechanism. Initially, one end of the capacitor is charged to approximately 6.3V by the reference voltage source, while the other end is at 0V. Later, as the other end of the capacitor is charged to the power supply voltage level by the push-pull mechanism, since the voltage across the capacitor cannot change abruptly, the voltage on the upper-level board will rise to the power supply voltage +6.3V. This voltage, after being reduced by a diode, ultimately powers the high-side drive, approximately the power supply voltage +5.5V.

[0005] In the existing push-pull mechanism, the pull-up PMOS is generally a high-voltage power PMOS with a large size. Because the PMOS turns on slowly, the lower stage board starts to discharge before the voltage of the capacitor reaches the power supply voltage, resulting in the final external voltage not meeting the requirements and low boost efficiency. Summary of the Invention

[0006] The purpose of this invention is to provide a charge pump boost circuit for improving the boost efficiency of the charge pump.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] This invention provides a charge pump boost circuit, comprising: a logic control module, a current source module, a drive module, and a boost module;

[0009] Both the current source module and the logic control module are connected to the drive module; the drive module is connected to the boost module; the current source module is used to provide a stable voltage to the drive module; the drive module includes at least a pull-up PMOS transistor;

[0010] The logic control module is used to generate two non-overlapping clock signals based on the input clock source, and to generate a first switch signal and a second switch signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include the first clock signal and the second clock signal.

[0011] The logic control module is used to control the switching of the drive module based on the two non-overlapping clock signals, the first switch signal, and the second switch signal, so that the drive module uses the pull-up PMOS transistor to drive the boost module to output the target voltage.

[0012] Compared with the prior art, the present invention provides a charge pump boost circuit, including a logic control module, a current source module, a drive module, and a boost module. The logic control module generates two non-overlapping clock signals based on an input clock source, and generates a first switch signal and a second switch signal based on the two non-overlapping clock signals. The two non-overlapping clock signals include a first clock signal and a second clock signal. The current source module provides a stable voltage to the drive module. The logic control module controls the switching of the drive module based on the two non-overlapping clock signals, the first switch signal, and the second switch signal, so that the drive module uses the pull-up PMOS transistor to drive the boost module to output a target voltage. Specifically, the logic control module, in conjunction with the drive module, provides more current to charge the gate of the pull-up PMOS transistor to accelerate its turn-on speed, and specifically, through the combined action of the first clock signal, the second clock signal, the first switch signal, and the second switch signal, accelerates the turn-off speed of the pull-up PMOS transistor in the drive module, thereby improving the boost speed and boost efficiency. Attached Figure Description

[0013] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0014] Figure 1A schematic diagram of a charge pump boost circuit provided by the prior art;

[0015] Figure 2 for Figure 1 The specific circuit structure diagram of the charge pump boost circuit in the diagram;

[0016] Figure 3 A schematic diagram of the circuit structure of a charge pump boost circuit provided in an embodiment of the present invention;

[0017] Figure 4 A schematic diagram of the circuit structure of the logic control module in a charge pump boost circuit provided for an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of the circuit structure of a non-overlapping clock signal generation module in a logic control module provided in an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of the circuit structure of a first switch signal generation module provided in an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of the circuit structure of a second switch signal generation module provided in an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of a portion of the specific circuit structure in a charge pump boost circuit provided for an embodiment of the present invention;

[0022] Figure 9 Waveforms of two non-overlapping clock signals VN and VP provided for one embodiment of the present invention;

[0023] Figure 10 A waveform diagram of the first switching signal vb following the clock signal VN, provided for one embodiment of the present invention;

[0024] Figure 11 Waveform diagrams of a first switch signal, a first clock signal, and a second clock signal provided for one embodiment of the present invention;

[0025] Figure 12 The diagram shows the simulation results of the output voltage of an embodiment of the present invention and the prior art.

[0026] Figure 13 A simulation result diagram is provided for one embodiment of the present invention;

[0027] Figure 14 The diagram shows the power consumption simulation results of an embodiment of the present invention and the prior art.

[0028] Figure 15This is a schematic diagram of the structure of a MIM capacitor provided in one embodiment of the present invention.

[0029] Figure label:

[0030] 10 - Logic control module; 20 - Current source module; 30 - Drive module; 40 - Boost module;

[0031] 11-Non-overlapping clock signal generation module; 12-First switch signal generation module; 13-Second switch signal generation module;

[0032] 101 - First NOT gate; 102 - Second NOT gate; 103 - Third NOT gate; 104 - Fourth NOT gate; 105 - Fifth NOT gate; 106 - Sixth NOT gate; 107 - Seventh NOT gate; 108 - First NAND gate; 109 - Second NAND gate;

[0033] 110 - Eighth NOT gate; 111 - Ninth NOT gate; 112 - Tenth NOT gate; 113 - Eleventh NOT gate; 114 - Twelfth NOT gate; 115 - AND gate;

[0034] 116 - First D flip-flop; 117 - Second D flip-flop; 118 - XOR gate; 119 - Thirteenth NOT gate; 120 - Fourteenth NOT gate;

[0035] 50 - Substrate; 60 - First metal layer; 70 - Second metal layer; 71 - First region; 72 - Second region; 80 - Third metal layer; 90 - Insulating layer; 91 - Metal via. Detailed Implementation

[0036] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0037] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] In this invention, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between the associated objects, indicating that three relationships can exist.

[0039] like Figure 3 As shown, this embodiment of the invention provides a charge pump boost circuit, which may include: a logic control module 10, a current source module 20, a drive module 30, and a boost module 40;

[0040] Both the current source module 20 and the logic control module 10 are connected to the drive module 30; the drive module 30 is connected to the boost module 40; the current source module 20 is used to provide a stable voltage to the drive module 30; the drive module 30 includes at least a pull-up PMOS transistor.

[0041] The logic control module 10 is used to generate two non-overlapping clock signals based on the input clock source, and to generate a first switch signal and a second switch signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include the first clock signal and the second clock signal.

[0042] The logic control module 10 is used to control the switching of the drive module 30 based on two non-overlapping clock signals, a first switch signal, and a second switch signal, so that the drive module 30 can drive the boost module 40 to output the target voltage using a pull-up PMOS transistor.

[0043] like Figure 4 As shown, the logic control module 10 includes at least a non-overlapping clock signal generation module 11, a first switch signal generation module 12, and a second switch signal generation module 13. As previously mentioned, the non-overlapping clock signal generation module 11 is used to generate a non-overlapping first clock signal (e.g., represented by VN) and a non-overlapping second clock signal (e.g., represented by VP). Figure 4 In the first switch signal generation module 12, the non-overlapping clock signal generation module 11 is connected to the first switch signal generation module 12. The first switch signal generation module 12 is used to generate a first switch signal (e.g., represented by vb) based on the first clock signal VN. The second switch signal generation module 13 is connected to the non-overlapping clock signal generation module 11. The second switch signal generation module 13 is used to generate a second switch signal (e.g., represented by sw) based on the first clock signal VN and the second clock signal VP.

[0044] In one alternative implementation, such as Figure 5 As shown, the non-overlapping clock signal generation module includes a first NOT gate 101, a second NOT gate 102, a third NOT gate 103, a fourth NOT gate 104, a fifth NOT gate 105, a sixth NOT gate 106, a seventh NOT gate 107, a first NAND gate 108, a second NAND gate 109, a first capacitor C1, and a second capacitor C2.

[0045] Among them, the input terminal of the first NOT gate 101 and the first input terminal of the first NAND gate 108 are both connected to the clock source input terminal, and the clock source input terminal is connected to the clock source.

[0046] The output of the first NOT gate 101 is connected to the first input of the second NAND gate 109; the input of the second NOT gate 102 and the first terminal of the first capacitor C1 are both connected to the output of the second NAND gate 109; the second terminal of the second capacitor C2 is grounded; the input of the third NOT gate 103 is connected to the output of the second NOT gate 102; the input of the fourth NOT gate 104 and the second input of the first NAND gate 108 are both connected to the output of the third NOT gate 103; the output of the fourth NOT gate 104 outputs the first clock signal VN.

[0047] The input terminal of the fifth NOT gate 105 and the first terminal of the second capacitor C2 are both connected to the output terminal of the first NAND gate 108; the second terminal of the second capacitor C2 is grounded; the output terminal of the fifth NOT gate 105 is connected to the input terminal of the sixth NOT gate 106; the input terminal of the seventh NOT gate 107 and the second input terminal of the first NAND gate 108 are both connected to the output terminal of the sixth NOT gate 106; the output terminal of the seventh NOT gate 107 outputs the second clock signal VP.

[0048] In one alternative implementation, such as Figure 6 As shown, the first switch signal generation module includes:

[0049] The eighth NOT gate 110, the ninth NOT gate 111, the tenth NOT gate 112, the eleventh NOT gate 113, the twelfth NOT gate 114, the third capacitor C3, the fourth capacitor C4, and the AND gate 115;

[0050] In this configuration, the input of the eighth NOT gate 110 is connected to the output of the fourth NOT gate (connected to the first clock signal VN); the first terminal of the third capacitor C3 and the input of the ninth NOT gate 111 are both connected to the output of the eighth NOT gate 110; the second terminal of the third capacitor C3 is grounded; the input of the tenth NOT gate 112 and the first terminal of the fourth capacitor C4 are both connected to the output of the ninth NOT gate 111; the second terminal of the fourth capacitor C4 is grounded.

[0051] The output of the tenth NOT gate 112 is connected to the first input of the AND gate 115; the second input of the AND gate 115 is connected to the input of the eighth NOT gate 110; the output of the AND gate 115 is connected to the input of the eleventh NOT gate 113; the output of the eleventh NOT gate 113 is connected to the input of the twelfth NOT gate 114; the output of the twelfth NOT gate 114 outputs the first switching signal vb.

[0052] In one alternative implementation, such as Figure 7 As shown, the second switch signal generation module includes: a first D flip-flop 116, a second D flip-flop 117, an XOR gate 118, and a thirteenth NOT gate 119;

[0053] The clock input of the first D flip-flop 116 is connected to the output of the seventh NOT gate (connected to the VP signal), the first output of the first D flip-flop 116 is connected to the data input of the first D flip-flop 116, and the second output of the first D flip-flop 116 is connected to the first input of the XOR gate 118.

[0054] The clock input of the second D flip-flop 117 is connected to the output of the fourth NOT gate (connected to the VN signal); the first output of the second D flip-flop 117 is connected to the data input of the second D flip-flop 117; and the second output of the second D flip-flop 117 is connected to the second input of the XOR gate 118.

[0055] The output of XOR gate 118 is connected to the input of the thirteenth NOT gate 119; the output of the thirteenth NOT gate 119 outputs the second switching signal sw.

[0056] In one alternative implementation, such as Figure 8 As shown, the boost module includes a fifth capacitor C5, a first diode D1, a second diode D2, and a third diode D3;

[0057] Among them, the lower-level board VCB of the fifth capacitor C5 is connected to the driving module; the first end of the first diode D1 and the first end of the second diode D2 are both connected to the upper-level board VCT of the fifth capacitor C5; the second end of the first diode D1 is connected to the power supply voltage (7V); the second end of the second diode D2 and the first end of the third diode D3 are both connected to the output terminal of the boost module; the second end of the third diode D3 is connected to the driving module.

[0058] like Figure 8 As shown, the current source module 20 includes:

[0059] Current source I1, first low-voltage NMOS transistor MN1, second low-voltage NMOS transistor MN2, third low-voltage NMOS transistor MN3, fourth low-voltage NMOS transistor MN4 and fifth low-voltage NMOS transistor MN5;

[0060] Among them, the first terminal of the current source I1 is connected to the reference power supply; the drain of the first low-voltage NMOS transistor MN1, the gate of the first low-voltage NMOS transistor MN1, the gate of the second low-voltage NMOS transistor MN2, the gate of the third low-voltage NMOS transistor MN3, the gate of the fourth low-voltage NMOS transistor MN4 and the gate of the fifth low-voltage NMOS transistor MN5 are all connected to the second terminal of the current source I1.

[0061] The sources of the first low-voltage NMOS transistor MN1, the second low-voltage NMOS transistor MN2, the third low-voltage NMOS transistor MN3, the fourth low-voltage NMOS transistor MN4, and the fifth low-voltage NMOS transistor MN5 are all grounded.

[0062] The drains of the second low-voltage NMOS transistor MN2, the third low-voltage NMOS transistor MN3, the fourth low-voltage NMOS transistor MN4, and the fifth low-voltage NMOS transistor MN5 are all connected to the protection drive module 30.

[0063] like Figure 8 As shown, the driving module 30 includes a first high-voltage PMOS transistor MHP1, a second high-voltage PMOS transistor MHP2, a third high-voltage PMOS transistor MHP3, a fourth high-voltage PMOS transistor MHP4, a fifth high-voltage PMOS transistor MHP5, a first high-voltage NMOS transistor MHN1, a second high-voltage NMOS transistor MHN2, a third high-voltage NMOS transistor MHN3, a fourth high-voltage NMOS transistor MHN4, a fifth high-voltage NMOS transistor MHN5, a sixth low-voltage NMOS transistor MN6, a seventh low-voltage NMOS transistor MN7, an eighth low-voltage NMOS transistor MN8, a first resistor R1, a second resistor R2, a third resistor R3, a fourteenth NOT gate 120, and a Zener diode D4;

[0064] Among them, the third high-voltage PMOS transistor MHP3 is a pull-up PMOS transistor;

[0065] The sources of the first high-voltage PMOS transistor MHP1, the second high-voltage PMOS transistor MHP2, the third high-voltage PMOS transistor MHP3, the fourth high-voltage PMOS transistor MHP4, the fifth high-voltage PMOS transistor MHP5, the first terminal of the first resistor R1, the first terminal of the second resistor R2, the first terminal of the third resistor R3, and the first terminal of the Zener diode D4 are all connected to the high-voltage power supply to access the high-voltage VM voltage.

[0066] The second terminal of the first resistor R1 and the gate (VR port) of the second high-voltage PMOS transistor MHP2 are both connected to the drain of the second high-voltage NMOS transistor MHN2; the source of the second high-voltage NMOS transistor MHN2 is connected to the drain of the second low-voltage NMOS transistor MN2; the gate of the second high-voltage NMOS transistor MHN2 is connected to the second switching signal sw.

[0067] The second terminal of the second resistor R2 and the gate (VH port) of the first high-voltage PMOS transistor MHP1 are both connected to the drain of the third high-voltage NMOS transistor MHN3; the source of the third high-voltage NMOS transistor MHN3 is connected to the drain of the third low-voltage NMOS transistor MN3; the gate of the third high-voltage NMOS transistor MHN3 is connected to the first terminal of the fourteenth NOT gate 120, and the second terminal of the fourteenth NOT gate 120 is connected to the second clock signal VP.

[0068] The gate of the fourth high-voltage PMOS transistor MHP4, the drain of the fourth high-voltage PMOS transistor MHP4, and the gate of the fifth high-voltage PMOS transistor MHP5 are all connected to the drain of the first high-voltage PMOS transistor MHP1.

[0069] The drain of the fourth high-voltage NMOS transistor MHN4 is connected to the drain of the fourth high-voltage PMOS transistor MHP4; the gate of the fourth high-voltage NMOS transistor MHN4 is connected to the enable signal EN; the source of the fourth high-voltage NMOS transistor MHN4 is connected to the drain of the sixth low-voltage NMOS transistor MN6.

[0070] The drain of the fifth high-voltage NMOS transistor MHN5 is connected to the drain of the fifth high-voltage PMOS transistor MHP5; the gate of the fifth high-voltage NMOS transistor MHN5 is connected to the enable signal EN; the source of the fifth high-voltage NMOS transistor MHN5 is connected to the drain of the seventh low-voltage NMOS transistor MN7.

[0071] The source of the sixth low-voltage NMOS transistor MN6 and the source of the seventh low-voltage NMOS transistor MN7 are both connected to the drain of the fourth low-voltage NMOS transistor MN4.

[0072] The source of the sixth low-voltage NMOS transistor MN6 and the source of the seventh low-voltage NMOS transistor MN7 are both connected to the drain of the eighth low-voltage NMOS transistor MN8; the source of the eighth low-voltage NMOS transistor MN8 is connected to the drain of the fifth low-voltage NMOS transistor MN5; the gate of the eighth low-voltage NMOS transistor MN8 is connected to the first switching signal vb.

[0073] The second terminal of the third resistor R3, the second terminal of the Zener diode D4, the drain of the second high-voltage PMOS transistor MHP2, and the gate of the third high-voltage PMOS transistor MHP3 are all connected to the drain of the fifth high-voltage PMOS transistor MHP5.

[0074] The drain of the third high-voltage PMOS transistor MHP3 is connected to the drain of the first high-voltage NMOS transistor MHN1; the source of the first high-voltage NMOS transistor MHN1 is grounded.

[0075] The drains of the third high-voltage PMOS transistor MHP3 and the first high-voltage NMOS transistor MHN1 are both connected to the lower stage VCB of the fifth capacitor C5.

[0076] Regarding the working process of the charge pump boost circuit: When the second clock signal is high and the first clock signal is low, the gate voltage of the first high-voltage PMOS transistor is high to turn off the first high-voltage PMOS transistor; and when the second switch signal is high, the second high-voltage PMOS transistor turns on to charge the gate of the third high-voltage PMOS transistor to lock the third high-voltage PMOS transistor and turn on the first high-voltage NMOS transistor.

[0077] When the first clock signal switches to a high level and the second clock signal switches to a low level, the first high-voltage PMOS transistor turns on, pulling up the gate voltages of the fourth and fifth high-voltage PMOS transistors to turn them off; the first switching signal turns on the eighth low-voltage NMOS transistor; the fifth low-voltage NMOS transistor acts as a mirror current source to amplify the current source I1 to turn on the third high-voltage PMOS transistor; the second high-voltage PMOS transistor is turned off before the third high-voltage PMOS transistor turns on; the Zener diode is used to protect the third high-voltage PMOS transistor.

[0078] When the first clock signal switches to a low level and the second clock signal switches to a high level, the second high-voltage PMOS transistor turns on, the third high-voltage PMOS transistor turns off, and the first high-voltage PMOS transistor turns off at the same time. Current flows from the fourth high-voltage PMOS transistor to the fourth low-voltage NMOS transistor.

[0079] It should be noted that, Figure 8 In this context, VH represents a port named VH, and VR represents a port named VR. Neither of them indicates voltage or signal; this is done to avoid overly complex circuit connections. VM represents high voltage, and VSS represents 0V voltage.

[0080] In layman's terms, the working principle of the logic control module is as follows:

[0081] The CLK signal (clock source) undergoes the following process: Figure 5 After the non-overlapping clock signal generation module shown, it generates the following: Figure 9 The two clock signals VN and VP shown are non-overlapping, with a dead time of 5ns for both VP and VN.

[0082] VN signal passes through Figure 6 After the first switch signal generation module shown, a first switch signal vb with a pulse width of 5ns following the VN signal is generated, and the waveform is as follows. Figure 10 As shown.

[0083] In addition, VN and VP signals pass through Figure 7 After the switch signal generation module shown, a second switch signal sw is generated, as follows: Figure 11 As shown, the rising edge of sw occurs before VP is high and the falling edge occurs after VN is high, and it does not overlap with VP and VN.

[0084] VP, VN, sw, and vb together control the on and off of the charge pump boost circuit.

[0085] In one specific implementation, CLK is the input clock source port with a frequency of 10MHz. When the clock signal arrives and the EN terminal is high, the charge pump boost circuit starts to work.

[0086] When VP is high and VN is low, the VH port (i.e., the gate of MHP1) is at the VM voltage, so MHP1 is turned off. At this time, the second switching signal sw is high, which turns on MHP2, charging the gate of MHP3 to the VM voltage and locking MHP3 (pull-up PMOS transistor). MHN1 is turned on, discharging the VCB of the lower-level board of C5 to VSS (0V).

[0087] When VN switches high and VP switches low, the voltage at the VH port decreases, MHP1 turns on, and instantly pulls the gate voltages of MHP4 and MHP5 up to VM, thus turning off MHP4 and MHP5. The VN signal then generates a narrow pulse signal (i.e., the first switching signal) vb through a delay chain. This pulse signal vb turns on MN8, and MN5 acts as a mirror current source, replicating the magnitude of current source I1 by tens of times. This replicated current is injected into the gate of MHP3, quickly turning it on. Before MHP3 turns on, the voltage at the VR port is pulled up to the VM voltage, turning off MHP2 and preventing the large current provided by MN5 from flowing away from MHP2. Simultaneously, a Zener diode D4 is added at the gate-source terminal of MHP3 for protection.

[0088] Next, when VN switches to low level and VP switches to high level, MHP2 turns on, quickly pulling the gate voltage of MHP3 to the VM voltage level to quickly turn off MHP3. At the same time, MHP1 turns off, and the current flows normally through MHP4 to MN4.

[0089] The above operating logic solves the problem of simultaneous conduction of the pull-up MOSFET (MHP3) and pull-down MOSFET (MHN1) in the charge pump boost circuit, greatly improving the boost efficiency of the charge pump.

[0090] In existing technologies Figure 2 The circuit structure of the circuit and the charge pump boost circuit in the embodiment of the present invention are compared and simulated to obtain the following results: Figure 12 The simulation comparison results are shown in the figure. Figure 12 The diagram illustrates the output voltages of two charge pumps. Red represents the output voltage of the charge pump boost circuit in this embodiment, while blue represents the output voltage of a charge pump in the prior art. With a power supply voltage of 20V, the charge pump boost circuit in this embodiment can boost the voltage from 20V to 26.7V, while the prior art boosts it to 26.1V. According to the formula:

[0091]

[0092] Calculations show that the boost efficiency of the embodiments of the present invention is improved by 10% compared with the prior art. δ represents the boost efficiency.

[0093] Furthermore, in this embodiment of the invention, the cooperation between the drive module and the logic control module improves the switching speed of MHP3 and MNH1, resulting in a dead time of approximately 4-5 ns. Figure 13 As shown, combined with Figure 14 Simulation results show that, under the premise of 10MHz frequency and 20V supply voltage, the average power consumption of the charge pump boost circuit in this design (referring to the design in this embodiment of the invention) is 22.4mW. Under the same conditions, the total average current of the charge pump boost circuit in the prior art is 2.46mA, and the average power consumption is 49.2mW. The circuit power consumption of this embodiment of the invention is reduced by 54%, which is a significant reduction in power consumption.

[0094] In one alternative implementation, such as Figure 15 As shown, the fifth capacitor is a MIM capacitor; the MIM capacitor includes at least a substrate 50 and a first metal layer 60, a second metal layer 70, and a third metal layer 80 on the substrate; the second metal layer 70 is above the first metal layer 60, the third metal layer 80 is above the second metal layer 70, and an insulating layer 90 is between the first metal layer 60 and the second metal layer 70; an insulating layer 90 is between the second metal layer 70 and the third metal layer 80; the first metal layer 60 is the lower electrode plate;

[0095] The second metal layer 70 includes a first region 71, a second region 72, and a spacer region. The first region 71 and the second region 72 are separated by the spacer region, and the first region 71 surrounds the second region 72. The second region 72 is the upper electrode plate. Multiple metal through-holes 91 are present on the insulating layer 90 and the second metal layer 70, allowing the third metal layer 80 to be connected to the first metal layer 60 through the metal through-holes 91. In other words, the third metal layer 80 is also connected to the lower electrode plate.

[0096] In the prior art, for example Figure 2 The boost capacitor c0 in the circuit uses a MIM capacitor. Existing MIM capacitors only include two metal layers. One metal layer serves as the lower stage of the capacitor, and the other metal layer serves as the upper stage of the capacitor and is connected to two diodes. The connection between the upper stage of the capacitor and the two diodes is defined as the VCT node. There is a parasitic capacitance at this VCT node. This parasitic capacitance will cause voltage division during each charge pump boost process, reducing the output voltage of the charge pump.

[0097] In detail, for the MIM capacitor with only two metal layers in the prior art, it is understandable that the parasitic capacitance mainly includes two types of capacitors. The first type of capacitor is the parasitic capacitance C11 between the metal traces near the boost capacitor, and the second type of capacitor is the parasitic capacitance CC from the upper board of the boost capacitor to the substrate. The influence of these two types of capacitors on the output voltage of the charge pump is shown in expression (1). Vo is the ideal output voltage of the charge pump when there is no parasitic capacitance, Vcp is the actual output voltage after voltage division by the parasitic capacitance, and C11 is the capacitance value of the boost capacitor. According to formula (1), the larger the parasitic capacitance CC is, the smaller the output voltage Vcp of the charge pump. At this time, it is necessary to increase the size of C11 to alleviate the problem. However, increasing C11 will increase the area cost of the circuit.

[0098]

[0099] To address the aforementioned problems, this invention improves and redesigns the structure of the existing MIM capacitor with only two metal layers: a third metal layer is added on top of the second metal layer. Furthermore, the second metal layer is divided into an intermediate metal layer and surrounding metal layers, with the intermediate metal layer serving as the lower-level plate. This allows for the construction of a boost capacitor (…). Figure 8 The lower stage board of the fifth capacitor (C5) can be completely surrounded by the surrounding metal layers and the third metal layer, and isolated from other metal traces in the circuit layout of the entire charge pump boost circuit.

[0100] Combination Figure 15 It can be assumed that C21 is the parasitic capacitance from the upper plate to the third metal layer M3. In this structure, the third metal layer and the first metal layer (lower plate of the capacitor) are connected through metal vias. Therefore, the parasitic capacitance from the second metal layer to the third metal layer is actually equivalent to a portion of C11. Furthermore, because the first metal layer isolates the second metal layer from the substrate, the parasitic capacitance from the second metal layer to the substrate is almost negligible. Additionally, since the upper plate of the capacitor is also surrounded by a surrounding metal layer, which is connected to the third and first metal layers, it blocks the connection between the upper plate of the capacitor and other metal traces, significantly reducing the parasitic capacitance.

[0101] With the above improvements to the boost capacitor structure, the parasitic capacitance in this embodiment of the invention can reach approximately 60 fF, while the parasitic capacitance in existing designs is approximately 200 fF, reducing the parasitic capacitance by 70%. Thanks to the very low parasitic capacitance in this embodiment, the output voltage of the charge pump boost circuit is improved. The calculation process is as follows:

[0102] V0 = V M +6V(3)

[0103]

[0104] In this design, the total parasitic capacitance is 60fF (C+CC)1, while in the prior art, the total parasitic capacitance is 200fF (C+CC)2. M The power supply voltage is 30V, V0 is the output voltage of the charge pump, and V CP1 V represents the output voltage after voltage division by parasitic capacitance in the existing design. CP2 The output voltage of this design after voltage division by parasitic capacitance.

[0105] In summary, the charge pump boost circuit provided in this embodiment of the invention has further improved boost efficiency, power consumption and utilization of reference voltage compared with the prior art, and has also solved the problem of charge pumps being susceptible to parasitic parameter interference.

[0106] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other device can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0107] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A charge pump boost circuit, characterized in that, include: Logic control module, current source module, drive module, and boost module; Both the current source module and the logic control module are connected to the drive module; the drive module is connected to the boost module; the current source module is used to provide a stable voltage to the drive module; the drive module includes at least a pull-up PMOS transistor; The logic control module is used to generate two non-overlapping clock signals based on the input clock source, and to generate a first switch signal and a second switch signal based on the two non-overlapping clock signals; the two non-overlapping clock signals include the first clock signal and the second clock signal. The logic control module is used to control the switching of the drive module based on the two non-overlapping clock signals, the first switch signal and the second switch signal, so that the drive module uses the pull-up PMOS transistor to drive the boost module to output the target voltage; The logic control module includes at least a non-overlapping clock signal generation module and a first switch signal generation module. The first switch signal generation module is connected to the non-overlapping clock signal generation module, and the first switch signal generation module is used to generate the first switch signal based on the first clock signal. The first switch signal generation module includes: an eighth NOT gate, a ninth NOT gate, a tenth NOT gate, an eleventh NOT gate, a twelfth NOT gate, a third capacitor, a fourth capacitor, and an AND gate; The input terminal of the eighth NOT gate is connected to the output terminal of the fourth NOT gate in the non-overlapping clock signal generation module; the first terminal of the third capacitor and the input terminal of the ninth NOT gate are both connected to the output terminal of the eighth NOT gate; the second terminal of the third capacitor is grounded; the input terminal of the tenth NOT gate and the first terminal of the fourth capacitor are both connected to the output terminal of the ninth NOT gate; the second terminal of the fourth capacitor is grounded. The output of the tenth NOT gate is connected to the first input of the AND gate; the second input of the AND gate is connected to the input of the eighth NOT gate; the output of the AND gate is connected to the input of the eleventh NOT gate; the output of the eleventh NOT gate is connected to the input of the twelfth NOT gate; and the output of the twelfth NOT gate outputs the first switch signal.

2. The charge pump boost circuit according to claim 1, characterized in that, The non-overlapping clock signal generation module includes a first NOT gate, a second NOT gate, a third NOT gate, a fourth NOT gate, a fifth NOT gate, a sixth NOT gate, a seventh NOT gate, a first NAND gate, a second NAND gate, a first capacitor, and a second capacitor; Wherein, the input terminal of the first NOT gate and the first input terminal of the first NAND gate are both connected to the clock source input terminal, and the clock source input terminal is connected to the clock source; The output of the first NOT gate is connected to the first input of the second NAND gate; the input of the second NOT gate and the first terminal of the first capacitor are both connected to the output of the second NAND gate; the second terminal of the first capacitor is grounded; the input of the third NOT gate is connected to the output of the second NOT gate; the input of the fourth NOT gate and the second input of the first NAND gate are both connected to the output of the third NOT gate; the output of the fourth NOT gate outputs the first clock signal. The input terminal of the fifth NOT gate and the first terminal of the second capacitor are both connected to the output terminal of the first NAND gate; The second terminal of the second capacitor is grounded; the output terminal of the fifth NOT gate is connected to the input terminal of the sixth NOT gate; the input terminal of the seventh NOT gate and the second input terminal of the first NAND gate are both connected to the output terminal of the sixth NOT gate; the output terminal of the seventh NOT gate outputs the second clock signal.

3. The charge pump boost circuit according to claim 2, characterized in that, The logic control module further includes a second switch signal generation module, which is connected to the non-overlapping clock signal generation module. The second switch signal generation module is used to generate a second switch signal based on the first clock signal and the second clock signal. The second switch signal generation module includes: a first D flip-flop, a second D flip-flop, an XOR gate, and a thirteenth NOT gate; Wherein, the clock input terminal of the first D flip-flop is connected to the output terminal of the seventh NOT gate, the first output terminal of the first D flip-flop is connected to the data input terminal of the first D flip-flop, and the second output terminal of the first D flip-flop is connected to the first input terminal of the XOR gate; The clock input of the second D flip-flop is connected to the output of the fourth NOT gate; the first output of the second D flip-flop is connected to the data input of the second D flip-flop; and the second output of the second D flip-flop is connected to the second input of the XOR gate. The output of the XOR gate is connected to the input of the thirteenth NOT gate; the output of the thirteenth NOT gate outputs the second switching signal.

4. The charge pump boost circuit according to claim 3, characterized in that, The boost module includes a fifth capacitor, a first diode, a second diode, and a third diode; The lower stage board of the fifth capacitor is connected to the driving module; the first end of the first diode and the first end of the second diode are both connected to the upper stage board of the fifth capacitor; the second end of the first diode is connected to the power supply voltage; the second end of the second diode and the first end of the third diode are both connected to the output terminal of the boost module; and the second end of the third diode is connected to the driving module.

5. The charge pump boost circuit according to claim 4, characterized in that, The current source module includes: a current source, a first low-voltage NMOS transistor, a second low-voltage NMOS transistor, a third low-voltage NMOS transistor, a fourth low-voltage NMOS transistor, and a fifth low-voltage NMOS transistor; The first terminal of the current source is connected to a reference power supply; the drain of the first low-voltage NMOS transistor, the gate of the first low-voltage NMOS transistor, the gate of the second low-voltage NMOS transistor, the gate of the third low-voltage NMOS transistor, the gate of the fourth low-voltage NMOS transistor, and the gate of the fifth low-voltage NMOS transistor are all connected to the second terminal of the current source. The sources of the first low-voltage NMOS transistor, the second low-voltage NMOS transistor, the third low-voltage NMOS transistor, the fourth low-voltage NMOS transistor, and the fifth low-voltage NMOS transistor are all grounded.

6. The charge pump boost circuit according to claim 5, characterized in that, The driving module includes a first high-voltage PMOS transistor, a second high-voltage PMOS transistor, a third high-voltage PMOS transistor, a fourth high-voltage PMOS transistor, a fifth high-voltage PMOS transistor, a first high-voltage NMOS transistor, a second high-voltage NMOS transistor, a third high-voltage NMOS transistor, a fourth high-voltage NMOS transistor, a fifth high-voltage NMOS transistor, a sixth low-voltage NMOS transistor, a seventh low-voltage NMOS transistor, an eighth low-voltage NMOS transistor, a first resistor, a second resistor, a third resistor, a fourteenth NOT gate, and a Zener diode; The third high-voltage PMOS transistor is the pull-up PMOS transistor; The source of the first high-voltage PMOS transistor, the source of the second high-voltage PMOS transistor, the source of the third high-voltage PMOS transistor, the source of the fourth high-voltage PMOS transistor, the source of the fifth high-voltage PMOS transistor, the first terminal of the first resistor, the first terminal of the second resistor, the first terminal of the third resistor, and the first terminal of the Zener diode are all connected to a high-voltage power supply to receive a high-voltage voltage. The second terminal of the first resistor and the gate of the second high-voltage PMOS transistor are both connected to the drain of the second high-voltage NMOS transistor; the source of the second high-voltage NMOS transistor is connected to the drain of the second low-voltage NMOS transistor; the gate of the second high-voltage NMOS transistor is connected to the second switching signal. The second terminal of the second resistor and the gate of the first high-voltage PMOS transistor are both connected to the drain of the third high-voltage NMOS transistor; the source of the third high-voltage NMOS transistor is connected to the drain of the third low-voltage NMOS transistor; the gate of the third high-voltage NMOS transistor is connected to the first terminal of the fourteenth NOT gate, and the second terminal of the fourteenth NOT gate is connected to the second clock signal. The gate of the fourth high-voltage PMOS transistor, the drain of the fourth high-voltage PMOS transistor, and the gate of the fifth high-voltage PMOS transistor are all connected to the drain of the first high-voltage PMOS transistor. The drain of the fourth high-voltage NMOS transistor is connected to the drain of the fourth high-voltage PMOS transistor; the gate of the fourth high-voltage NMOS transistor is connected to an enable signal; the source of the fourth high-voltage NMOS transistor is connected to the drain of the sixth low-voltage NMOS transistor. The drain of the fifth high-voltage NMOS transistor is connected to the drain of the fifth high-voltage PMOS transistor; the gate of the fifth high-voltage NMOS transistor is connected to the enable signal; the source of the fifth high-voltage NMOS transistor is connected to the drain of the seventh low-voltage NMOS transistor. The source of the sixth low-voltage NMOS transistor and the source of the seventh low-voltage NMOS transistor are both connected to the drain of the fourth low-voltage NMOS transistor. The source of the sixth low-voltage NMOS transistor and the source of the seventh low-voltage NMOS transistor are both connected to the drain of the eighth low-voltage NMOS transistor; the source of the eighth low-voltage NMOS transistor is connected to the drain of the fifth low-voltage NMOS transistor; the gate of the eighth low-voltage NMOS transistor is connected to the first switching signal. The second terminal of the third resistor, the second terminal of the Zener diode, the drain of the second high-voltage PMOS transistor, and the gate of the third high-voltage PMOS transistor are all connected to the drain of the fifth high-voltage PMOS transistor. The drain of the third high-voltage PMOS transistor is connected to the drain of the first high-voltage NMOS transistor; the source of the first high-voltage NMOS transistor is grounded. The drain of the third high-voltage PMOS transistor and the drain of the first high-voltage NMOS transistor are both connected to the lower stage board of the fifth capacitor.

7. The charge pump boost circuit according to claim 6, characterized in that, When the second clock signal is high and the first clock signal is low, the gate voltage of the first high-voltage PMOS transistor is high to turn off the first high-voltage PMOS transistor; and when the second switch signal is high, the second high-voltage PMOS transistor turns on to charge the gate of the third high-voltage PMOS transistor to lock the third high-voltage PMOS transistor and turn on the first high-voltage NMOS transistor. When the first clock signal switches to a high level and the second clock signal switches to a low level, the first high-voltage PMOS transistor turns on, pulling up the gate voltages of the fourth and fifth high-voltage PMOS transistors to turn them off; the first switching signal turns on the eighth low-voltage NMOS transistor; the fifth low-voltage NMOS transistor acts as a current mirror to amplify the current source, turning on the third high-voltage PMOS transistor; the second high-voltage PMOS transistor is turned off before the third high-voltage PMOS transistor turns on; the Zener diode is used to protect the third high-voltage PMOS transistor. When the first clock signal switches to a low level and the second clock signal switches to a high level, the second high-voltage PMOS transistor turns on, the third high-voltage PMOS transistor turns off, and the first high-voltage PMOS transistor turns off at the same time. Current flows from the fourth high-voltage PMOS transistor to the fourth low-voltage NMOS transistor.

8. The charge pump boost circuit according to claim 4, characterized in that, The fifth capacitor is a MIM capacitor; The MIM capacitor includes at least a substrate and a first metal layer, a second metal layer, and a third metal layer on the substrate; The first metal layer is the lower electrode of the fifth capacitor; The second metal layer includes a first region, a second region, and a spacer region, wherein the first region and the second region are separated by the spacer region, and the first region surrounds the second region; the second region is the upper electrode of the fifth capacitor; The third metal layer is also connected to the lower plate.

9. The charge pump boost circuit according to claim 8, characterized in that, An insulating layer is formed between the first metal layer and the second metal layer; an insulating layer is formed between the second metal layer and the third metal layer; and the spacing region is also an insulating layer.

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