SAR ADC structure with embedded two-bit auxiliary quantizer

Abstract

The invention discloses an SARADC structure with an embedded two-bit auxiliary quantizer, and relates to the technical field of semiconductor devices. Comprising an input voltage module, a high-order capacitor array module, a bridging capacitor module and a comparator module. According to the SARADC structure embedded with the two-bit auxiliary quantizer, on the premise of wide voltage input, a comparison result of a most significant bit (MSB) and a second significant bit (MSB-1) is generated through the two-bit auxiliary quantizer, switching of the switch array and setting and resetting of the high-bit capacitor are controlled according to the comparison result so as to participate in the quantization process of the SARADC, and the quantization efficiency of the SARADC is improved. According to the invention, the voltage range of the input ends VN and VP of the comparator is controlled within 1.8 V, that is to say, quantitative processing of input signals on a low-voltage device under the condition of wide voltage input is realized, so that the SARADC meets the requirements of wide voltage input and low working voltage, and the technical indexes of speed, power consumption and the like of the SARADC are optimized.

Description

Technical Field

[0001] The invention relates to the field of semiconductor devices, and in particular to a SAR ADC structure with a two-bit auxiliary quantizer embedded therein. Background Art

[0002] At present, the successive approximation analog-to-digital converter (SAR ADC) has gradually become one of the widely used ADC architectures in the market due to its advantages such as simple structure, low power consumption and high precision. In recent years, with the advancement of semiconductor technology and the increasing demand for high-performance and low-power devices, the research on SAR ADC has continued to deepen, covering noise shaping technology, dynamic range optimization, mismatch correction and other aspects. These studies not only improve the conversion accuracy and sampling rate of SAR ADC, but also effectively reduce its power consumption, making it show broad prospects in emerging applications such as the Internet of Things, medical monitoring and industrial automation. However, SAR ADC still faces many challenges under the requirements of high resolution and high-speed sampling.

[0003] In the prior art, the working process of the successive approximation analog-to-digital converter SAR ADC is mainly divided into a sampling stage and a quantization stage. For the SAR ADC with lower plate sampling, the sampling process is mainly performed by the lower plate of some capacitors in the capacitor digital-to-analog converter of the SAR ADC to sample the input signal. Due to the environmental requirements of multiple voltage domains, the actual SAR ADC application process needs to meet the wide range fluctuation of the analog input, and the functional level requires the voltage input to meet the maximum reference voltage range. Therefore, the sampling range of the capacitor sampled by the SAR ADC should also be the reference voltage range. After the sampling stage, the comparator needs to compare the upper plate voltages at the N and P terminals and switch the lower plate switch to achieve the successive approximation of the upper plate voltage and complete the quantization process.

[0004] However, the comparison speed of the comparator significantly affects the operating speed of the SAR ADC. The power consumption of the comparator accounts for a large part of the total power consumption of the SAR ADC. In order to improve the operating speed of the SAR ADC and reduce power consumption, the comparator and other modules in the SAR ADC use low-voltage devices. The input common-mode voltage and input voltage swing of the comparator need to be in the low-voltage domain. It is impossible to implement sampling and calculation of input signals on low-voltage devices at higher input voltages.

[0005] Therefore, under the condition of wide input voltage, realizing the quantization of the input signal of the SAR ADC low-voltage device becomes the key issue in designing the SAR ADC to meet the requirements of wide voltage input and low operating voltage. Summary of the invention

[0006] Based on this, it is necessary to provide a SARADC structure with a built-in two-bit auxiliary quantizer to address the above technical problems.

[0007] The present invention provides a SAR ADC structure with a two-bit auxiliary quantizer embedded therein, comprising:

[0008] Input voltage module, high-position capacitor array module, switch array module and comparator module;

[0009] The input voltage module includes: a voltage input terminal V IN , voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFP and the negative terminal of the reference voltage V REFN ;

[0010] The high-position capacitor array module includes: the sixth-position capacitor C6N and the redundant capacitor C6P_R of the N-end circuit, and the sixth-position capacitor C6P and the capacitor C6P_R of the P-end circuit;

[0011] The switch array module includes: switches SWNR6 and SWN6 of the N-end circuit, and switches SWPR6 and SWP6 of the P-end circuit;

[0012] The comparator module comprises: a comparator positive input terminal VN and a comparator negative input terminal VP;

[0013] Voltage input terminal V IN , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6N_R is connected through the switch SWNR6, and the lower plate of the sixth capacitor C6N is connected through the switch SWN6; the upper plate of the redundant capacitor C6N_R and the upper plate of the sixth capacitor C6N are connected to the positive input terminal VN of the comparator.

[0014] Voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6P_R is connected through the switch SWPR6, and the lower plate of the sixth capacitor C6P is connected through the switch SWP6; the upper plate of the redundant capacitor C6P_R and the upper plate of the sixth capacitor C6P are connected to the negative input terminal VP of the comparator.

[0015] Preferably, the switch array module further comprises switches SWN1, SWN2, SWN3, SWN4, SWN5, SWNR of the N-end circuit and switches SWP1, SWP2, SWP3, SWP4, SWP5, SWPR of the P-end circuit.

[0016] Preferably, the high-position capacitor array module further comprises: a first capacitor C1N, a second capacitor C2N, a third capacitor C3N, a fourth capacitor C4N, a fifth capacitor C5N and a capacitor CRN of the N-end circuit; a first capacitor C1P, a second capacitor C2P, a third capacitor C3P, a fourth capacitor C4P, a fifth capacitor C5P and a capacitor CRP of the P-end circuit;

[0017] The first capacitor C1N, the second capacitor C2N, the third capacitor C3N, the fourth capacitor C4N, the fifth capacitor C5N and the upper plate of the capacitor CRN of the N-terminal circuit are all connected to the positive input terminal VN of the comparator through the switch SWN;

[0018] The upper plates of the first capacitor C1P, the second capacitor C2P, the third capacitor C3P, the fourth capacitor C4P, the fifth capacitor C5P and the capacitor CRP of the P-end circuit are all connected to the negative input terminal VP of the comparator through the switch SWP;

[0019] Among them, the capacitance of the first capacitor C1N and C1P is 32C; the capacitance of the second capacitor C2N and C2P is 16C; the capacitance of the third capacitor C3N and C3P is 8C; the capacitance of the fourth capacitor C4N and C4P is 4C, the capacitance of the fifth capacitor C5N and C5P is 2C, the capacitance of the sixth capacitor C6N and C6P is 1C; the capacitance of capacitor CRN and capacitor CRP is 8C.

[0020] Preferably, the high-position capacitor array module comprises:

[0021] For the N-terminal circuit, the voltage input terminal V IN Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN , respectively connecting the lower plate of the first capacitor C1N, the lower plate of the second capacitor C2N, the lower plate of the third capacitor C3N, the lower plate of the fourth capacitor C4N and the lower plate of the fifth capacitor C5N through switches SWN1, SWN2, SWN3, SWN4 and SWN5 of the N-terminal circuit;

[0022] For the P-terminal circuit, the voltage input terminal V IP Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN, respectively connected through switches SWP1, SWP2, SWP3, SWP4 and SWP5 of the P-end circuit, the lower plate of the first capacitor C1P, the lower plate of the second capacitor C2P, the lower plate of the third capacitor C3P, the fourth capacitor C4P and the lower plate of the fifth capacitor C5P.

[0023] Preferably, the input voltage module further comprises: a comparator common mode voltage input terminal V CM _ COMP The positive input terminal VN and the negative input terminal VP of the comparator are connected through the switch SWN_CM0 and the switch SWN_CM1 respectively.

[0024] Preferably, the reference voltage positive terminal V REFP Or the negative terminal of the reference voltage V REFN , the lower plate of capacitor CRN is connected through switch SWNR, and the lower plate of capacitor CRP is connected through switch SWPR.

[0025] Preferably, the capacitor CRN and the capacitor CRP are used to raise the voltage of the upper plate to prevent leakage.

[0026] Preferably, it also includes: a capacitor C DUMMYN and capacitor C DUMMYP ;

[0027] The capacitor C DUMMYN The upper plate of the capacitor C is connected to the positive input terminal VN of the comparator through the switch SWN; DUMMYP The upper plate of the transistor is connected to the negative input terminal VP of the comparator through the switch SWP.

[0028] The capacitor C DUMMYN and capacitor C DUMMYP The lower plates are all grounded;

[0029] Among them, the capacitor C DUMMYN and C DUMMYP Used for capacitor matching, the capacitor size is 16C.

[0030] Preferably, it also includes: a low-position capacitor array CDACL, through a bridge capacitor C BRN and bridge capacitor C BRP Connect the positive input terminal VN and the negative input terminal VP of the comparator respectively.

[0031] Preferably, it further comprises: a capacitor array control logic module SAR ADC Logic, which is used to control the switching of switches according to the output result of the comparator to realize a successive approximation quantization mode.

[0032] Compared with the prior art, the SAR ADC structure with a two-bit auxiliary quantizer embedded in the present invention has the following beneficial effects:

[0033] The present invention provides a SAR ADC structure with a two-bit auxiliary quantizer embedded therein. Under the premise of wide voltage input, the two-bit auxiliary quantizer (high-bit capacitors C6N and C6P and redundant capacitors C6P_R and C6N_R) are reset by switching switches to generate the most significant bit (MSB) and the second most significant bit (MSB-1), and the setting and resetting of other high-bit capacitors participating in the SAR ADC quantization process are controlled according to the comparison results of the most significant bit and the second most significant bit, thereby avoiding leakage caused by the upper plate voltage VN and VP being too high or too low, and controlling the voltage range of the comparator input terminals VN and VP within the low working voltage of 1.8V, that is, realizing the quantization processing of the input signal on the low-voltage device under the wide voltage input condition, so that the SAR ADC meets the requirements of wide voltage input and low working voltage, and optimizes the technical indicators of the SAR ADC such as speed and power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A circuit diagram of a SAR ADC structure with a two-bit auxiliary quantizer embedded in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0036] In one embodiment, a circuit diagram of a SAR ADC structure with a two-bit auxiliary quantizer embedded is provided, such as Figure 1 As shown, including:

[0037] An input voltage module, a high-position capacitor array module, a low-position capacitor array module, a switch array module, a bridge capacitor module and a comparator module;

[0038] Input voltage module, high-position capacitor array module, switch array module and comparator module;

[0039] The input voltage module includes: a voltage input terminal V IN , voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFP and the negative terminal of the reference voltage V REFN ;

[0040] The high-position capacitor array module includes: the sixth-position capacitor C6N and the redundant capacitor C6P_R of the N-end circuit, and the sixth-position capacitor C6P and the capacitor C6P_R of the P-end circuit;

[0041] The switch array module includes: switches SWNR6 and SWN6 of the N-end circuit, and switches SWPR6 and SWP6 of the P-end circuit;

[0042] The comparator module comprises: a comparator positive input terminal VN and a comparator negative input terminal VP;

[0043] Voltage input terminal V IN , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6N_R is connected through the switch SWNR6, and the lower plate of the sixth capacitor C6N is connected through the switch SWN6; the upper plate of the redundant capacitor C6N_R and the upper plate of the sixth capacitor C6N are connected to the positive input terminal VN of the comparator.

[0044] Voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6P_R is connected through the switch SWPR6, and the lower plate of the sixth capacitor C6P is connected through the switch SWP6; the upper plate of the redundant capacitor C6P_R and the upper plate of the sixth capacitor C6P are connected to the negative input terminal VP of the comparator.

[0045] In addition, the switch array module further includes switches SWN1, SWN2, SWN3, SWN4, SWN5, SWNR of the N-end circuit and switches SWP1, SWP2, SWP3, SWP4, SWP5, SWPR of the P-end circuit.

[0046] In addition, the high-position capacitor array module also includes: a first capacitor C1N, a second capacitor C2N, a third capacitor C3N, a fourth capacitor C4N, a fifth capacitor C5N and a capacitor CRN of the N-end circuit; a first capacitor C1P, a second capacitor C2P, a third capacitor C3P, a fourth capacitor C4P, a fifth capacitor C5P and a capacitor CRP of the P-end circuit;

[0047] The first capacitor C1N, the second capacitor C2N, the third capacitor C3N, the fourth capacitor C4N, the fifth capacitor C5N and the upper plate of the capacitor CRN of the N-terminal circuit are connected to the positive input terminal VN of the comparator through the switch SWN;

[0048] The upper plates of the first capacitor C1P, the second capacitor C2P, the third capacitor C3P, the fourth capacitor C4P, the fifth capacitor C5P and the capacitor CRP of the P-end circuit are all connected to the negative input terminal VP of the comparator through the switch SWP;

[0049] Among them, the capacitance of the first capacitor C1N and C1P is 32C; the capacitance of the second capacitor C2N and C2P is 16C; the capacitance of the third capacitor C3N and C3P is 8C; the capacitance of the fourth capacitor C4N and C4P is 4C, the capacitance of the fifth capacitor C5N and C5P is 2C, the capacitance of the sixth capacitor C6N and C6P is 1C; the capacitance of capacitor CRN and capacitor CRP is 8C.

[0050] In addition, the high-position capacitor array module includes:

[0051] For the N-terminal circuit, the voltage input terminal V IN Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN , respectively connecting the lower plate of the first capacitor C1N, the lower plate of the second capacitor C2N, the lower plate of the third capacitor C3N, the lower plate of the fourth capacitor C4N and the lower plate of the fifth capacitor C5N through switches SWN1, SWN2, SWN3, SWN4 and SWN5 of the N-terminal circuit;

[0052] For the P-terminal circuit, the voltage input terminal V IP Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN , respectively connected through switches SWP1, SWP2, SWP3, SWP4 and SWP5 of the P-end circuit, the lower plate of the first capacitor C1P, the lower plate of the second capacitor C2P, the lower plate of the third capacitor C3P, the fourth capacitor C4P and the lower plate of the fifth capacitor C5P.

[0053] In addition, the input voltage module also includes: a comparator common mode voltage input terminal V CM_COMP , connecting the positive input terminal VN and the negative input terminal VP of the comparator through switch SWN_CM0 and switch SWN_CM1 respectively.

[0054] In addition, the reference voltage positive terminal V REFP Or the negative terminal of the reference voltage V REFN , the lower plate of capacitor CRN is connected through switch SWNR, and the lower plate of capacitor CRP is connected through switch SWPR.

[0055] In addition, the capacitor CRN and the capacitor CRP are used to raise the voltage of the upper plate to prevent leakage.

[0056] In addition, it also includes: capacitor C DUMMYNand capacitor C DUMMYP ;

[0057] The capacitor C DUMMYN The upper plate of the capacitor C is connected to the positive input terminal VN of the comparator through the switch SWN; DUMMYP The upper plate of the transistor is connected to the negative input terminal VP of the comparator through the switch SWP.

[0058] The capacitor C DUMMYN and capacitor C DUMMYP The lower plates are all grounded;

[0059] Among them, the capacitor C DUMMYN and C DUMMYP Used for capacitor matching, the capacitor size is 16C.

[0060] In addition, it also includes: low-position capacitor array CDACL, through the bridge capacitor C BRN and bridge capacitor C BRP Connect the positive input terminal VN and the negative input terminal VP of the comparator respectively.

[0061] In addition, it also includes: a capacitor array control logic module SAR ADC Logic, which is used to control the switching of switches according to the output result of the comparator to achieve a successive approximation quantization mode.

[0062] The specific operation process of the circuit includes: sampling stage, sampling end stage, SAR ADC preparation stage, SAR ADC working stage and first two position stage, including the following steps:

[0063] S101: Sampling phase, including: switches SWN_CM0, SWN_CM1, SWP_CM0, SWP_CM1 are closed, voltage input terminals VN1, VN, VP1, VP are connected to common mode voltage input terminal V CM_COMP The above connection method can make the common mode voltage of the subsequent comparator input terminal all at V CM_COMP The lower plates of the capacitors C1N, C2N, C3N, C4N, C5N, C6N, and C6N_R of the high-position capacitor array module and the voltage input terminal V of the N-terminal circuit are connected. IN The lower plates of capacitors C1P, C2P, C3P, C4P, C5P, C6P, and C6P_R are connected to the voltage input section V of the P-terminal circuit. IP connected, capacitors CRN and CRP are connected to V REFN (0V) are connected, and switches SWN and SWP are in the open state.

[0064] S102: Sampling end stage: After sampling is completed, switches SWN_CM1 and SWP_CM1 are disconnected, and switches SWP1, SWP2, SWP3, SWP4, SWP5, SWP6, SWPR6, SWN1, SWN2, SWN3, SWN4, SWN5, SWN6, and SWNR6 are also disconnected. The upper plate voltages VN1 and VP1 of the high-order capacitor array module are in a suspended state, and the capacitors CRN and CRP are still connected to V REFN (0V), the switches SWN and SWP remain in the off state.

[0065] S103: Two-bit quantizer preparation stage, including: other switches remain connected, switches SWP6, SWPR6, SWN6, SWNR6 are switched to the common mode voltage V CM , so that the lower plates of the high-position capacitors C6N, C6P, redundant capacitors C6N_R, C6P_R and the common-mode voltage input terminal V CM After the above four capacitors are reset, the capacitors C6N, C6N_R, C6P, and C6P_R form a two-bit sub-quantizer structure to generate the values ​​of the MSB bit and the MSB-1 bit.

[0066] S104: Two-bit quantizer working stage, including: After the capacitors C6N, C6N_R, C6P, and C6P_R are reset, the comparator starts to compare and generate the result of the MSB bit. According to the result of the first comparison, the capacitors C6N, C6P and the reference voltage V REFP or V REFN connected, the redundant capacitors C6N_R and C6P_R are still connected to the common mode voltage V CM connect.

[0067] S105: First two position phase, including:

[0068] After the two sub-quantizers perform two comparisons, the latch stores the results of the two comparisons, which are recorded as result1 and result2 respectively.

[0069] After saving the value of result2, the connection mode of other switches remains unchanged, and the lower plates of the high-order capacitors CRN and CRP are switched to the reference voltage V REFP (5V) is connected to each other, so that the voltage values ​​of VN1 and VP1 increase to avoid subsequent leakage.

[0070] After the upper plate voltages VN1 and VP1 of the high-order capacitor array module are established, the lower plates of the high-order capacitors C2N and C2P are determined according to the value of result2 to determine the voltage between them and the reference voltage V REFP or V REFNBecause the voltages of the upper plate voltages VN1 and VP1 of the high-order capacitor array module are raised before the second capacitor is set, even in the most extreme case, the values ​​of VN1 and VP1 will not be pulled too low to cause leakage. At the same time, the highest reference voltage of 5V can also ensure that the upper plate voltages VN1 and VP1 of the high-order capacitor array module will not leak due to excessively high voltages.

[0071] After the second bit is set, the lower plates of the first capacitors C1N and C1P are determined to be connected to the reference voltage terminal V according to the value of result1. REFP or V REFN The reason for setting the second bit first and then the first bit is that the weight of the second bit capacitor is half of the first bit. After the two-bit quantizer is compared, the capacitors connected to the upper plate voltages VN1 and VP1 of the high-order capacitor array module are only capacitors CRN and CRP. DUMMYN and C DUMMYP The lower plate of the capacitor is connected to a stable voltage, and the lower plates of other capacitors are in a suspended state. Therefore, other capacitors can participate in charge sharing to reduce the total weight of capacitors that cause VN1 and VP1 voltage fluctuations due to setting.

[0072] Therefore, in this embodiment, the second capacitor with a smaller capacitance weight is first set. After the second capacitors C2N and C2P are set, their lower plate voltage is also in a stable state and can participate in the charge sharing during the setting of the first capacitors C1N and C1P, thereby reducing the voltage fluctuation of the upper plate voltages V1N and V1P of the high-position capacitor array module, so that no leakage occurs during the first setting process.

[0073] After the first and second positions are set, the other capacitors in the high position are reset. Connect the lower plates of the high-position capacitors C3N, C4N, C5N, C6N, C3P, C4P, C5P and C6P to the common-mode voltage input terminal V CM , the lower plates of C6N_R and C6P_R are originally connected to V CM During the above operation, SWN and SWP are both disconnected, the upper plate voltage VN1 of the high-position capacitor array module of the N-terminal circuit is disconnected from the positive input terminal VN of the comparator, and the upper plate voltage VP1 of the high-position capacitor array module of the P-terminal circuit is disconnected from the negative input terminal VP of the comparator.

[0074] After the lower plates of the high-position capacitors C1N, C2N, C3N, C4N, C5N, C6N, C1P, C2P, C3P, C4P, C5P and C6P are switched, the lower plates of the capacitors CRN and CRP are switched to the reference voltage V REFN(0V), and at the same time, switches SWN and SWP are turned on, and the upper plate voltage VN1 of the high-position capacitor array module of the N-end circuit is connected to the positive input terminal VN of the comparator, and the upper plate voltage VP1 of the high-position capacitor array module of the P-end circuit is connected to the negative input terminal VP of the comparator. After the above switching steps, the fluctuation range of the positive input terminal VN of the comparator and the negative input terminal VP of the comparator are both within 1.8V, and the common mode voltage of the positive input terminal VN of the comparator and the negative input terminal VP of the comparator is V CM_COMP (0.9V) approximately.

[0075] In summary, this embodiment controls the connection relationship between the two-bit quantizer and the main ADC through the timing design of the switch switching, and makes the four capacitors C6N, C6P, C6N_R and C6P_R as the two-bit quantizer to generate the comparison results of the first two bits and participate in the quantization process of the SAR ADC. By scientifically designing the order of setting and resetting of each capacitor, the leakage of the upper plate voltage VN1 and VP1 caused by excessively high or too low voltage is avoided. In addition, the capacitors CRN and CRP put the voltage values ​​of the upper plate voltage input terminals VN1 and VP1 in a safe voltage range before the first two bits are set, and leakage will not occur due to the process of the first two bits. In short, the SAR ADC structure with an embedded two-bit auxiliary quantizer provided by the present invention controls the voltage range of the comparator input terminals VN and VP within 1.8V, that is, it realizes the quantization processing of the input signal on the low-voltage device under the condition of wide voltage input, so that the SAR ADC meets the requirements of wide voltage input and low working voltage, and optimizes the technical indicators of the SAR ADC such as speed and power consumption. 。

[0076] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A SARADC structure with a built-in two-bit auxiliary quantizer, characterized in that: include: Input voltage module, high-position capacitor array module, switch array module and comparator module; The input voltage module includes: a voltage input terminal V IN , voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFP and the negative terminal of the reference voltage V REFN ; The high-position capacitor array module includes: the sixth-position capacitor C6N and the redundant capacitor C6P_R of the N-end circuit, and the sixth-position capacitor C6P and the capacitor C6P_R of the P-end circuit; The switch array module includes: switches SWNR6 and SWN6 of the N-end circuit, and switches SWPR6 and SWP6 of the P-end circuit; The comparator module comprises: a comparator positive input terminal VN and a comparator negative input terminal VP; Voltage input terminal V IN , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6N_R is switched through the switch SWNR6, and the lower plate of the sixth capacitor C6N is switched through the switch SWN6; the upper plate of the redundant capacitor C6N_R and the upper plate of the sixth capacitor C6N are connected to the positive input terminal VN of the comparator; Voltage input terminal V IP , common mode voltage input terminal V CM , reference voltage positive terminal V REFN , negative reference voltage terminal V REFP , the lower plate of the redundant capacitor C6P_R is switched through the switch SWPR6, and the lower plate of the sixth capacitor C6P is switched through the switch SWP6; the upper plate of the redundant capacitor C6P_R and the upper plate of the sixth capacitor C6P are connected to the negative input terminal VP of the comparator.

2. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 1, characterized in that: The switch array module further includes switches SWN1, SWN2, SWN3, SWN4, SWN5, SWNR of the N-end circuit and switches SWP1, SWP2, SWP3, SWP4, SWP5, SWPR of the P-end circuit.

3. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 1, characterized in that: The high-position capacitor array module also includes: a first capacitor C1N, a second capacitor C2N, a third capacitor C3N, a fourth capacitor C4N, a fifth capacitor C5N and a capacitor CRN of the N-end circuit; a first capacitor C1P, a second capacitor C2P, a third capacitor C3P, a fourth capacitor C4P, a fifth capacitor C5P and a capacitor CRP of the P-end circuit; The first capacitor C1N, the second capacitor C2N, the third capacitor C3N, the fourth capacitor C4N, the fifth capacitor C5N and the upper plate of the capacitor CRN of the N-terminal circuit are all connected to the positive input terminal VN of the comparator through the switch SWN; The upper plates of the first capacitor C1P, the second capacitor C2P, the third capacitor C3P, the fourth capacitor C4P, the fifth capacitor C5P and the capacitor CRP of the P-end circuit are all connected to the negative input terminal VP of the comparator through the switch SWP; Among them, the capacitance of the first capacitor C1N and C1P is 32C; the capacitance of the second capacitor C2N and C2P is 16C; the capacitance of the third capacitor C3N and C3P is 8C; the capacitance of the fourth capacitor C4N and C4P is 4C, the capacitance of the fifth capacitor C5N and C5P is 2C, the capacitance of the sixth capacitor C6N and C6P is 1C; the capacitance of capacitor CRN and capacitor CRP is 8C.

4. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 3, characterized in that: The high-position capacitor array module comprises: For the N-terminal circuit, the voltage input terminal V IN Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN , respectively connecting the lower plate of the first capacitor C1N, the lower plate of the second capacitor C2N, the lower plate of the third capacitor C3N, the lower plate of the fourth capacitor C4N and the lower plate of the fifth capacitor C5N through switches SWN1, SWN2, SWN3, SWN4 and SWN5 of the N-terminal circuit; For the P-terminal circuit, the voltage input terminal V IP Or common mode voltage input terminal V CM Or the positive reference voltage V REFP Or the negative terminal of the reference voltage V REFN , respectively connected through switches SWP1, SWP2, SWP3, SWP4 and SWP5 of the P-end circuit, the lower plate of the first capacitor C1P, the lower plate of the second capacitor C2P, the lower plate of the third capacitor C3P, the fourth capacitor C4P and the lower plate of the fifth capacitor C5P.

5. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 3, characterized in that: The input voltage module also includes: a comparator common mode voltage input terminal V CM _ COMP The positive input terminal VN and the negative input terminal VP of the comparator are connected through the switch SWN_CM0 and the switch SWN_CM1 respectively.

6. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 3, characterized in that: The reference voltage positive terminal V REFP Or the negative terminal of the reference voltage V REFN , the lower plate of capacitor CRN is connected through switch SWNR, and the lower plate of capacitor CRP is connected through switch SWPR.

7. A SARADC structure with a two-bit auxiliary quantizer embedded in claim 3, characterized in that: The capacitor CRN and the capacitor CRP are used to raise the voltage of the upper plate to prevent leakage.

8. The SARADC structure with a two-bit auxiliary quantizer embedded in claim 1, characterized in that: Also includes: Capacitor C DUMMYN and capacitor C DUMMYP ; The capacitor C DUMMYN The upper plate of the capacitor C is connected to the positive input terminal VN of the comparator through the switch SWN; DUMMYP The upper plate is connected to the negative input terminal VP of the comparator through the switch SWP; The capacitor C DUMMYN and capacitor C DUMMYP The lower plates are all grounded; Among them, the capacitor C DUMMYN and C DUMMYP Used for capacitor matching, the capacitor size is 16C.

9. The SARADC structure with a two-bit auxiliary quantizer embedded in claim 1, characterized in that: Also includes: The low-order capacitor array CDACL is connected through the bridge capacitor C BRN and bridge capacitor C BRP Connect the positive input terminal VN and the negative input terminal VP of the comparator respectively.

10. The SARADC structure with a two-bit auxiliary quantizer embedded in claim 1, characterized in that: Also includes: The capacitor array control logic module SARADC Logic is used to control the switching of switches according to the output result of the comparator to realize the successive approximation quantization mode.

Images