Diamond MIS-HEMT device and manufacturing method thereof
By forming a silicon-containing material layer and MIS structure on a single crystal diamond substrate, the problem of degradation of voltage resistance and increased risk of breakdown in high-voltage occasions is solved, and a diamond MIS-HEMT device with low leakage current and high reliability is achieved.
Patent Information
- Application Number
- CN202311180792.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-13
- Publication Date
- 2025-03-14
AI Technical Summary
After diamond devices are used in high-voltage occasions, their voltage resistance is challenged and the risk of breakdown is increased.
By forming a silicon-containing material layer laminated on a single crystal diamond substrate, and forming a silicon terminal conductive layer, a semiconductor layer, an insulating layer and a gate conductive layer thereon, a metal-insulator-semiconductor (MIS) structure is formed to avoid Schottky contact and increase the surface barrier height.
It effectively reduces the gate leakage current of the device, avoids breakdown near the gate conductive layer, improves the reliability and performance of the device, and is suitable for high-voltage power switches and microwave power devices.
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Figure CN119630011A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a diamond MIS-HEMT device and a method for manufacturing the same. Background Art
[0002] The bandgap width of diamond reaches 5.5eV, which means that diamond has a larger breakdown electric field, which ensures the application of diamond devices in high-voltage situations; at the same time, diamond has the widest operating temperature range, which means that diamond devices can perform normally in extreme high-temperature environments, and also ensures the application of diamond devices in high-temperature situations.
[0003] However, when diamond devices are used in high-voltage situations, their pressure-resistant performance is challenged and the risk of breakdown increases. Summary of the invention
[0004] Based on this, it is necessary to provide a diamond MIS-HEMT device and a manufacturing method thereof to address the breakdown risk of diamond devices.
[0005] The disclosed embodiments provide a method for manufacturing a diamond MIS-HEMT device, the method comprising: forming a silicon-containing material layer stacked on a single crystal diamond substrate, and obtaining a silicon terminal conductive layer stacked between the silicon-containing material layer and the single crystal diamond substrate; forming a semiconductor layer stacked on the silicon-containing material layer; forming an insulating layer stacked on the semiconductor layer; and forming a gate conductive layer stacked on the insulating layer, wherein a projected area of the gate conductive layer along a stacking direction is smaller than a projected area of the semiconductor layer.
[0006] The method provided in the embodiment of the present disclosure forms a semiconductor layer and an insulating layer between the silicon-containing material layer and the gate conductive layer, avoiding the gate conductive layer and the silicon-containing material layer from forming a Schottky contact, but realizing a metal-insulator-semiconductor (MIS) structure composed of a gate conductive layer, an insulating layer and a semiconductor layer. The insulating layer can effectively increase the surface barrier height of the device, thereby reducing the gate leakage current of the device, and effectively avoiding breakdown near the gate conductive layer. The manufactured diamond MIS-HEMT (metal-insulator-semiconductor-high electron mobility transistor) device is reliable in use, has low off-state leakage, and has a large gate voltage swing, and is an ideal choice for high-voltage power switches and microwave power devices.
[0007] In addition, when preparing the silicon-terminated conductive layer, a two-dimensional hole gas (2DHG) can be easily formed on the surface of the single-crystal diamond substrate and used as the channel structure of the device. The channel structure exhibits high resistance characteristics, can increase the barrier height, reduce leakage, and is conducive to the realization of enhanced devices. The silicon-terminated conductive layer optimizes the interface quality between the silicon-containing dielectric layer and the single-crystal diamond substrate, and can improve the key performance indicators of the enhanced diamond MIS-HEMT device.
[0008] The thermal conductivity of single crystal diamond ranges from 1800W / (mk) to 2200W / (mk). The single crystal diamond substrate can enhance heat dissipation and reduce the junction temperature of the diamond MIS-HEMT device. Compared with common RF devices, diamond MIS-HEMT devices can avoid self-heating effects and ensure their own frequency performance and breakdown resistance.
[0009] In some embodiments, the method further includes the step of forming a single crystal diamond substrate, including: forming a 0.2 mm to 2 mm thick single crystal diamond substrate stacked on a diamond seed crystal by a microwave plasma chemical vapor deposition process; peeling the diamond seed crystal from the single crystal diamond substrate; and treating the single crystal diamond substrate by a cleaning process.
[0010] Such an arrangement can form a single crystal diamond substrate with complete morphology and ensure the realization of subsequent functional layers on the single crystal diamond substrate.
[0011] Exemplarily, the power of the microwave plasma chemical vapor deposition process is 1500W to 5000W, the chamber pressure is 30Torr to 300Torr, the proportion of methane in the gas atmosphere is 3% to 12%, and the temperature is 900°C to 1300°C.
[0012] In this way, a single crystal diamond substrate with a stable structure can be formed.
[0013] In some embodiments, the step of forming the silicon-containing material layer includes: forming a silicon-containing material layer with a thickness of 100 nm to 300 nm by a first plasma enhanced chemical vapor deposition process, wherein the silicon source includes tetraethoxysilane.
[0014] With such configuration, the material of the silicon-containing material layer may include silicon dioxide, and a C-Si-O / SiO2 structure may be formed at the silicon terminal conductive layer. The silicon terminal conductive layer is conducive to the realization of an enhanced device.
[0015] In some embodiments, the step of forming a semiconductor layer includes: forming a semiconductor layer of silicon carbide material with a thickness of 1 μm to 10 μm by a metal organic compound chemical vapor deposition process.
[0016] In this way, a semiconductor layer of silicon carbide material can be formed, which helps to ensure the performance of the HEMT device.
[0017] Exemplarily, the pressure of the metal organic chemical vapor deposition process is 120 mbar to 500 mbar, and the carbon-silicon ratio of the gas atmosphere is 1 to 2.
[0018] By such arrangement, a semiconductor layer with good electrical properties can be formed.
[0019] In some embodiments, the step of forming an insulating layer includes: forming an insulating layer with a thickness of 5nm to 10nm by an atomic layer deposition process, and the material of the insulating layer includes at least one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, molybdenum oxide and hafnium oxide.
[0020] By configuring in this way, an insulating layer can be realized, and the insulating layer and the semiconductor layer can be well combined.
[0021] Illustratively, the temperature of the atomic layer deposition process is 150° C. to 350° C., and the pressure is 0.1 Torr to 0.3 Torr.
[0022] With this arrangement, a stable insulating layer can be formed.
[0023] In some embodiments, the material of the insulating layer is aluminum oxide. In this way, the insulating layer can have a higher dielectric constant and a good passivation effect.
[0024] In some embodiments, the step of forming the gate conductive layer includes: forming a gate conductive layer with a thickness of 80 nm to 100 nm and a T-type gate by a photolithography process, wherein the material of the gate conductive layer includes aluminum.
[0025] Such an arrangement can realize a gate conductive layer and ensure reliable use of the gate relative to the source electrode and the drain electrode.
[0026] In some embodiments, a single crystal diamond substrate is formed by a microwave plasma chemical vapor deposition process with a power of 4800 W, a chamber pressure of 165 Torr, a ratio of methane to the gas atmosphere of 8%, and a temperature of 1050° C.
[0027] By such arrangement, a single crystal diamond substrate with good quality and stable performance can be formed, and the surface of the single crystal diamond substrate is flat.
[0028] Exemplarily, the semiconductor layer is formed by a metal organic compound chemical vapor deposition process at a pressure of 350 mbar and a carbon-silicon ratio of a gas atmosphere of 1.2.
[0029] With such an arrangement, a good semiconductor layer can be formed.
[0030] Exemplarily, the insulating layer is formed by an atomic layer deposition process at a temperature of 250° C. and a pressure of 0.2 torr.
[0031] By configuring in this way, an insulating layer combined with the semiconductor layer can be formed.
[0032] In some embodiments, the method for manufacturing a diamond MIS-HEMT device further includes: forming a first electrode and forming a second electrode, the first electrode and the second electrode are respectively in ohmic contact with the single crystal diamond substrate, the first electrode and the second electrode are spaced apart, and the distance between the gate conductive layer and the first electrode and the distance between the gate conductive layer and the second electrode are respectively in the range of 0.5 μm to 3 μm; wherein the silicon terminal conductive layer, the silicon-containing material layer, the semiconductor layer, the insulating layer and the gate conductive layer are located between the first electrode and the second electrode, and the first electrode and the second electrode are respectively spaced apart from the gate conductive layer.
[0033] This setting can ensure performance and reliability.
[0034] In some embodiments, the method for manufacturing a diamond MIS-HEMT device further includes forming a passivation layer, the passivation layer being juxtaposed with the insulating layer and covering the semiconductor layer.
[0035] This setting can passivate the surface state and suppress current collapse.
[0036] In some embodiments, the step of forming a first electrode and the step of forming a second electrode respectively include: forming sequentially stacked metal layers by an electron beam evaporation process, the sequentially stacked metal layers including: a 20nm to 2μm thick titanium layer, a 70nm to 3μm thick aluminum layer, a 30nm to 2μm thick nickel layer and a 90nm to 3μm thick gold layer; and annealing at a temperature of 700°C to 850°C for 30s to 50s in a nitrogen atmosphere.
[0037] Such an arrangement can form a first electrode and a second electrode with good electrical performance and reliable structure, which is helpful to improve the function of the HEMT device.
[0038] In some embodiments, the step of forming the passivation layer includes: forming a passivation layer of silicon nitride material with a thickness of 100nm to 300nm by a second plasma enhanced chemical vapor deposition process, wherein the temperature of the second plasma enhanced chemical vapor deposition process is 250°C to 350°C, the power is 350W to 500W, the gas pressure is 100mTorr to 500mTorr, the gas flow rate is 20sccm to 75sccm, and the ratio of monosilane to ammonia is 0.6 to 0.8. Specifically, in the raw material gas forming the gas atmosphere, the ratio of the flow rate of monosilane to the flow rate of ammonia is 0.6 to 0.8
[0039] With such an arrangement, a passivation layer of silicon nitride material can be formed, which helps to passivate the semiconductor layer and also ensures that the electrical properties at the insulating layer, the first electrode and the second electrode are achieved.
[0040] Exemplarily, the sequentially stacked metal layers are subjected to an annealing process at 780° C. for 35 seconds.
[0041] With such arrangement, the annealing effect is good and the ohmic contact effect is good.
[0042] Exemplarily, the passivation layer is formed by a second plasma enhanced chemical vapor deposition process with a temperature of 300° C., a power of 400 W, a radio frequency of 13.56 MHz, a gas pressure of 400 mTorr, a gas flow of 65 sccm, and a ratio of monosilane to ammonia of 0.7.
[0043] With such an arrangement, a passivation layer with stable performance can be formed.
[0044] The disclosed embodiments also provide a diamond MIS-HEMT device, which includes: a single crystal diamond substrate, a silicon terminal conductive layer, a silicon-containing material layer, a semiconductor layer, an insulating layer and a gate conductive layer stacked in sequence, wherein a projected area of the gate conductive layer along the stacking direction is smaller than a projected area of the semiconductor layer.
[0045] The diamond MIS-HEMT device provided in the embodiments of the present disclosure is a novel diamond-based heterogeneous integrated device and a novel diamond power electronic device. The diamond MIS-HEMT device is reliable in use, has low off-state leakage, and has a large gate voltage swing, and is an ideal choice for high-voltage power switches and microwave power devices.
[0046] In some embodiments, the diamond MIS-HEMT device further includes: a first electrode, a second electrode and a passivation layer, the first electrode and the second electrode are respectively spaced apart from the gate conductive layer, the first electrode and the second electrode respectively extend through the semiconductor layer, the silicon-containing material layer and the silicon terminal conductive layer and are in ohmic contact with the single crystal diamond substrate, and the passivation layer is parallel to the insulating layer and covers the semiconductor layer.
[0047] Such an arrangement can ensure the extraction of the first electrode and the second electrode, and can also ensure the realization of the circuit functions of each functional layer. The passivation layer can also be used to enable the channel to be well formed and remain stable.
[0048] In some embodiments, the thickness of the single crystal diamond substrate is 0.2 mm to 2 mm, the thickness of the silicon-containing material layer is 100 nm to 300 nm, the thickness of the semiconductor layer is 1 μm to 10 μm, the thickness of the insulating layer is 5 nm to 10 nm, the type of the gate conductive layer is a T-type gate, the thickness of the gate conductive layer is 80 nm to 100 nm, the distance between the gate conductive layer and the first electrode and the distance between the gate conductive layer and the second electrode are respectively in the range of 0.5 μm to 3 μm, the length of the gate conductive layer along the relative direction of the first electrode and the second electrode is 0.1 μm to 0.5 μm, and the width of the gate conductive layer is 50 μm to 100 μm.
[0049] With such an arrangement, the single crystal diamond substrate can be used to achieve excellent heat dissipation, avoid self-heating effects, ensure that the functions of each functional layer are well realized, and ensure that the functions of the first electrode and the second electrode are well realized. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] Figure 1 A schematic flowchart of a method for manufacturing a diamond MIS-HEMT device according to an embodiment of the present disclosure;
[0051] Figure 2 A schematic diagram of the process for forming a single crystal diamond substrate;
[0052] Figure 3 A schematic structural diagram of a prefabricated structure after forming a single crystal diamond substrate;
[0053] Figure 4 Schematic diagram of the structure of a single crystal diamond substrate;
[0054] Figure 5 is a schematic structural diagram of a prefabricated structure after forming an electrode;
[0055] Figure 6 A schematic structural diagram of a prefabricated structure after forming a silicon-containing material layer;
[0056] Figure 7 is a schematic structural diagram of a prefabricated structure after forming a semiconductor layer;
[0057] Figure 8 A schematic structural diagram of a prefabricated structure after forming an insulating layer;
[0058] Fig. 9 is a schematic structural diagram of a prefabricated structure after a gate conductive layer is formed;
[0059] Fig.10 A schematic diagram of the structure of a diamond MIS-HEMT device provided in an embodiment of the present disclosure;
[0060] Fig.11 A structural block diagram of an electronic device provided in an embodiment of the present disclosure.
[0061] Description of the accompanying drawings: 1. diamond seed crystal; 2. plasma; 3. single crystal diamond substrate; 4. first electrode; 41. first metal layer; 42. second metal layer; 43. third metal layer; 44. fourth metal layer; 5. second electrode; 6. silicon-containing material layer; 7. silicon terminal conductive layer; 8. semiconductor layer; 9. insulating layer; 10. gate conductive layer; 11. passivation layer;
[0062] 100. Diamond MIS-HEMT device; 200. Peripheral circuit; 300. Electronic device. DETAILED DESCRIPTION
[0063] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the specific implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the embodiments of the present disclosure. However, the embodiments of the present disclosure can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the embodiments of the present disclosure, so the embodiments of the present disclosure are not limited by the specific examples of the embodiments disclosed below.
[0064] In the description of the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present disclosure.
[0065] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.
[0066] In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. Exemplarily, the first electrode may also be referred to as the second electrode, and the second electrode may also be referred to as the first electrode. In the description of the embodiments of the present disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0067] In the embodiments of the present disclosure, unless otherwise clearly specified and limited, the terms "connected", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a flexible connection, or a rigid connection along at least one direction; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or directly connected with the presence of an intermediate medium, or it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly limited. The terms "installed", "set", "fixed", etc. can be broadly understood as connection. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.
[0068] As used herein, the terms "layer" and "region" refer to a portion of a material that includes an area with a certain thickness. A layer can extend horizontally, vertically and / or along a tapered surface. A layer can be an area of a uniform or non-uniform continuous structure, and its thickness perpendicular to the extension direction may not be greater than the thickness of the continuous structure. A layer can include multiple layers, which can be stacked layers or multiple layers extending discretely. The shapes of various regions and layers in the drawings and their relative sizes and positional relationships are only exemplary, and may actually deviate due to manufacturing tolerances or technical limitations, and the design can be adjusted according to actual needs.
[0069] See also Figure 1 , Figure 1 The flow of the method for manufacturing a diamond MIS-HEMT device in an embodiment of the present disclosure is shown. In some embodiments, the method 1000 for manufacturing a diamond MIS-HEMT device may include the following steps S103 to S106.
[0070] Exemplarily, the method 1000 for manufacturing a diamond MIS-HEMT device further includes step S101 of forming a single crystal diamond substrate.
[0071] In some embodiments, step S102 may be performed first to form a first electrode and a second electrode; and then steps S103 to S106 may be performed to form functional layers stacked on a single crystal diamond substrate. The first electrode and the second electrode are located on the same side of the single crystal diamond substrate and are spaced apart, and the first electrode and the second electrode are in ohmic contact with the single crystal diamond substrate, respectively. In other embodiments, multiple functional layers may be formed first, and then the first electrode and the second electrode may be formed.
[0072] Step S103 includes: forming a silicon-containing material layer and obtaining a silicon terminal conductive layer. Specifically, forming a silicon-containing material layer stacked on a single crystal diamond substrate and obtaining a silicon terminal conductive layer stacked between the silicon-containing material layer and the single crystal diamond substrate. The silicon-containing material layer is connected between the first electrode and the second electrode.
[0073] Step S104 includes: forming a semiconductor layer. The semiconductor layer is stacked on the side of the silicon-containing material layer facing away from the single crystal diamond substrate.
[0074] Step S105 includes: forming an insulating layer. The insulating layer is stacked on a side of the semiconductor layer facing away from the silicon-containing material layer.
[0075] Step S106 includes: forming a gate conductive layer. The gate conductive layer, the insulating layer and the semiconductor layer form a MIS structure. The projected area of the gate conductive layer along the stacking direction is smaller than the projected area of the semiconductor layer to ensure that the gate conductive layer is spaced apart from the first electrode and the second electrode.
[0076] Exemplarily, the method 1000 further includes step S107 of forming a passivation layer. The passivation layer is parallel to the insulating layer and covers the semiconductor layer.
[0077] The method for manufacturing a diamond MIS-HEMT device provided by the embodiment of the present disclosure realizes a MIS structure at the gate conductive layer by forming a semiconductor layer and an insulating layer between the silicon-containing material layer and the gate conductive layer, thereby manufacturing a diamond MIS-HEMT device with good voltage resistance performance.
[0078] Combination Figures 2 to 10 , detailing the method for manufacturing a diamond MIS-HEMT device provided by an embodiment of the present disclosure.
[0079] refer to Figure 2 and Figure 3 , the method 1000 for manufacturing a diamond MIS-HEMT device in the embodiment of the present disclosure may include the step of forming a single crystal diamond substrate 3. In some embodiments, a microwave plasma chemical vapor deposition process may be used, during which a plasma 2 is formed; after the plasma 2 contacts the diamond seed crystal 1, a single crystal diamond substrate 3 stacked on the diamond seed crystal 1 may be formed. The power of the microwave plasma chemical vapor deposition process is 1500W to 5000W, such as 2000W, 3000W or 4000W; the chamber pressure is 30Torr to 300Torr, such as 50Torr, 100Torr, 150Torr or 200Torr; the proportion of methane in the gas atmosphere is 3% to 12%, such as 5% or 10%; the temperature is 900°C to 1300°C, such as 1000°C, 1100°C or 1200°C. The thickness of the single crystal diamond substrate 3 may be 0.2mm to 2mm.
[0080] For example, the microwave plasma chemical vapor deposition process is configured with a power of 4800W, a chamber pressure of 165 Torr, a methane ratio of 8% in the gas atmosphere, and a temperature of 1050° C. to form a 1.8 mm thick single crystal diamond substrate 3. In this way, a single crystal diamond substrate with a complete structure and good performance can be formed.
[0081] Step S010 also includes: peeling off the diamond seed crystal 1 from the single crystal diamond substrate 3; and treating the single crystal diamond substrate 3 through a cleaning process to obtain a Figure 4 The single crystal diamond substrate 3 is shown. The cleaning process may include an acid cleaning step and an organic cleaning step.
[0082] Exemplarily, a single crystal diamond substrate may also be obtained by other processes. In the method provided in the embodiment of the present disclosure, the structure obtained in each step may be referred to as a prefabricated structure for the next step.
[0083] Single crystal diamond has excellent properties such as large bandgap, extremely high hardness and thermal conductivity, high electron saturation drift velocity, high temperature resistance, corrosion resistance, and radiation resistance. Its performance completely surpasses existing semiconductor materials and can overcome the difficulties of insufficient breakdown field strength and self-heating effect of SiC and GaN. In terms of electronic devices that require ultra-high voltage, ultra-high current, ultra-high power, high efficiency, radiation resistance, and ultra-high frequency operation without cooling, the disclosed embodiments have extremely important application prospects by using single crystal diamond substrates.
[0084] refer to Figure 5 , forming the first electrode 4, and forming the second electrode 5. The first electrode 4 and the second electrode 5 may be formed simultaneously or in steps. For example, an electron beam evaporation process may be used to form sequentially stacked metal layers, such as a first metal layer 41, a second metal layer 42, a third metal layer 43, and a fourth metal layer 44 sequentially stacked on the single crystal diamond substrate 3 along the Z-axis direction. The metal layer structures of the first electrode 4 and the second electrode 5 may be the same. The first electrode 4 and the second electrode 5 are spaced apart along the X-axis direction.
[0085] The first metal layer 41 may be a titanium layer with a thickness of 20nm to 2μm, such as a titanium layer with a thickness of 20nm to 70nm, or a titanium layer with a thickness of 1μm to 1.5μm; the second metal layer 42 may be an aluminum layer with a thickness of 70nm to 3μm, such as an aluminum layer with a thickness of 70nm to 100nm, or an aluminum layer with a thickness of 1μm to 2μm; the third metal layer 43 may be a nickel layer with a thickness of 30nm to 2μm, such as a nickel layer with a thickness of 30nm to 70nm, or a nickel layer with a thickness of 1μm to 1.5μm; the fourth metal layer 44 may be a gold layer with a thickness of 90nm to 3μm, such as a gold layer with a thickness of 90nm to 100nm, or a gold layer with a thickness of 1μm to 2μm. It can be understood that the thickness direction of the single crystal diamond substrate 3 is along the Z-axis direction, and the thickness of each metal layer also refers to its size along the Z-axis direction. By setting a titanium-aluminum-nickel-gold alloy structure, the structural strength of the first electrode 4 and the second electrode 5 can be ensured, and the overall low resistance performance can be ensured.
[0086] Exemplarily, the first electrode 4 and the second electrode 5 include a 30 nm thick titanium layer, a 72 nm thick aluminum layer, a 35 nm thick nickel layer, and a 96 nm thick gold layer, respectively. In some embodiments, the first electrode 4 and the second electrode 5 include leads electrically connected to their metal layer structures, respectively. The leads may be drawn from the passivation layer, and the material of the leads may include gold.
[0087] The step of forming the first electrode 4 and the step of forming the second electrode 5 also include: annealing at a temperature of 700° C. to 850° C. for 30 seconds to 50 seconds in a nitrogen atmosphere. Exemplarily, the temperature of the annealing process is 780° C. for 35 seconds. This is conducive to the first electrode 4 and the second electrode 5 to achieve ohmic contact with the single crystal diamond substrate 3 with low contact resistance.
[0088] refer to Figure 6 , a silicon-containing material layer 6 can be formed between the first electrode 4 and the second electrode 5. The step of forming the silicon-containing material layer 6 includes: forming a 100nm to 300nm thick silicon-containing material layer 6 by a first plasma enhanced chemical vapor deposition process. The silicon source of the process includes tetraethoxysilane, and the material of the silicon-containing material layer 6 includes TEOS-SiO2.
[0089] In the process of forming the silicon-containing material layer 6, a silicon terminal conductive layer 7 is obtained at the interface between the silicon-containing material layer 6 and the single crystal diamond substrate 3. Exemplarily, the thickness of the silicon-containing material layer 6 is 180 nm. The silicon terminal conductive layer 7 exhibits high resistance characteristics, can increase the barrier height, reduce leakage, and is conducive to the realization of enhancement mode devices.
[0090] refer to Figure 7, a semiconductor layer 8 stacked on the silicon-containing material layer 6 is formed. Specifically, the semiconductor layer 8 can be epitaxially formed by a metal organic compound chemical vapor deposition process. The material of the semiconductor layer 8 is silicon carbide material with a thickness of 1μm to 10μm. The pressure of the metal organic compound chemical vapor deposition process is 120mbar to 500mbar, for example, 200mbar, 300mbar or 400mbar; in the gas atmosphere of the process, the carbon-silicon ratio is 1 to 2. Exemplarily, under the conditions of a pressure of 350mbar and a gas atmosphere with a carbon-silicon ratio of 1.2, a semiconductor layer 8 of silicon carbide material with a thickness of 4μm is formed.
[0091] Relative to the single crystal diamond substrate 3, the top of the first electrode 4 and the top of the second electrode 5 may protrude from the top of the semiconductor layer 8. The first electrode 4 and the second electrode 5 extend through the semiconductor layer 8, the silicon-containing material layer 6 and the silicon terminal conductive layer 7 respectively.
[0092] refer to Figure 8 , an insulating layer 9 may be formed by an atomic layer deposition process. The projected area of the insulating layer 9 along the Z-axis direction may be smaller than the projected area of the semiconductor layer 8. The insulating layer 9 is located between the first electrode 4 and the second electrode 5 along the X-axis direction, and the insulating layer 9 may be spaced apart from the first electrode 4 and the second electrode 5. The thickness of the insulating layer 9 is 5 nm to 10 nm. The top of the insulating layer 9 may protrude from the top of the first electrode 4 and the top of the second electrode 5.
[0093] The material of the insulating layer 9 includes at least one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, molybdenum oxide and hafnium oxide. The material of the insulating layer 9 can be selected from aluminum nitride, silicon nitride and boron nitride. The material of the insulating layer 9 can be selected from aluminum oxide, molybdenum oxide and hafnium oxide. Exemplarily, the dielectric constant of aluminum oxide is 9, and the passivation effect is good. The material of the insulating layer 9 is preferably Al2O3.
[0094] The temperature of the atomic layer deposition process is 150° C. to 350° C., such as 180° C., 240° C. or 290° C., and the pressure is 0.1 Torr to 0.3 Torr. Exemplarily, the insulating layer 9 is grown on the semiconductor layer 8 by the atomic layer deposition process at a temperature of 250° C. and a pressure of 0.2 Torr, and the thickness of the insulating layer 9 is 8 nm.
[0095] refer to Fig. 9, a gate conductive layer 10 stacked on the insulating layer 9 can be formed by a photolithography process. The projected area of the gate conductive layer 10 along the Z-axis direction is smaller than the projected area of the semiconductor layer 8. Exemplarily, the projected area of the gate conductive layer 10 along the Z-axis direction is not larger than the projected area of the insulating layer 9. The silicon terminal conductive layer 7, the silicon-containing material layer 6, the semiconductor layer 8, the insulating layer 9 and the gate conductive layer 10 are located between the first electrode 4 and the second electrode 5, and the first electrode 4 and the second electrode 5 are respectively spaced apart from the gate conductive layer 10. The distance between the gate conductive layer 10 and the first electrode 4 and the distance between the gate conductive layer 10 and the second electrode 5 are respectively in the range of 0.5μm to 3μm. The material of the gate conductive layer 10 includes aluminum. The type of the gate conductive layer 10 can be a T-type gate, and its narrow end is connected to the insulating layer 9. The thickness of the gate conductive layer 10 can be 80nm to 100nm.
[0096] Exemplarily, the first electrode 4 can be used as a source electrode, and the second electrode 5 can be used as a drain electrode. The size of the gate conductive layer 10 along the X-axis direction, that is, the length, can be 0.3 μm; the gap between the gate conductive layer 10 and the first electrode 4 is 0.5 μm, and the gap between the gate conductive layer 10 and the second electrode 5 is 3 μm; the thickness of the gate conductive layer 10 is 85 nm; the vertical size of the gate conductive layer 10 along the XZ plane can be 60 μm.
[0097] refer to Fig.10 , the method 1000 provided in the embodiment of the present disclosure can manufacture a diamond MIS-HEMT device 100. Exemplarily, the method 1000 for manufacturing a diamond MIS-HEMT device further includes: forming a passivation layer 11. The passivation layer 11 covers the portion of the semiconductor layer 8 exposed outside the insulating layer 9, and the passivation layer 11 is parallel to the insulating layer 9 and can extend to the side walls of the first electrode 4 and the second electrode 5. The thickness of the passivation layer 11 is smaller than the thickness of the insulating layer 9. The first electrode 4 and the second electrode 5 can protrude from the passivation layer 11, respectively. The thickness of the passivation layer 11 can be 100 nm to 300 nm.
[0098] The material of the passivation layer 11 may include silicon nitride (SiN x). Exemplarily, the material of the insulating layer 9 is also silicon nitride. The passivation layer 11 can be formed by a second plasma enhanced chemical vapor deposition process. The temperature of the second plasma enhanced chemical vapor deposition process is 250°C to 350°C, for example, 280°C or 320°C; the power is 350W to 500W; the gas pressure is 100mTorr to 500mTorr, for example, 200mTorr, 300mTorr or 400mTorr; the gas flow rate is 20sccm to 75sccm, for example, 30sccm, 40sccm, 50sccm or 60sccm; the ratio of monosilane to ammonia is 0.6 to 0.8. Exemplarily, the passivation layer 11 is formed by a second plasma enhanced chemical vapor deposition process with a temperature of 300°C, a power of 400W, a radio frequency of 13.56MHz, a gas pressure of 400mTorr, a gas flow rate of 65sccm, and a ratio of monosilane to ammonia of 0.7. A passivation layer 11 with stable bonding and good performance can be formed.
[0099] The diamond MIS-HEMT device 100 manufactured by the method 1000 provided in the embodiment of the present disclosure can reduce the gate leakage current to 10 -8 A level.
[0100] refer to Fig.10 The diamond MIS-HEMT device 100 provided in the embodiment of the present disclosure includes a single crystal diamond substrate 3, a silicon terminal conductive layer 7, a silicon-containing material layer 6, a semiconductor layer 8, an insulating layer 9 and a gate conductive layer 10. The single crystal diamond substrate 3, the silicon terminal conductive layer 7, the silicon-containing material layer 6, the semiconductor layer 8, the insulating layer 9 and the gate conductive layer 10 are sequentially stacked along the Z-axis direction, and the projected area of the gate conductive layer 10 along the stacking direction is smaller than the projected area of the semiconductor layer 8. The projected area of the insulating layer 9 may not be smaller than the projected area of the gate conductive layer 10.
[0101] The diamond MIS-HEMT device 100 further includes a first electrode 4 and a second electrode 5. Exemplarily, the first electrode 4 and the second electrode 5 may be drawn out from the semiconductor layer 8, and then the first electrode 4 and the second electrode 5 are respectively arranged to be spaced apart from the gate conductive layer 10. The first electrode 4 and the second electrode 5 respectively extend through the semiconductor layer 8, the silicon-containing material layer 6 and the silicon terminal conductive layer 7 and are in ohmic contact with the single crystal diamond substrate 3. The first electrode 4 may be used as a source electrode and the second electrode 5 may be used as a gate electrode.
[0102] The diamond MIS-HEMT device 100 provided in the embodiment of the present disclosure has a MIS structure based on a gate conductive layer 10, an insulating layer 9 and a semiconductor layer 8, and the breakdown risk at the gate conductive layer 10 is greatly reduced. The diamond MIS-HEMT device 100 has low gate leakage current, low off-state leakage, large gate voltage swing, and excellent heat dissipation capability.
[0103] In an exemplary embodiment, the diamond MIS-HEMT device 100 further includes a passivation layer 11. The passivation layer 11 is parallel to the insulating layer 9 and covers the semiconductor layer 8. The passivation layer 11 helps to passivate the surface state, reduce the influence on the channel at both sides of the insulating layer 9, and suppress the current collapse.
[0104] The dimensions of each functional layer in the diamond MIS-HEMT device 100 can refer to the above content. For example, the thickness of the single crystal diamond substrate 3 is 0.2 mm to 2 mm, the thickness of the silicon-containing material layer 6 is 100 nm to 300 nm, the thickness of the semiconductor layer 8 is 1 μm to 10 μm, and the thickness of the insulating layer 9 is 5 nm to 10 nm.
[0105] Exemplarily, the length of the insulating layer 9 along the X-axis direction is the same as the length of the gate conductive layer 10. The type of the gate conductive layer 10 may be a T-type gate. Exemplarily, the first electrode 4 and the second electrode 5 are arranged relative to each other along the X-axis direction, the length of the gate conductive layer 10 along the relative direction of the first electrode 4 and the second electrode 5 is 0.1 μm to 0.5 μm, the distance between the gate conductive layer 10 and the first electrode 4 and the distance between the gate conductive layer 10 and the second electrode 5 are respectively in the range of 0.5 μm to 3 μm, the thickness of the gate conductive layer 10 is 80 nm to 100 nm, and the width of the gate conductive layer is 50 μm to 100 μm. The electrical performance of the diamond MIS-HEMT device 100 can be effectively guaranteed.
[0106] refer to Fig.11 The embodiment of the present disclosure provides an electronic device 300, which includes a diamond MIS-HEMT device 100 and a peripheral circuit 200. The diamond MIS-HEMT device 100 and the peripheral circuit 200 are electrically connected. Specifically, the gate conductive layer, the source and the drain of the diamond MIS-HEMT device 100 can be electrically connected to the peripheral circuit 200 respectively. The electronic device 300 can be a high-voltage power switch or a microwave power switch. The electronic device 300 provided in the embodiment of the present disclosure is suitable for high temperature and high pressure environments and can stably play the role of the circuit.
[0107] The technical features of the embodiments disclosed above can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0108] In the embodiments disclosed above, unless otherwise clearly specified and limited, the execution order of each step is not limited, for example, it can be executed in parallel, or it can be executed successively in different orders. The sub-steps of each step can also be executed alternately. The above-mentioned various forms of processes can be used, and steps can be reordered, added or deleted, as long as the desired results of the technical solution provided in the embodiment of the present disclosure can be achieved, and this document does not limit it here.
[0109] The embodiments disclosed above only express several implementation methods of the invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection of the invention. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the invention, and these all belong to the scope of patent protection required by the invention. Therefore, the scope of patent protection of the invention shall be subject to the attached claims.
Claims
1. A method for manufacturing a diamond MIS-HEMT device, characterized in that include: Forming a silicon-containing material layer stacked on a single crystal diamond substrate, and obtaining a silicon terminal conductive layer stacked between the silicon-containing material layer and the single crystal diamond substrate; forming a semiconductor layer stacked on the silicon-containing material layer; forming an insulating layer stacked on the semiconductor layer; as well as A gate conductive layer is formed and stacked on the insulating layer, wherein a projected area of the gate conductive layer along a stacking direction is smaller than a projected area of the semiconductor layer.
2. The method for manufacturing a diamond MIS-HEMT device according to claim 1, wherein: The method also includes the steps of forming the single crystal diamond substrate, including: forming the single crystal diamond substrate with a thickness of 0.2 mm to 2 mm stacked on the diamond seed crystal by a microwave plasma chemical vapor deposition process; peeling the diamond seed crystal from the single crystal diamond substrate; and treating the single crystal diamond substrate by a cleaning process.
3. The method for manufacturing a diamond MIS-HEMT device according to claim 1, wherein: The step of forming the silicon-containing material layer comprises: forming the silicon-containing material layer with a thickness of 100 nm to 300 nm by a first plasma enhanced chemical vapor deposition process, wherein the silicon source comprises tetraethoxysilane; and / or, The step of forming the semiconductor layer comprises: forming the semiconductor layer of silicon carbide material with a thickness of 1 μm to 10 μm by metal organic chemical vapor deposition process; and / or, The step of forming the insulating layer comprises: forming the insulating layer with a thickness of 5 nm to 10 nm by an atomic layer deposition process, wherein the material of the insulating layer comprises at least one of aluminum nitride, silicon nitride, boron nitride, aluminum oxide, molybdenum oxide and hafnium oxide; and / or, The step of forming the gate conductive layer includes: forming the gate conductive layer with a thickness of 80 nm to 100 nm and a T-type gate by a photolithography process, wherein the material of the gate conductive layer includes aluminum.
4. The method for manufacturing a diamond MIS-HEMT device according to claim 1, wherein: The method further comprises: forming a first electrode and a second electrode, wherein the first electrode and the second electrode are in ohmic contact with the single crystal diamond substrate respectively, the first electrode and the second electrode are spaced apart, and the distance between the gate conductive layer and the first electrode and the distance between the gate conductive layer and the second electrode are respectively in the range of 0.5 μm to 3 μm; The silicon terminal conductive layer, the silicon-containing material layer, the semiconductor layer, the insulating layer and the gate conductive layer are located between the first electrode and the second electrode, and the first electrode and the second electrode are spaced apart from the gate conductive layer respectively.
5. The method for manufacturing a diamond MIS-HEMT device according to claim 4, wherein: The method further includes: forming a passivation layer, wherein the passivation layer is parallel to the insulating layer and covers the semiconductor layer.
6. The method for manufacturing a diamond MIS-HEMT device according to claim 5, wherein: The step of forming the passivation layer includes: forming a passivation layer of silicon nitride material with a thickness of 100nm to 300nm through a second plasma enhanced chemical vapor deposition process, wherein the temperature of the second plasma enhanced chemical vapor deposition process is 250°C to 350°C, the power is 350W to 500W, the gas pressure is 100mTorr to 500mTorr, the gas flow rate is 20sccm to 75sccm, and the ratio of monosilane to ammonia is 0.6 to 0.
8.
7. The method for manufacturing a diamond MIS-HEMT device according to claim 4, wherein: The step of forming the first electrode and the step of forming the second electrode respectively include: forming a stacked metal layer by electron beam evaporation process, the stacked metal layer including: a titanium layer with a thickness of 20nm to 2μm, an aluminum layer with a thickness of 70nm to 3μm, a nickel layer with a thickness of 30nm to 2μm and a gold layer with a thickness of 90nm to 3μm; and annealing at a temperature of 700°C to 850°C for 30s to 50s in a nitrogen atmosphere.
8. A diamond MIS-HEMT device, characterized in that: include: A single crystal diamond substrate, a silicon terminal conductive layer, a silicon-containing material layer, a semiconductor layer, an insulating layer and a gate conductive layer are stacked in sequence, wherein the projected area of the gate conductive layer along the stacking direction is smaller than the projected area of the semiconductor layer.
9. The diamond MIS-HEMT device according to claim 8, wherein: It also includes: a first electrode, a second electrode and a passivation layer, the first electrode and the second electrode are respectively spaced apart from the gate conductive layer, the first electrode and the second electrode respectively extend through the semiconductor layer, the silicon-containing material layer and the silicon terminal conductive layer and are in ohmic contact with the single crystal diamond substrate, and the passivation layer is parallel to the insulating layer and covers the semiconductor layer.
10. The diamond MIS-HEMT device according to claim 9, wherein: The thickness of the single crystal diamond substrate is 0.2 mm to 2 mm, the thickness of the silicon-containing material layer is 100 nm to 300 nm, the thickness of the semiconductor layer is 1 μm to 10 μm, and the thickness of the insulating layer is 5 nm to 10 nm. The type of the gate conductive layer is T-type gate, the thickness of the gate conductive layer is 80nm to 100nm, the distance between the gate conductive layer and the first electrode and the distance between the gate conductive layer and the second electrode are respectively in the range of 0.5μm to 3μm, the length of the gate conductive layer along the relative direction of the first electrode and the second electrode is 0.1μm to 0.5μm, and the width of the gate conductive layer is 50μm to 100μm.