Method of manufacturing super-junction device

Abstract

The application discloses a manufacturing method of a super-junction device, which comprises the following steps: growing a first epitaxial layer; forming a trench gate in an active region, removing the gate conductive material layer outside the gate trench, and making the top surface of the gate conductive material layer in the gate trench flat; forming a well region in the active region and a transition region and annealing; forming a second trench; growing a second epitaxial layer doped with a second conductive type in the second trench, removing the second epitaxial layer outside the second trench, and making the surface of the second epitaxial layer in the second trench flat; completing subsequent front process and setting a heat process according to the requirement of controlling the mutual diffusion of PN impurities of a super-junction structure, wherein the subsequent front process comprises forming a protective ring oxide film covering the inner region of a cutoff region of the transition region and a terminal region; and completing back process. The application can effectively control the mutual diffusion of PN impurities of the super-junction structure, and can improve the reliability of the product.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a manufacturing method of a super junction (SJ) device. BACKGROUND

[0002] Compared with the existing conventional VDMOS, the existing super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special N-pillar and P-pillar in the super junction MOSFET structure, that is, the N-type column and the P-type column compensate each other, so that a high breakdown voltage can be achieved under a relatively high N-type epitaxial layer (NEPI) epitaxial concentration. Therefore, it has a low on-resistance and high breakdown voltage beyond the Si limit.

[0003] There are two main manufacturing processes for the existing super junction MOSFET device. One is to form the P-type region and the N-type region by multiple epitaxial deposition and lithography. The other is to form the P-type column by deep trench and trench filling on a thick N-epitaxial layer, thereby forming the P-type region and the N-type region. In the existing deep trench technology, in order to enable the planarization process of the deep trench P-type column to be well implemented, the P-type column forming process is usually placed before the polysilicon forming process of the gate structure. At the same time, the P-type well process is sometimes placed after the P-type column formation. In this way, the P-type column and the N-type column are formed after the P-type column in the trench, and then the gate oxide process and other high-temperature processes are performed, which causes the mutual diffusion of the P-type column impurities and the N-type column impurities, thereby increasing the source-drain on-resistance (Rdson) of the device and affecting the chip performance. SUMMARY

[0004] The technical problem to be solved by the present application is to provide a manufacturing method of a super junction device, which can independently set the heat processes of the trench gate, the well region and the super junction structure, so as to ensure the quality of the trench gate and the well region, effectively control the mutual diffusion of the PN impurities of the super junction structure, facilitate the realization of a smaller step super junction structure and the reduction of the on-resistance of the super junction device, and can also improve the reliability of the product without increasing the process complexity and cost.

[0005] To solve the above technical problems, the manufacturing method of the super junction device provided by the present application comprises the following steps:

[0006] Growth of a first epitaxial layer doped with a first conductivity type on the surface of a semiconductor substrate; the super junction device comprises an active region, a transition region and a terminal region, the terminal region surrounds the periphery of the active region, and the transition region is located between the active region and the terminal region.

[0007] forming a plurality of trench gates in the first epitaxial layer of the active region, the trench gate comprising a gate oxide layer formed on the inner side surface of a gate trench and a gate conductive material layer filled in the gate trench; each of the trench gates is located in a subsequent corresponding first conductive type column; the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer in the gate trench is flat to ensure the formation process of a subsequent second trench, and the quality of the trench gate is adjusted by adjusting the heat process in the formation process of the trench gate.

[0008] forming a second conductive type doped well region in the active region and the transition region by photolithography and ion implantation, and annealing the well region, each of the trench gates passing through the well region, and the well region being set in position and repairing ion implantation damage by adjusting the heat process of the annealing of the well region;

[0009] forming a plurality of second trenches in the first epitaxial layer by photolithography and etching, the first epitaxial layer between each of the second trenches serving as a first conductive type column; the second trenches are located in the active region, the transition region, and the part of the termination region close to the transition region.

[0010] growing a second conductive type doped second epitaxial layer in the second trench, removing the second epitaxial layer outside the second trench and flattening the surface of the second epitaxial layer in the second trench, the second conductive type column being composed of the second epitaxial layer filled in the second trench, and the super-junction structure being formed by the first conductive type column and the second conductive type column being alternately arranged.

[0011] after the super-junction structure is completed, a subsequent front process is performed, in which the heat process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super-junction structure, so that the on-resistance of the super-junction device meets the requirement.

[0012] the subsequent front process comprises: forming a first oxide film and performing patterned etching on the first oxide film to remove the first oxide film at the active region and the cutoff region at the outermost periphery of the termination region, the remaining first oxide film covering the inner region of the transition region and the cutoff region of the termination region and forming a protection ring oxide film;

[0013] a back process of the super-junction device is completed.

[0014] Further improvement is that the material of the semiconductor substrate comprises silicon, the material of the first epitaxial layer comprises silicon, and the material of the second epitaxial layer comprises silicon.

[0015] Further improvement is that the step of forming the trench gate comprises:

[0016] forming a first dielectric layer on top of the first epitaxial layer.

[0017] lithography defines the formation area of the gate trench.

[0018] sequentially etching the first dielectric layer and the first epitaxial layer in the formation area of the gate trench to form the gate trench.

[0019] forming the gate oxide layer by thermal oxidation process.

[0020] forming the gate conductive material layer.

[0021] performing first chemical mechanical polishing process to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to flatten the top surface of the gate conductive material layer inside the gate trench.

[0022] Further improvement is that the material of the gate conductive material layer includes polysilicon.

[0023] Further improvement is that before or after the first chemical mechanical polishing process, further comprising:

[0024] performing one rapid thermal oxidation or one rapid thermal annealing.

[0025] Further improvement is that the maximum temperature of the annealing of the well region is above 1100℃ for more than 30 minutes.

[0026] Further improvement is that before performing the lithography process of the second trench, further comprising: forming a hard mask layer.

[0027] In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

[0028] Further improvement is that the hard mask layer includes a bottom silicon dioxide layer, an intermediate silicon nitride layer and a top silicon dioxide layer which are stacked in sequence.

[0029] After the etching of the second trench is completed, the top silicon dioxide layer and the intermediate silicon nitride layer outside the second trench are removed, and then the growth of the second epitaxial layer is performed.

[0030] Then, the second chemical mechanical polishing process is performed to planarize the second epitaxial layer to remove the second epitaxial layer outside the second trench and to flatten the surface of the second epitaxial layer in the second trench.

[0031] Further improvement is that the subsequent front side process includes:

[0032] Photolithography and ion implantation are performed to form a source region heavily doped with the first conductivity type, wherein the source region and the corresponding side surface of the gate trench are self-aligned.

[0033] The source region is annealed and activated. The annealing of the source region is performed in a furnace at a temperature below 950° C. or in a rapid thermal annealing process.

[0034] When the source region is formed, a cutoff region heavily doped with the first conductivity type is formed in a surface region of the first epitaxial layer at an outer edge of the terminal region.

[0035] A further improvement is that the subsequent front surface process further includes:

[0036] An interlayer film is formed, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0037] A contact hole opening is formed through the interlayer film.

[0038] A contact region heavily doped with the second conductivity type is formed at the bottom of the contact hole opening.

[0039] A metal layer is filled in the contact hole opening to form a contact hole.

[0040] A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

[0041] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0042] A dielectric protection layer is formed; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0043] The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0044] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0045] A polyimide layer is formed.

[0046] The polyimide layer is patterned by photolithography and development to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0047] The polyimide layer is baked.

[0048] Further improvement is that the metal layer forming the contact hole comprises:

[0049] A barrier layer is formed on the inner surface of the contact hole opening.

[0050] A tungsten layer is formed to fill in the contact hole opening.

[0051] The barrier layer and the tungsten layer also extend onto the ILD surface outside the contact hole opening.

[0052] The front metal layer is formed on the surface of the tungsten layer, and when the front metal layer is patterned, the tungsten layer and the barrier layer in the front metal layer removal area are also removed, and the tungsten layer and the barrier layer in the front metal layer retention area are also retained.

[0053] Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before the front metal layer is formed, and then a second barrier layer and the front metal layer are formed or the front metal layer is directly formed.

[0054] Further improvement is that the back process comprises:

[0055] The semiconductor substrate is back thinned.

[0056] A first conductive type heavily doped drain region is formed; the semiconductor substrate is heavily doped of the first conductive type, and the drain region is directly composed of the thinned semiconductor substrate; or the drain region is composed of a back implantation region which is back implanted of the second conductive type.

[0057] A back metal layer is formed and the drain is composed of the back metal layer.

[0058] Further improvement is that the setting of the thermal process corresponding to the subsequent front process comprises: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to no more than 950℃.

[0059] Further improvement is that the second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant.

[0060] Alternatively, the second trench has a side inclined structure with a wide bottom and a narrow top, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination and depth of the second trench. From the bottom to the top of the second trench, the doping concentration of the first epitaxial layer at the corresponding depth gradually increases, so that the charge balance of adjacent first conductive type columns and corresponding second conductive type columns at each longitudinal position meets the requirements.

[0061] Alternatively, the second trench has a top wide and bottom narrow side surface inclined structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side surface inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer gradually decreases from the bottom to the top of the second trench.

[0062] Further improvement is that after the first chemical mechanical polishing process, the top surface of the gate conductive material layer in the gate trench is located below the top surface of the first epitaxial layer outside the gate trench So as to facilitate the subsequent formation of the second trench.

[0063] Further improvement is that the first oxide film is composed of a thermal oxide film formed by a thermal oxidation process.

[0064] Alternatively, the first oxide film is composed of an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process.

[0065] Alternatively, the first oxide film is composed of a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process.

[0066] Further improvement is that the temperature of the thermal oxidation process of the thermal oxide film constituting the first oxide film is 900-950°C.

[0067] Further improvement is that the step of the super junction structure in the active region is a first step, the step in the transition region is a second step, and the step in the terminal region is a third step.

[0068] The first step, the second step and the third step are equal.

[0069] Alternatively, the second step is smaller than the first step, and the third step is smaller than the first step.

[0070] The process flow of the super-junction device is specially set in the application, mainly the formation process of the trench gate and the well region which requires higher heat process is placed before the formation process of the super-junction structure, the flatness of the gate conductive material layer in the gate trench is set including that the gate conductive material layer outside the gate trench is removed and the top surface of the gate conductive material layer in the gate trench is flat, which can ensure that the etching and filling process of the second trench of the super-junction structure is well realized; since the formation process of the trench gate and the well region is placed before the formation process of the super-junction structure, the formation process of the trench gate and the well region which requires higher heat process can not have adverse effects on the super-junction structure, so that the trench gate and the well region can adopt higher heat process according to their own needs, so that the quality of the trench gate and the well region is well guaranteed; meanwhile, the heat process after the super-junction structure is controlled in the application, which can ensure that the PN impurity diffusion of the super-junction structure meets the requirements, so that the on-resistance of the super-junction device meets the requirements. Since the PN impurity diffusion of the super-junction structure can be well controlled, the step of the super-junction structure can be further reduced, so that the on-resistance of the super-junction device is further reduced and the performance of the super-junction device is improved.

[0071] Although the formation process of the trench gate and the well region is placed before the formation process of the super-junction structure in the application, the flatness of the gate conductive material layer in the gate trench is controlled in the application, which can ensure that the super-junction structure can still be formed under the condition of forming the trench gate and the well region, so that the application also has the advantages of not increasing the process complexity and cost.

[0072] Therefore, the heat process of the trench gate, the heat process of the well region and the heat process of the super-junction structure can be independently set in the application, so that the quality of the trench gate and the well region is guaranteed, the PN impurity diffusion of the super-junction structure is effectively controlled, which is beneficial to realize the super-junction structure with smaller step and reduce the on-resistance of the super-junction device, and the process complexity and cost are not increased.

[0073] The protective ring oxide film is formed in the transition region and the terminal region after the formation of the super-junction structure in the application, which can improve the reliability of the product. BRIEF DESCRIPTION OF DRAWINGS

[0074] The application will be further described in detail below in combination with the drawings and specific embodiments:

[0075] Figure 1 is a flow chart of the manufacturing method of the super-junction device of the first embodiment of the application;

[0076] Figures 2A-2L is a device structure schematic diagram in each step of the manufacturing method of the super-junction device of the first embodiment of the application;

[0077] Figure 3is a device structure schematic diagram of the super junction device formed by the manufacturing method of the second embodiment of the present application. DETAILED DESCRIPTION

[0078] As shown in Figure 1 , it is a flow chart of the manufacturing method of the super junction device of the first embodiment of the present application; as shown in Figures 2A-2L , it is a device structure schematic diagram in each step of the manufacturing method of the super junction device of the first embodiment of the present application; the manufacturing method of the super junction device of the first embodiment of the present application comprises the following steps:

[0079] Step S101, growing a first epitaxial layer 102 of a first conductive type doping on the surface of a semiconductor substrate 101; the super junction device comprises an active region 201, a transition region 202 and a terminal region 203, the terminal region 203 surrounds the periphery of the active region 201, and the transition region 202 is located between the active region 201 and the terminal region 203.

[0080] Figure 2A In the embodiment, the area of the semiconductor substrate 101 is relatively large, and in the cross section of Figure 2A , the curve AA indicates that the active region 201, the transition region 202 and the terminal region 203 are continuously distributed, and the structure in the area omitted by the curve AA can refer to the structure shown in Figure 2A .

[0081] Step S102, as shown in Figure 2C , forming a plurality of trench gates in the first epitaxial layer 102; the trench gate comprises a gate oxide layer 104 formed on the inner side surface of a gate trench 103 and a gate conductive material layer 105 filled in the gate trench 103; each trench gate is located in the corresponding first conductive type column in the subsequent; the gate conductive material layer 105 outside the gate trench 103 is all removed, and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat, so as to ensure the formation process of the subsequent second trench 107, and the quality of the trench gate is adjusted by adjusting the heat process in the formation process of the trench gate.

[0082] In the first embodiment of the present application, the step of forming the trench gate comprises:

[0083] As shown in Figure 2A , a first dielectric layer 301 is formed on the top surface of the first epitaxial layer 102. The material of the first dielectric layer 301 generally adopts silicon oxide.

[0084] As shown in Figure 2A , photolithography defines the formation area of the gate trench 103. Among them, the photolithography will form a photoresist pattern 202, and the opening area of the photoresist pattern 202 is the formation area of the gate trench 103.

[0085] As shown in Figure 2BAs shown, the first dielectric layer 301 and the first epitaxial layer 102 in the region where the gate trench 103 is to be formed are etched in sequence to form the gate trench 103. The photoresist pattern 202 is removed before or after etching the first epitaxial layer 102 or consumed during the etching process.

[0086] like Figure 2C As shown, a thermal oxidation process is used to form the gate oxide layer 104. The thermal oxidation process has a high temperature thermal process. Since the thermal process corresponding to the thermal oxidation process is not affected by the subsequently formed super junction structure, the parameters of the thermal oxidation process can be set according to the need to form a high-quality gate oxide layer 104, and ultimately the quality of the trench gate is guaranteed.

[0087] like Figure 2C As shown, a gate conductive material layer 105 is formed.

[0088] In the first embodiment of the present invention, the gate conductive material layer 105 is made of polysilicon.

[0089] like Figure 2C As shown, a first chemical mechanical polishing process is performed to planarize the gate conductive material layer 105 to remove the gate conductive material layer 105 above the top surface of the first epitaxial layer 102 outside the gate trench 103 and to flatten the top surface of the gate conductive material layer 105 inside the gate trench 103 .

[0090] In the first embodiment of the present invention, after the first chemical mechanical polishing process, the top surface of the gate conductive material layer 105 in the gate trench 103 is located below the top surface of the first epitaxial layer 102 outside the gate trench 103. so that the second trench 107 can be formed subsequently, that is, so that the subsequent process of the second trench 107 can achieve its goal.

[0091] In some embodiments, before or after the first chemical mechanical polishing process, the method further includes performing a rapid thermal oxidation or a rapid thermal annealing.

[0092] like Figure 2C As shown, after the trench gate is formed, a protective film 204 is formed on the surface of the first epitaxial layer 102. The protective film 204 is formed by thinning the first dielectric layer 301, or by removing the first dielectric layer 301 and then oxidizing it. The protective film 204 can serve as a protective layer for subsequent ion implantation.

[0093] Step S103: Figure 2DAs shown, a well region 106 doped with a second conductive type is formed in the active region 201 and the transition region 202 by photolithography and ion implantation, and the well region 106 is annealed. Each trench gate passes through the well region 106. The thermal process of the annealing of the well region 106 is adjusted to push the well region 106 to the set position and repair the ion implantation damage.

[0094] The well region located in the transition region 202 is individually denoted by reference numeral 106a.

[0095] In the first embodiment of the present invention, the maximum annealing temperature of the well region 106 is greater than 1100° C., and the annealing time is greater than 30 minutes.

[0096] Step S104: Figure 2E As shown, photolithography and etching are performed to form multiple second trenches 107 in the first epitaxial layer 102. The first epitaxial layer 102 between the second trenches 107 serves as a first conductivity type pillar. The second trenches 107 are located in the active area 201, the transition area 202, and the portion of the terminal area 203 near the transition area 202. The depth of the second trenches 107 is much greater than the depth of the gate trench 103. Photolithography and etching means first defining the etching area through photolithography, and then performing etching.

[0097] In the first embodiment of the present invention, before performing the photolithography process on the second trench 107, the process further includes forming a hard mask layer. The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer, and a top silicon dioxide layer stacked in sequence.

[0098] In the etching process of the second trench 107 , the hard mask layer is etched first, and then the first epitaxial layer 102 is etched.

[0099] After the etching of the second trench 107 is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench 107 are removed, and then the subsequent growth of the second epitaxial layer 108 is performed.

[0100] Step S105: Figure 2E As shown, a second epitaxial layer 108 doped with a second conductive type is grown in the second trench 107, the second epitaxial layer 108 outside the second trench 107 is completely removed and the surface of the second epitaxial layer 108 in the second trench 107 is flattened, and the second epitaxial layer 108 filled in the second trench 107 forms a second conductive type column, and the first conductive type column and the second conductive type column are alternately arranged to form a super junction structure.

[0101] In the first embodiment of the present invention, the step of the super junction structure in the active area 201 is the first step, the step in the transition area 202 is the second step, and the step in the terminal area 203 is the third step; the first step, the second step and the third step are equal.

[0102] In other embodiments, the second step size can be less than the first step size, and the third step size can be less than the first step size, or the third step size can be equal to the second step size.

[0103] The second epitaxial layer 108 is then planarized by a second chemical mechanical polishing process to remove the second epitaxial layer 108 outside the second trench 107 and to make the surface of the second epitaxial layer 108 in the second trench 107 flat.

[0104] The bottom silicon dioxide layer 205 with a certain thickness is retained on the surface of the first epitaxial layer 102 after the second chemical mechanical polishing process.

[0105] The first conductive type column and the second conductive type column of the super junction structure achieve charge matching at each longitudinal position.

[0106] In some embodiments, the second trench 107 has a vertical side surface structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is constant.

[0107] In some embodiments, the second trench 107 has a top wide and bottom narrow side surface inclined structure, the doping concentration of the second epitaxial layer 108 is constant, and the doping concentration of the first epitaxial layer 102 is set according to the side surface inclination angle and depth of the second trench 107, and the doping concentration of the first epitaxial layer 102 at the corresponding depth gradually increases from the bottom to the top of the second trench 107, so that the charge balance of the adjacent first conductive type column and the corresponding second conductive type column at each longitudinal position meets the requirements.

[0108] In some embodiments, the second trench 107 has a top wide and bottom narrow side surface inclined structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is set according to the side surface inclination angle and depth of the second trench 107, and the doping concentration of the second epitaxial layer 108 at the corresponding depth gradually decreases from the bottom to the top of the second trench 107.

[0109] In step S106, a subsequent front process after the super junction structure is completed, in which a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure, so that the on-resistance of the super junction device meets the requirements.

[0110] In the first embodiment of the present application, the setting of the thermal process corresponding to the subsequent front process includes that when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950℃.

[0111] The subsequent front process includes:

[0112] As Figure 2FAs shown, a first oxide film 110a is formed and the first oxide film 110a is patterned and etched to remove the first oxide film 110a at the active area 201 and the outermost cutoff area 109a of the terminal area 203. The retained first oxide film 110a covers the inner area of ​​the cutoff area 109a of the transition area 202 and the terminal area 203 and forms a protective epoxy film.

[0113] In some embodiments, the first oxide film 110a is formed by a thermal oxide film formed by a thermal oxidation process, and the thickness of the thermal oxide film is The temperature of the thermal oxidation process of the thermal oxide film constituting the first oxide film 110a is 900°C to 950°C.

[0114] In some embodiments, the first oxide film 110a can be formed by stacking an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process, and the thickness of the ALD oxide film is The thickness of the thermal oxide film is The temperature of the thermal oxidation process of the thermal oxide film constituting the first oxide film 110 a is 900° C. to 950° C. The ALD oxide film can obtain a better interface between the first epitaxial layer 102 and the first oxide film 110 a , and can improve the high temperature reverse bias stress (HTRB) reliability of the device.

[0115] In some embodiments, the first oxide film 110a can be formed by stacking a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process, and the thickness of the thermal oxide film is The thickness of the CVD oxide film is The temperature of the thermal oxidation process of the thermal oxide film constituting the first oxide film 110a is 900°C to 950°C.

[0116] In the first embodiment of the present invention, the subsequent front surface process further includes:

[0117] like Figure 2G As shown, photolithography and ion implantation are performed to form a heavily doped source region 109 of the first conductivity type. The source region 109 and the side surface of the corresponding gate trench 103 are self-aligned.

[0118] In the first embodiment of the present invention, while forming the source region 109 , a cutoff region 109 a heavily doped with the first conductivity type is formed in the surface region of the first epitaxial layer 102 at the outer edge of the termination region 203 .

[0119] The source region 109 is annealed and activated. The annealing of the source region 109 is performed in a furnace at a temperature below 950° C. or by rapid thermal annealing.

[0120] like Figure 2HAs shown, an interlayer film 110 is formed, which is composed of a stack of undoped silicon dioxide layer and BPSG layer.

[0121] As shown, a contact hole opening 111 is formed through the interlayer film 110, which also extends into the first epitaxial layer 102 and contacts the surface source region 109 and the well region 106. Figure 2H

[0122] As shown, a second conductive type heavily doped contact region 111a, i.e. contact hole implant (CT IMP), is formed at the bottom of the contact hole opening 111. Figure 2I

[0123] As shown, a metal layer is filled in the contact hole opening 111 to form a contact hole. Figure 2I

[0124] The metal layer forming the contact hole includes:

[0125] A barrier layer 112 is formed on the inner surface of the contact hole opening 111.

[0126] In some embodiments, the material of the barrier layer 112 includes a Ti layer and a TiN layer stacked in sequence.

[0127] As shown, a tungsten layer 113 is formed, which is filled in the contact hole opening 111. Figure 2J The barrier layer 112 and the tungsten layer 113 also extend onto the surface of the interlayer film 110 outside the contact hole opening 111.

[0128] As shown, a front metal layer 114 is formed. The front metal layer 114 is patterned and etched to form source and gate electrodes, the source region 109 and the well region 106 are connected to the source electrode through the corresponding contact hole on the top, and the gate electrode is connected through the contact hole on the top of the gate conductive material layer 105 of the trench gate lead end. In some embodiments, the material of the front metal layer 114 includes AlCu.

[0129] Figure 2J In the first embodiment of the present application, the front metal layer 114 is formed on the surface of the tungsten layer 113, and when the front metal layer 114 is patterned, the tungsten layer 113 and the barrier layer 112 in the area where the front metal layer 114 is removed are also removed, and the tungsten layer 113 and the barrier layer 112 in the area where the front metal layer 114 is retained are also retained. Only the source forming area is shown, so

[0130] In the second embodiment of the present application, the front metal layer 114 and the bottom tungsten layer 113 and the barrier layer 112 are all retained. Figure 2I Figure 2I

[0131] Figure 2J ​​​​​In the figure, the patterned front metal layer 114 includes: a source electrode corresponding to label 114a, a gate bus corresponding to label 114b, a transition region field plate corresponding to label 114c, multiple terminal region field plates corresponding to labels 114d1, 114d2 to 114dx, and a metal connected to the drain electrode corresponding to label 114e. The bottom of metal 114e is connected to the cut-off region 109a. The source electrode 114a and the gate bus 114b need to be separated, and the gate bus 114b and the transition region field plate 114c can be an integrated structure or separated structures. The terminal region field plates 114d1, 114d2 to 114dx are separated structures. The number of terminal region field plates 114d1, 114d2 to 114dx can be adjusted as needed, and the terminal region field plates 114d1, 114d2 to 114dx can also be omitted.

[0132] In the first embodiment of the present invention, a front passivation protection process is further performed, and the front passivation protection process further comprises:

[0133] like Figure 2K As shown, a dielectric protection layer 115 is formed; the dielectric protection layer 115 is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0134] Photolithography and dry etching are performed to pattern the dielectric protection layer 115 to open the lead-out region of the source and the lead-out region of the gate.

[0135] like Figure 2L As shown, the front passivation protection process also includes:

[0136] A polyimide layer 116 is formed.

[0137] Photolithography and development are performed to pattern the polyimide layer 116 to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0138] The polyimide layer 116 is baked.

[0139] In the first embodiment of the present invention, the dielectric protection layer 115 and the polyimide layer 116 are stacked simultaneously.

[0140] In some embodiments, only the dielectric protection layer 115 may be formed, and the polyimide layer 116 may be omitted.

[0141] In some embodiments, the dielectric protection layer 115 can be omitted and only the polyimide layer 116 can be formed.

[0142] Step S107 , completing the backside process of the super junction device.

[0143] In the first embodiment of the present invention, the back surface process includes:

[0144] The semiconductor substrate 101 is back-thinned.

[0145] A first-conductivity-type heavily doped drain region is formed. In the first embodiment of the present application, the semiconductor substrate 101 is first-conductivity-type heavily doped, and the drain region is directly composed of the thinned semiconductor substrate 101, so that the drain region does not need to be activated further. In other embodiments, the drain region can be composed of a back-implanted region of a second-conductivity-type heavily doped on the back of the semiconductor substrate 101, and the drain region needs to be activated later.

[0146] A back metal layer 117 is formed and composed of the back metal layer 117 to form the drain. In some embodiments, the back metal layer 117 includes TiNiAg.

[0147] In the first embodiment of the present application, the super-junction device is an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the super-junction device can be a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0148] In the first embodiment of the present application, the process flow of the super-junction device is specially set, mainly by placing the formation process of the trench gate and the well region 106, which requires a higher thermal process, before the formation process of the super-junction structure, and by setting the flatness of the gate conductive material layer 105 in the gate trench 103 to include that the gate conductive material layer 105 outside the gate trench 103 is removed and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat, so that the etching and filling process of the second trench 107 of the super-junction structure can be well implemented. Since the formation process of the trench gate and the well region 106 is placed before the formation process of the super-junction structure, the formation process of the trench gate and the well region 106, which requires a higher thermal process, does not adversely affect the super-junction structure, so that the trench gate and the well region 106 can use a higher thermal process according to their own needs, so that the quality of the trench gate and the well region 106 is well guaranteed. Meanwhile, the thermal process after the super-junction structure is controlled in the first embodiment of the present application, so that the PN impurity diffusion of the super-junction structure meets the requirements, so that the on-resistance of the super-junction device meets the requirements. Since the PN impurity diffusion of the super-junction structure can be well controlled, the step of the super-junction structure can be further reduced, so that the on-resistance of the super-junction device can be further reduced and the performance of the super-junction device can be improved.

[0149] Although the first embodiment of the present invention places the process of forming the trench gate and the well region 106 before the process of forming the super junction structure, the first embodiment of the present invention controls the flatness of the gate conductive material layer 105 in the gate trench 103, which can ensure that the super junction structure can still be easily formed under the conditions of forming the trench gate and the well region 106. Therefore, the first embodiment of the present invention also has the advantage of not increasing the process complexity and cost.

[0150] Therefore, the first embodiment of the present invention can independently set the thermal process of the trench gate, the thermal process of the well region 106, and the thermal process of the super junction structure, so that the quality of the trench gate and the well region 106 is guaranteed while the mutual diffusion of PN impurities in the super junction structure is effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost.

[0151] The first embodiment of the present invention further forms a protective epoxy film in the transition region 202 and the terminal region 203 after the super junction structure is formed, thereby improving product reliability.

[0152] like Figure 3 , which is a schematic diagram of the device structure of a super junction device formed by the manufacturing method of a super junction device according to the second embodiment of the present invention; the difference from the manufacturing method of a super junction device according to the first embodiment of the present invention is that in the manufacturing method of a super junction device according to the second embodiment of the present invention,

[0153] Before forming the front metal layer 114, the barrier layer 112 and the tungsten layer 113 outside the contact hole opening 111 are removed, and then the second barrier layer 112a and the front metal layer 114 are formed. In some embodiments, the material of the second barrier layer 112a includes a Ti layer and a TiN layer stacked in sequence.

[0154] In other embodiments, the tungsten layer 113 outside the contact hole opening 111 may be removed before forming the front metal layer 114 , and then the front metal layer 114 may be directly formed.

[0155] In the first embodiment of the present invention, using an N-type MOSFET as an example, the thermal process after the P-type pillar is formed can be significantly reduced, thereby further reducing the on-resistance of the device. The following uses a 600V trench gate super junction N-type MOSFET as an example, and combines the corresponding parameters to further illustrate the first embodiment of the present invention:

[0156] In step S101 , the semiconductor substrate 101 is a low-resistivity N-type substrate. For example, the resistivity of the semiconductor substrate 101 is less than 0.003 ohm.cm.

[0157] The thickness of the first epitaxial layer 102 is 45-50 microns. The resistivity of the first epitaxial layer 102 is designed in association with the step of the P-type column (second conductive type column) and N-type column (first conductive type column) to be formed later, and can be designed by simulation with computer-aided software. For example, the step of the PN column is set to 5 microns, and the resistivity is set to 0.5 ohm-cm.

[0158] In step S102, the thickness of the first dielectric layer 201 is 0.5-2 microns.

[0159] The width and depth of the gate trench 103 can be set according to the performance of the device. For example, the width of the gate trench 103 is set to 0.8-1.5 microns, and the depth is set to 2.5-4 microns.

[0160] The thickness of the gate oxide layer 104 is set to 500-1500 angstroms.

[0161] The resistivity of the polysilicon of the gate conductive material layer 105 is generally set to about 10-30 ohm-cm. Before or after the planarization of the polysilicon of the gate conductive material layer 105, a high-temperature RTO or high-temperature RTA can be performed, so as to improve the leakage between the gate and the drain of the product.

[0162] In step S103, the impurity of the ion implantation of the well region 106 is generally B, the implantation energy is 100 Kev, and the implantation dose is designed according to the threshold voltage of the device, for example, the implantation dose is 1E13 atoms / cm 2 . The ion implantation of the well region 106 can also be realized by using two different energy B implantations, so as to construct different P-type wells (well regions 106) and adjust the performance parameters of the device, including the threshold voltage and EAS, etc. After the ion implantation of the well region 106 is formed, a high-temperature annealing can be performed, for example, 1100C for 30 min or higher temperature and longer time annealing. 1100C for 30 min means thermal annealing at 1100C for 30 min. In this way, on the one hand, the P-type well is pushed to the set position, and on the other hand, some damage caused in the ion implantation process can be repaired.

[0163] Before the B implantation of the well region 106, the dielectric film on the surface of the silicon (semiconductor substrate 101) and the first epitaxial layer 102 is thinned to about 200 angstroms to play the role of the ion implantation protection film 204. This oxide film (protection film 204) can be the film left after the previous polysilicon CMP (first chemical mechanical polishing), and is obtained by dry or wet etching. It can also be a generated thermal oxide film or CVD film after the film after the polysilicon CMP is completely removed. The latter plays the role of increasing the consistency of the ion implantation protection film, and can also improve the consistency of the device parameters, especially the threshold voltage.

[0164] The thickness of the bottom silicon dioxide layer is 0.5-1.5 microns. The thickness of the intermediate silicon nitride layer is 0.5-1.5 microns. The thickness of the top silicon dioxide layer is 2-5 microns.

[0165] The width of the deep trench, i.e. the second trench 107, is 2.5 microns, the size of the N region between adjacent trenches, i.e. the distance between the second trenches 107, is 2.5 microns, and the depth of the second trench 107 is 40-42 microns, which can be set according to the BVdss requirement of the device.

[0166] After etching the second trench 107, the hard mask top SIO2 and SIN, i.e. the top silicon dioxide layer and the intermediate silicon nitride layer, are removed, and the bottom SIO2, i.e. the bottom silicon dioxide layer, is kept as a protective layer for the Si surface. Then the second trench 107 is completely filled by P-type epitaxial deposition, and then the surface Si is removed by chemical mechanical polishing. In this setting, the P-type pillars and the N-type pillars are adjacent, and the step in the active region 201, the transition region 202 and the termination region 203 can be set to the same step, the same P-type pillar width, and the same N-type pillar width, for example, the step is set to step 5 μm, the P-type pillar top width is 2.5 μm, and the N-type pillar top width is 2.5 μm. It can also be set that the steps in the transition region 202 and the termination region 203 are different from the step in the active region, and generally the steps in the transition region 202 and the termination region 203 are set to be smaller than the step in the active region, for example, the step in the transition region 202 and the termination region 203 is set to step 4.8 μm, the P-type pillar top width is 2.5 μm, and the N-type pillar top width is 2.3. μm. The outermost P-type pillar of the termination region 203 is a certain distance from the outermost periphery of the chip, for example, 15-30 microns.

[0167] In step S106, when the first oxide film 110a is formed, a thermal oxidation is performed on the silicon wafer, i.e. the semiconductor substrate 101 on which the first epitaxial layer 102 is formed, to form a thermal oxide film with a thickness of 2000-8000 angstrom. The temperature of the thermal oxidation can be set at 900-950°C. In order to obtain a better SI-SiO2 interface and improve the high temperature reverse bias stress (HTRB) reliability of the device, a very thin oxide film with a thickness of 30-100 angstrom can also be deposited on the silicon wafer by using an atomic layer deposition (ALD) device, and then a thermal oxide film with a thickness of 2000-8000 angstrom is formed. If the thermal oxide film is set at 2000 angstrom, a CVD oxide film (not doped) with a thickness of 2000-6000 angstrom can be further deposited. Then the first oxide film 110a in the active region 201 is removed by photolithography and wet etching, and the first oxide film 110a in the outermost part of the termination region 203 (cut-off region) is also removed, while the first oxide film 110a in the transition region 202 and other parts of the termination region 203 is kept. The total thickness of the retained first oxide film 110a is 4000-8000 angstrom.

[0168] In step S106, as shown in Figure 2F , an oxide film with a thickness of 100-300 angstrom is deposited on the surface of the active region 201 and the outermost part of the chip as a protective film for subsequent N+ implantation, and then the N+ source region 109 is formed by photolithography and ion implantation. Here, the N+ can be phosphorus implantation or arsenic (As) implantation. For example, As 60 keV 1-5E15 atoms / cm 2 , As 60 keV 1-5E15 atoms / cm 2 indicates that the implanted impurity is As, the implantation energy is 60 keV, and the implantation dose is 1 atoms / cm 2 -5E15 atoms / cm 2 . After ion implantation of the source region 109, an activation process at a temperature below 950°C, for example 900°C for 30 min, can be performed, or RTA activation can be used.

[0169] In the step of forming the interlayer film 110, a 2000 angstrom undoped silicon dioxide layer is first deposited, and then a BPSG layer with a thickness of 8000-10000 angstrom is deposited.

[0170] In the step of forming the contact hole, the contact hole opening 111 can penetrate into the Si in the first epitaxial layer 102 to

[0171] The bottom of the contact hole opening 111 can form a P-type region, i.e. a contact region 111a, by implanting B or BF2. For example, when the contact region 111a is implanted by B, the implantation energy can be 30-60 keV, and the implantation dose can be 5E14-1E15 / cm2 This is to ensure the ohmic contact between the metal in the contact hole opening 111 and the Si at the bottom of the contact hole opening 111 and to reduce the contact resistance.

[0172] In the step of forming the barrier layer 112, the thickness of the Ti layer is The thickness of the TiN layer is

[0173] In the step of forming the tungsten layer 113, the process of filling the contact hole opening 111 with the metal tungsten is to grow along the sidewall of the contact hole opening 111 and to contact the upper part in the central area of the contact hole opening 111. The upper part can have some gaps or no gaps. The tungsten can completely fill the contact hole opening 111 or not, as long as the subsequent metal can well cover the hole.

[0174] In the step of forming the front metal layer 114, the deposition temperature of the AlCu can be set to 250-450C and the thickness can be set to 2-6 microns. Then, the metal Al-Cu, the tungsten layer 113 below the Al-Cu and the barrier layer 112 are removed by the metal lithography and dry etching.

[0175] In addition, as an alternative, in the second embodiment of the present application, the following can be used as an alternative:

[0176] Before forming the front metal layer 114, the W on the surface of the Si is completely removed by dry etching, then the barrier layer 112 below the W is also completely etched, and then the Ti / TiN / AlCu, i.e. the second barrier layer 112a and the front metal layer 114, are deposited. The thickness of the films can be set as follows: 5 microns, or other settings, wherein 5 microns means that the thickness of the Ti layer is The thickness of the TiN layer is The thickness of the AlCu is 5 microns. Or after the W on the surface is completely etched, only the deposition of the AlCu is performed, for example, 5 microns thick AlCu is deposited. After the deposition of the AlCu is completed, the metal lithography and dry etching are performed.

[0177] In step S107, the entire thickness of the Si wafer, i.e. the entire thickness of the semiconductor substrate 101 and the first epitaxial layer 102, is thinned to 60-200 microns.

[0178] The thickness of the TiNiAg of the back metal layer 115 can be i.e. the thickness of the Ti layer the thickness of the Ni layer the thickness of the Ag layer

[0179] The above process can realize the manufacture of a super-junction MOSFET, and can form the division of the active region, the transition region and the terminal region for bearing the lateral voltage. The electrode of the source region is led out through the front metal layer 114 in Figure 2L The gate is led out through the contact hole connected to the end of the trench gate through layout design, metal, and trench gate in Figure 2L The drain is the back metal layer 115.

[0180] Based on the MOSFET obtained through the above manufacturing process, the following front passivation process can be further added to improve the performance and reliability of the product, which includes:

[0181] A 1-2 micron dielectric protective layer can be deposited, which can be SiON, SiO2, SiN, silicon oxide film rich in Si, or a combination thereof. Then, the electrode leading-out area of the gate is opened, the electrode leading-out area of the source is opened, and other areas including the terminal region for bearing the lateral voltage are protected through photoetching and dry etching, so as to improve the reliability of the product.

[0182] The front passivation process further includes:

[0183] A polyimide film can be deposited on the surface of the silicon wafer, which can be formed on the surface of the dielectric protective layer or omitted. Then, the electrode leading-out area of the gate is opened, the electrode leading-out area of the source is opened, and other areas including the terminal region for bearing the lateral voltage are protected through photoetching and developing, so as to improve the reliability of the product. After photoetching and developing, baking at 300-400C (30-90min) can be performed, and the thickness of the polyimide film is 4-15 microns after baking.

[0184] In the first embodiment of the present application, in order to reduce the mutual diffusion of P-type column and N-type column after the formation of the P-type column, the temperature during the heat process after the formation of the P-type column is limited to not more than 950C for more than 10 minutes.

[0185] In the first embodiment of the present application, the following further optimization can be performed:

[0186] In step S101, the first epitaxial layer 102 can be set according to the inclination angle and depth of the trench, i.e., the second trench 107, in step S104. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e., consistent from top to bottom. If the trench is an inclined trench with a large top and a small bottom, the N epitaxial layer, i.e., the first epitaxial layer 102, can be set to have a high concentration at the top and a low concentration at the bottom, with the concentration varying linearly in the middle, so that the balance of PN can be achieved when the impurity concentration of the p-type column, i.e., the second conductive type column, is a single concentration at each position perpendicular to the trench, and the balance of the source-drain breakdown voltage (BVdss) and Rdson of the device can be better achieved.

[0187] In the filling of the trench, i.e., the second trench 107, with the second epitaxial layer 108 in step S105, the first epitaxial layer 102 can be set in combination with the inclination angle of the trench. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e., consistent from top to bottom, and the impurity concentration of the p-type column can also be constant. If the resistivity of the first epitaxial layer 102 can be set to be constant, and the trench is an inclined trench with a large top and a small bottom, the P-type epitaxial deposition process can be set to have a high P-type impurity concentration at the beginning and gradually reduce the deposition concentration. The specific process conditions can be determined by evaluating the BVdss of the device and the window relationship of the P-type impurity setting, with the goal of expanding the process window of the P-type epitaxial process.

[0188] Compared with the prior art, the first embodiment of the present application adopts a new process flow without increasing the process complexity and cost. Before the formation of the P-type column trench, i.e., the second trench 107, the high-heat process of the gate oxide process, i.e., the formation of the gate oxide layer 104, and the P-type well formation are all placed before the P-type column trench. After the formation of the P-type column, the heat process is set to be below 950C, or only the RTA and other special short-time activation processes are used. At the same time, by adding a thermal oxide film or a combination of a thermal oxide film and an ALD film, or a combination of these films and a cvd film in the transition zone and the area subjected to lateral voltage after the formation of the P-type column, the reliability of the product can be improved.

[0189] The present application has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can make many modifications and improvements without departing from the principles of the present application, and these should also be considered within the scope of protection of the present application.

Claims

1. A method for manufacturing a super junction device, characterized in that: The steps include: A first epitaxial layer doped with a first conductivity type is grown on a surface of a semiconductor substrate; the superjunction device includes an active region, a transition region, and a terminal region, wherein the terminal region surrounds the active region, and the transition region is located between the active region and the terminal region; forming a plurality of trench gates in the first epitaxial layer of the active region, wherein the trench gates include a gate oxide layer formed on an inner surface of a gate trench and a gate conductive material layer filled in the gate trench; Each trench gate is located in a subsequent corresponding first conductivity type column; the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer inside the gate trench is flat to ensure the implementation of the subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process; forming a well region doped with a second conductive type in the active region and the transition region by photolithography and ion implantation, and annealing the well region, wherein each trench gate passes through the well region, and adjusting a thermal process of the annealing of the well region so as to push the well region to a set position and repair ion implantation damage; Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, wherein the first epitaxial layer between the second trenches serves as a first conductivity type pillar; the second trenches are located in a portion of the active region, the transition region, and the terminal region close to the transition region; growing a second epitaxial layer doped with a second conductivity type in the second trench, removing all of the second epitaxial layer outside the second trench and smoothing the surface of the second epitaxial layer in the second trench, forming second conductivity type pillars from the second epitaxial layer filled in the second trench, and forming a super junction structure by alternating the first conductivity type pillars and the second conductivity type pillars; After completing the super junction structure, a subsequent front-side process is performed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities in the super junction structure so that the on-resistance of the super junction device meets the requirement; The subsequent front surface process includes: forming a first oxide film and patterning and etching the first oxide film to remove the first oxide film in the active area and the outermost cut-off area of ​​the terminal area, and the remaining first oxide film covers the inner area of ​​the transition area and the cut-off area of ​​the terminal area to form a protective epoxy film; the formation process of the first oxide film includes a thermal oxidation process; Complete the backside process of super junction devices.

2. The method for manufacturing a super junction device according to claim 1, wherein: The steps of forming the trench gate include: forming a first dielectric layer on a top surface of the first epitaxial layer; Photolithography defines a formation area of ​​the gate trench; Sequentially etching the first dielectric layer and the first epitaxial layer in the gate trench formation region to form the gate trench; forming the gate oxide layer by a thermal oxidation process; forming the gate conductive material layer; A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

3. The method for manufacturing a super junction device according to claim 2, wherein: Before or after the first chemical mechanical polishing process, the method further includes: Perform a rapid thermal oxidation or a rapid thermal annealing.

4. The method for manufacturing a super junction device according to claim 1, wherein: The maximum annealing temperature of the well region is above 1100° C., and the annealing time is above 30 minutes.

5. The method for manufacturing a super junction device according to claim 1, wherein: Before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer; In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

6. The method for manufacturing a super junction device according to claim 5, wherein: The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence; After the etching of the second trench is completed, removing the top silicon dioxide layer and the middle silicon nitride layer outside the second trench, and then growing the second epitaxial layer; Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

7. The method for manufacturing a super junction device according to claim 1, wherein: The subsequent front surface process includes: Performing photolithography and ion implantation to form a heavily doped source region of the first conductivity type, wherein the source region and the corresponding side surface of the gate trench are self-aligned; Annealing and activating the source region, wherein the annealing of the source region is performed in a furnace at a temperature below 950° C. or by rapid thermal annealing; When the source region is formed, a cutoff region heavily doped with the first conductivity type is formed in a surface region of the first epitaxial layer at an outer edge of the terminal region.

8. The method for manufacturing a super junction device according to claim 7, wherein: The subsequent front surface process further includes: forming an interlayer film, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer; forming a contact hole opening through the interlayer film; forming a second conductive type heavily doped contact region at the bottom of the contact hole opening; Filling the contact hole opening with a metal layer to form a contact hole; A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

9. The method for manufacturing a super junction device according to claim 8, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a dielectric protection layer; the dielectric protection layer is a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer, or a combination thereof; The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

10. The method for manufacturing a super junction device according to claim 8 or 9, wherein: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a polyimide layer; Performing photolithography and development to pattern the polyimide layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode; The polyimide layer is baked.

11. The method for manufacturing a super junction device according to claim 8, wherein: The metal layer forming the contact hole includes: forming a barrier layer, wherein the barrier layer is formed on the inner surface of the contact hole opening; forming a tungsten layer, wherein the tungsten layer is filled in the contact hole opening; The barrier layer and the tungsten layer further extend onto the surface of the interlayer film outside the contact hole opening; The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer are also removed in the front metal layer removal area, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area. Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed, or the front metal layer is directly formed.

12. The method for manufacturing a super junction device according to claim 1, wherein: The back side process includes: performing backside thinning on the semiconductor substrate; forming a drain region heavily doped with a first conductivity type; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is directly formed by thinning the semiconductor substrate; or, the drain region is formed by a backside implantation region in which the backside of the semiconductor substrate is heavily doped with a second conductivity type; A back metal layer is formed and a drain electrode is formed from the back metal layer.

13. The method for manufacturing a super junction device according to claim 12, wherein: The setting of the thermal process corresponding to the subsequent front surface process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

14. The method for manufacturing a super junction device according to claim 1, wherein: The second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant; Alternatively, the second trench has a side slope structure that is wide at the top and narrow at the bottom, the doping concentration of the second epitaxial layer is constant, the doping concentration of the first epitaxial layer is set according to the side slope angle and depth of the second trench, and the doping concentration of the first epitaxial layer at corresponding depths gradually increases from the bottom to the top of the second trench, so that charge balance between adjacent first conductivity type pillars and corresponding second conductivity type pillars at each longitudinal position meets requirements; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench. From the bottom to the top of the second trench, the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases.

15. The method for manufacturing a super junction device according to claim 2, wherein: After the first chemical mechanical polishing process, the top surface of the gate conductive material layer in the gate trench is located 500Å to 1000Å below the top surface of the first epitaxial layer outside the gate trench to facilitate the subsequent formation of the second trench.

16. The method for manufacturing a super junction device according to claim 1 or 13, wherein: The first oxide film is composed of a thermal oxide film formed by a thermal oxidation process; Alternatively, the first oxide film is formed by stacking an ALD oxide film formed by an ALD process and a thermal oxide film formed by a thermal oxidation process; Alternatively, the first oxide film is formed by stacking a thermal oxide film formed by a thermal oxidation process and a CVD oxide film formed by a CVD process.

17. The method for manufacturing a super junction device according to claim 16, wherein: The temperature of the thermal oxidation process of the thermal oxidation film constituting the first oxide film is 900° C. to 950° C.

18. The method for manufacturing a super junction device according to claim 1, wherein: The step of the super junction structure in the active area is a first step, the step in the transition area is a second step, and the step in the terminal area is a third step; The first step, the second step and the third step are equal; Alternatively, the second step is smaller than the first step, and the third step is smaller than the first step.

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