Semiconductor structure and manufacturing method thereof, radio frequency device and electronic equipment

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof, a radio frequency device and electronic equipment, and aims to solve the problem of low rollback efficiency. The active region structure is arranged on a substrate, the active region structure comprises a barrier layer and a channel layer which are arranged in a stacked mode, electrode layers are arranged on the active region structure in a stacked mode, electrodes comprise a first electrode and a second electrode which are arranged in a spaced mode, and the first electrode and the second electrode are both connected with the barrier layer; wherein the width of the interface of the channel layer and the barrier layer in the direction parallel to the current is gradually reduced in the direction perpendicular to the current direction, and the flowing speed of electrons is gradually increased along with the reduction of the width of the interface in a conducting state, so that the electrons can reach the saturation drift speed more quickly, and the saturation current is further achieved; the knee point voltage is reduced, and the rollback efficiency of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and specifically to a semiconductor structure and a manufacturing method thereof, a radio frequency device, and an electronic device. Background Art

[0002] Gallium nitride transistors have been widely used in fields such as radio frequency due to their advantages such as wide bandgap, high critical breakdown electric field, high electron saturation velocity, high thermal conductivity, and strong radiation resistance; however, the back-off efficiency of gallium nitride transistors is low, which affects the performance of gallium nitride transistors. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor structure and a manufacturing method thereof, a radio frequency device and an electronic device, which can improve the fallback efficiency.

[0004] In a first aspect, an embodiment of the present application provides a semiconductor structure, including: a substrate and a device structure, wherein the device structure is disposed on the substrate, and the device structure includes:

[0005] An active region structure, the active region structure includes a barrier layer and a channel layer stacked in a direction parallel to the current, and a width of an interface between the channel layer and the barrier layer gradually decreases along a direction perpendicular to the current direction;

[0006] The electrode layer is stacked on the active area structure, and the electrode layer includes a first electrode and a second electrode that are spaced apart, and both the first electrode and the second electrode are connected to the barrier layer.

[0007] Through the above-mentioned arrangement, the active area structure is arranged on the substrate, the active area structure includes a barrier layer and a channel layer that are stacked, the electrode layer is stacked on the active area structure, the electrode includes a first electrode and a second electrode that are spaced apart, and the first electrode and the second electrode are both connected to the barrier layer; wherein, along a direction parallel to the current, the width of the interface between the channel layer and the barrier layer along a direction perpendicular to the current gradually decreases, and in the on state, the flow velocity of electrons gradually increases with the decrease in the width of the interface, thereby enabling the electrons to reach the saturation drift velocity faster, and then reach the saturation current, thereby reducing the knee voltage, improving the back-off efficiency of the semiconductor structure, and thereby improving the performance of the semiconductor structure.

[0008] In some embodiments that may include the above embodiments, the projections of the channel layer and the barrier layer on the substrate completely overlap. This arrangement can reduce the space occupied by the channel layer and the barrier layer, reduce the volume of the device structure, and further reduce the volume of the semiconductor structure; on the other hand, due to the small volume of the device structure, more device structures can be arranged in the semiconductor structure of the same volume, thereby improving the arrangement density of the device structure.

[0009] In some embodiments that may include the above embodiments, the projection of part of the barrier layer on the substrate coincides with the projection of part of the channel layer on the substrate, that is, part of the barrier layer and part of the channel layer contact and form an interface, and the width of the interface gradually decreases along the direction parallel to the current.

[0010] In some embodiments that may include the above embodiments, the projection of the barrier layer on the substrate is located within the projection of the channel layer on the substrate, and accordingly, the surface of the barrier layer facing the channel layer contacts the channel layer to form an interface.

[0011] In some embodiments that may include the above embodiments, the projection of the channel layer on the substrate is located within the projection of the barrier layer on the substrate, and accordingly, the surface of the channel layer facing the barrier layer contacts the barrier layer to form an interface.

[0012] In some embodiments that may include the above embodiments, the first electrode and the second electrode are both in contact with the barrier layer, and the width of the interface between the channel layer and the barrier layer gradually decreases along the direction perpendicular to the current from the first electrode to the second electrode. That is, the width of the barrier layer between the second electrode and the substrate is smaller than the width of the barrier layer between the first electrode and the substrate, and the width of the barrier layer between the second electrode and the substrate is the smallest. In this way, in the on state, the number of electrons at the interface near the first electrode is much larger than the interface near the second electrode. Under the action of a high electric field, the electrons converge to the interface near the second electrode, and the flow speed of the electrons gradually increases, so that the electrons can quickly reach the saturation drift speed, and then reach the saturation current, thereby reducing the knee voltage and improving the back-off efficiency of the semiconductor structure.

[0013] In some embodiments that may include the above embodiments, the projection of the interface between the channel layer and the barrier layer on the substrate is triangular, the first electrode is connected to the barrier layer corresponding to the preset side of the triangle, and the second electrode is connected to the barrier layer corresponding to the preset vertex opposite to the preset side. Through the above arrangement, the projection of the interface on the substrate is triangular, and the shape of the interface is relatively regular, which reduces the difficulty of manufacturing the semiconductor structure.

[0014] In some embodiments that may include the above embodiments, there are multiple device structures, and the multiple device structures are arranged around a preset center. The multiple device structures are arranged around a preset center on the substrate. Such an arrangement improves the layout rationality of the device structure, thereby improving the density of the device.

[0015] In some embodiments that may include the above embodiments, the second electrode of each device structure is arranged close to a preset center, which can further improve the rationality of the layout of the device structure.

[0016] In some embodiments that may include the above-mentioned embodiments, adjacent device structures may be arranged at intervals, that is, the first electrodes of each device structure are arranged at intervals, the second electrodes of each device structure are arranged at intervals, the gates of each device structure are arranged at intervals, and the interfaces of each device structure are arranged at intervals; accordingly, each device structure can be turned on and off individually through the corresponding gate.

[0017] In some embodiments that may include the above embodiments, the first electrodes of the device structures are connected, and the second electrodes of the device structures are connected to form a cell. The device structures are connected in parallel, and the device structures in the cell are turned on and off at the same time. Through the above arrangement, the operating current and power of the semiconductor structure can be increased to further improve the performance of the semiconductor structure.

[0018] In some embodiments that may include the above embodiments, there are multiple cells, and the first electrodes in the multiple cells are connected, and the second electrodes in the multiple cells are connected. So that the cells are connected in parallel, and the device structures in the cells are turned on and off at the same time. Through the above arrangement, the working current and power of the semiconductor structure can be further increased.

[0019] In some embodiments that may include the above embodiments, the device structure further includes a gate, which is stacked on the active region structure, the gate is located between the first electrode and the second electrode, and the gate is connected to the barrier layer; each gate in the plurality of cells is connected; the semiconductor structure further includes a third electrode, the plurality of cells are arranged around the third electrode, and each gate in the plurality of cells is connected to the third electrode. In this arrangement, the gate in each cell is connected to the third electrode, which can improve the voltage uniformity of the gate in each cell.

[0020] In some embodiments that may include the above embodiments, the device structure also includes a gate, which is stacked on the active area structure, the gate is located between the first electrode and the second electrode, and the gate is connected to the barrier layer; the width of the interface between the channel layer and the barrier layer gradually decreases from the first electrode to the gate along the direction perpendicular to the current. That is to say, the width of the interface corresponding to the gate is the smallest, and the width of the interface gradually increases from the gate to the first electrode. Through the above arrangement, in the implementation method of the current flowing from the first electrode to the second electrode, in the on state, the number of electrons at the interface near the first electrode is much larger than the interface near the gate. Under the action of the high electric field, the electrons converge to the interface near the gate, and the flow speed of the electrons gradually increases. The interface near the gate makes the flow speed of the electrons the largest, and can quickly reach the saturation drift speed, and then reach the saturation current, so as to reduce the knee voltage and improve the retreat efficiency of the semiconductor structure.

[0021] In some embodiments that may include the above embodiments, the width of the interface between the channel layer and the barrier layer along the direction perpendicular to the current gradually decreases from the second electrode to the gate. In other words, the width of the interface corresponding to the gate is the smallest, and the width of the interface gradually increases from the gate to the first electrode, and the width of the interface gradually increases from the gate to the second electrode. In this way, the first electrode and the second electrode can both have a large area to facilitate the connection between the first electrode and the second electrode and the radio frequency circuit.

[0022] In some embodiments that may include the above embodiments, there are multiple device structures, multiple device structures share the same gate, and multiple device structures are arranged around the gate; the first electrodes of the multiple device structures are connected, the second electrodes of the multiple device structures are connected, and the adjacent first electrodes and second electrodes are isolated by a first isolation structure. The first electrodes of the multiple device structures are connected, and the second electrodes of the multiple device structures are connected to achieve parallel connection of the device structures, and each device structure is turned on and turned off at the same time. Through the above arrangement, the operating current and power of the semiconductor structure can be increased. It can be understood that the number of device structures connected in parallel can be 2, 3, 4, 5, 6, etc., and the embodiments of the present application are not limited to this.

[0023] In some embodiments that may include the above embodiments, each first electrode is located on one side of the first isolation structure, and adjacent first electrodes are in contact; each second electrode is located on the other side of the isolation structure, and adjacent second electrodes are in contact. Through the above arrangement, the connection between the first electrodes is facilitated, and the connection between the second electrodes is also facilitated, so as to simplify the structural complexity of the semiconductor structure.

[0024] In some embodiments, which may include the above embodiments, the first electrodes and the second electrodes are alternately arranged around the gate.

[0025] In some embodiments that may include the above embodiments, the device structure further includes a second isolation structure, and the second isolation structure is used to reduce the width of the region in the active region structure through which the current flows in a direction perpendicular to the current flow. In this way, the electron flow speed can be further increased, so that the electrons can reach the saturation drift speed faster, and then reach the saturation current, further reducing the knee voltage, so as to further improve the fallback efficiency of the semiconductor structure.

[0026] In some embodiments that may include the above embodiments, the material of the second isolation structure includes P-type gallium nitride, the second isolation structure is stacked on the active area structure, and the second isolation structure is located between the first electrode and the second electrode. The second isolation structure including P-type gallium nitride can remove electrons on the channel layer of the corresponding area, so that no electrons flow through the interface covered by the second isolation structure, and correspondingly increases the electron flow rate at the interface near the second isolation structure. It can be understood that the projection on the interface of the second isolation structure extends inward from the edge of the interface perpendicular to the current direction, and the second isolation structure can be two, and the two second isolation structures are arranged oppositely, that is, the connection line of the two second isolation structures is perpendicular to the current direction. Such an arrangement further increases the electron flow rate.

[0027] In some embodiments that may include the above embodiments, a groove is provided on the channel layer and / or barrier layer corresponding to the interface, and the second isolation structure includes an insulating filler, and the insulating filler is filled in the groove. In this way, the insulating filler can reduce the width of the interface to increase the speed of electron flow. The groove can extend inward from the edge of the interface perpendicular to the direction of current. In some achievable methods, there can be two grooves, and the two grooves are arranged opposite to each other, that is, the line connecting the two grooves is perpendicular to the direction of current. In this way, the width of the interface can be further reduced and the speed of electron flow can be further increased.

[0028] In a second aspect, an embodiment of the present application further provides a radio frequency device, comprising: a radio frequency circuit and the semiconductor structure as described above, wherein the device structure is connected to the radio frequency circuit.

[0029] The radio frequency device provided in the embodiments of the present application includes the semiconductor structure in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0030] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a control device and the radio frequency device as described above, wherein the radio frequency device is connected to the control device.

[0031] The electronic device provided in the embodiments of the present application includes the semiconductor structure in any of the above embodiments, so the two can solve the same technical problems and achieve the same technical effects.

[0032] In a fourth aspect, an embodiment of the present application also provides a method for manufacturing a semiconductor structure, comprising: forming an active area structure on a substrate, the active area structure comprising a barrier layer and a channel layer that are stacked; along a direction parallel to the current, the width of an interface between the channel layer and the barrier layer gradually decreases along a direction perpendicular to the current direction; forming an electrode layer on the active area structure, the electrode layer comprising a first electrode and a second electrode that are spaced apart, and the first electrode and the second electrode are both connected to the barrier layer.

[0033] The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in the embodiment of the present application, the active area structure is arranged on the substrate, the active area structure includes a barrier layer and a channel layer arranged in a stacked manner, the electrode layer is stacked on the active area structure, the electrode includes a first electrode and a second electrode arranged in an interval, and the first electrode and the second electrode are both connected to the barrier layer; wherein, along the direction parallel to the current, the width of the interface between the channel layer and the barrier layer along the direction perpendicular to the current gradually decreases, and in the on state, the flow speed of electrons gradually increases with the decrease in the width of the interface, thereby enabling the electrons to reach the saturation drift speed faster, and then reach the saturation current, thereby reducing the knee voltage, improving the back-off efficiency of the semiconductor structure, and thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A cross-sectional view of a semiconductor structure provided in an embodiment of the present application;

[0035] Figure 2 A top view of a semiconductor structure provided in an embodiment of the present application Figure 1 ;

[0036] Figure 3 is a cross-sectional view of a semiconductor structure in the related art;

[0037] Figure 4 is a curve diagram of the distance between the first electrode and the second electrode and the knee voltage in the related art;

[0038] Figure 5 is a curve diagram of the electric field of the active layer of the semiconductor structure and the distance between the first electrode and the second electrode;

[0039] Figure 6 A top view of a semiconductor structure provided in an embodiment of the present application Figure 2 ;

[0040] Figure 7 A schematic diagram of a structure in which multiple device structures constitute a unit cell in an embodiment of the present application Figure 1 ;

[0041] Figure 8 A schematic diagram of a structure in which multiple device structures constitute a unit cell in an embodiment of the present application Figure 2 ;

[0042] Fig. 9 Schematic diagram of the connection of multiple cells in the embodiment of the present application Figure 1 ;

[0043] Fig.10 Schematic diagram of the connection of multiple cells in the embodiment of the present application Figure 2 ;

[0044] Fig.11 Schematic diagram of the connection of multiple cells in the embodiment of the present application Figure 3 ;

[0045] Fig.12 A top view of a semiconductor structure provided in an embodiment of the present application Figure 3 ;

[0046] Fig.13 Schematic diagram of a structure in which multiple device structures are arranged around a gate in an embodiment of the present application Figure 1 ;

[0047] Fig.14 Schematic diagram of a structure in which multiple device structures are arranged around a gate in an embodiment of the present application Figure 2 .

[0048] Description of reference numerals:

[0049] 101: substrate; 102: nucleation layer; 103: buffer layer; 104: back plate; 105: back hole; 201: active area structure; 202: barrier layer; 203: channel layer; 204: interface; 301: electrode layer; 302: first electrode; 303: second electrode; 401: passivation layer; 402: first passivation layer; 403: second passivation layer; 404: third passivation layer; 405: field plate; 501: gate; 502: gate body; 503: gate contact; 601: second isolation structure; 701: third electrode; 702: opening; 703: connection part; 801: first isolation structure. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0051] In the following, the terms "first", "second", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features.

[0052] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left", "right", "horizontal" and "vertical" are defined relative to the orientation of the components schematically placed in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they may change accordingly according to changes in the orientation of the components placed in the drawings.

[0053] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, a coupling connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a communication between two components. For those skilled in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0054] The embodiment of the present application provides an electronic device, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, etc. The embodiment of the present application does not limit the electronic device. In the embodiment of the present application, the electronic device includes a control device and a radio frequency device, and the control device and the radio frequency device are electrically connected. The radio frequency device can be connected to an antenna and send a radio frequency signal to the antenna under the control of the control device, thereby realizing communication between the electronic device and an external device (such as a communication base station, a communication satellite, etc.). The control device can be a controller of the electronic device, such as a central processing unit, etc.

[0055] The radio frequency device includes a radio frequency circuit and a semiconductor structure connected to the radio frequency circuit, and the semiconductor structure is electrically connected to the control device through the radio frequency circuit to achieve connection between the radio frequency device and the control device. Exemplarily, the radio frequency device may also include a radio frequency circuit board, on which the radio frequency circuit is arranged, and the semiconductor structure may be a radio frequency chip, which is arranged on the radio frequency circuit board and connected to the radio frequency circuit.

[0056] Please refer to Figure 1 In the embodiment of the present application, the semiconductor structure includes a substrate 101 and a device structure disposed on the substrate 101. The substrate 101 is the basis of the semiconductor structure and can support other structures and film layers. The material of the substrate 101 can include silicon (Si), sapphire, gallium nitride (GaN), etc. The embodiment of the present application does not limit the material of the substrate 101. The device structure is disposed on the substrate 101, and the device structure can include a transistor. For example, the transistor can include a high electron mobility transistor (HEMT).

[0057] The device structure includes an active region structure 201, and the active region structure 201 is arranged on a substrate 101. The active region structure 201 includes a barrier layer 202 and a channel layer 203 that are stacked. Exemplarily, the channel layer 203 can be arranged between the barrier layer 202 and the substrate 101, and the channel layer 203 is in contact with the barrier layer 202. The projections of the barrier layer 202 and the channel layer 203 on the substrate 101 at least partially overlap, that is, there is an interface 204 between the barrier layer 202 and the channel layer 203, and the interface 204 can be a surface where the barrier layer 202 and the channel layer 203 contact each other, and the interface 204 can allow current to pass through. Among them, the material of the barrier layer 202 can include aluminum gallium nitride (AlGaN) and the like, and the material of the channel layer 203 can include gallium nitride (GaN) and the like. The embodiment of the present application does not limit the materials of the barrier layer 202 and the channel layer 203. In some implementations, a nucleation layer 102 and a buffer layer 103 are stacked between the substrate 101 and the active region structure 201 , and the nucleation layer 102 may be located between the buffer layer 103 and the substrate 101 .

[0058] In the above implementation, the semiconductor structure further includes an electrode layer 301, which is stacked on the active region structure 201, that is, the electrode layer 301 is stacked on the side of the active region structure 201 away from the substrate 101; the electrode layer 301 includes a first electrode 302 and a second electrode 303 which are spaced apart, and the first electrode 302 and the second electrode 303 are both connected to the barrier layer 202. It can be understood that the first electrode 302 can be the source of the transistor, and the corresponding second electrode 303 is the drain of the transistor; or the first electrode 302 can be the drain of the transistor, and the corresponding second electrode 303 is the source of the transistor, and the embodiment of the present application does not limit the first electrode 302 and the second electrode 303.

[0059] Continue to refer to Figure 1 In the implementation mode where the first electrode 302 includes a source electrode, the semiconductor structure further includes a back plate 104, which is stacked and arranged on the side of the substrate 101 away from the active area structure 201. The material of the back plate 104 may include titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), titanium nitride (TiN), etc. A back hole 105 is arranged on the substrate 101, and the back hole 105 extends to the first electrode 302, and the bottom of the back hole 105 is in contact with the first electrode 302. A conductive layer is arranged on the side wall and the bottom of the back hole 105, and the conductive layer is in contact with the first electrode 302 and the back plate 104, so as to realize the connection between the back plate 104 and the first electrode 302. Exemplarily, the back plate 104 and the conductive layer can be an integral structure, that is, the back plate 104 and the conductive layer are formed simultaneously by the same process, which can reduce the difficulty of manufacturing the semiconductor structure.

[0060] In some embodiments, at least a portion of the first electrode 302 contacts the surface of the barrier layer 202 facing away from the substrate 101, and at least a portion of the second electrode 303 contacts the surface of the barrier layer 202 facing away from the substrate 101, so as to achieve connection between the first electrode 302 and the second electrode 303 and the barrier layer 202. Of course, in other implementations, the first electrode 302 and the second electrode 303 may also be connected to the barrier layer 202 through other conductive structures.

[0061] In the implementation mode where the first electrode 302 and the second electrode 303 are in contact with the barrier layer 202, a passivation layer 401 may be provided between the first electrode 302 and the second electrode 303, and the passivation layer 401 may implement insulation between the first electrode 302 and the second electrode 303 to prevent a short circuit. Exemplarily, the material of the passivation layer 401 may include insulating materials such as silicon oxide and silicon nitride.

[0062] In the above implementation, the material of the first electrode 302 and the second electrode 303 may include titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), titanium nitride (TiN), etc. The material of the first electrode 302 and the second electrode 303 may be the same, the first electrode 302 and the second electrode 303 may be arranged in the same layer, and the first electrode 302 and the second electrode 303 may be formed at the same time to reduce the difficulty of manufacturing the semiconductor structure; of course, the material of the first electrode 302 and the second electrode 303 may also be different, and the embodiment of the present application is not limited to this.

[0063] Continue to refer to Figure 1 In the embodiment of the present application, the semiconductor structure further includes a gate 501, which is stacked and arranged on the side of the active region structure 201 away from the substrate 101. The gate 501 is connected to the barrier layer 202. Through the gate 501, the first electrode 302 and the second electrode 303 can be controlled to be conductive or not, thereby realizing the conduction and cutoff of the transistor. It can be understood that in the implementation mode in which the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 at least partially overlap, the first electrode 302, the second electrode 303 and the gate 501 can all be connected to the barrier layer 202 corresponding to the interface 204.

[0064] In the above implementation, the material of the gate 501 may include titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), titanium nitride (TiN), etc. The material of the gate 501 may be the same as the material of the first electrode 302 and the second electrode 303. Accordingly, the gate 501, the first electrode 302 and the second electrode 303 may be arranged in the same layer, and the gate 501, the first electrode 302 and the second electrode 303 may be formed at the same time to reduce the difficulty of manufacturing the semiconductor structure. Of course, the materials of the gate 501 and the first electrode 302 and the second electrode 303 may also be different, and the embodiment of the present application does not limit this.

[0065] In some embodiments, the passivation layer 401 includes a first passivation layer 402 and a second passivation layer 403 which are stacked, the first passivation layer 402 is located between the second passivation layer 403 and the barrier layer 202, the gate 501 includes a gate body 502 and a gate contact 503, the gate contact 503 is located in the second passivation layer 403, the gate body 502 is located in the first passivation layer 402, the gate contact 503 is in contact with both the barrier layer 202 and the gate body 502, and the gate body 502 is connected to the barrier layer 202 through the gate contact 503.

[0066] Continue to refer to Figure 1 In the embodiment of the present application, the semiconductor structure further includes a third passivation layer 404, which covers the gate body 502 and the electrode layer 301 to protect the gate 501, the first electrode 302, and the second electrode 303. In some implementations, the semiconductor structure further includes a field plate 405, the projection of the field plate 405 on the substrate 101 covers part of the gate 501 and the projection of the interface 204 between the gate 501 and the second electrode 303, and the material of the field plate 405 may include titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), titanium nitride (TiN), etc. The field plate 405 can adjust the electric field of the interface 204 between the gate 501 and the second electrode 303. Exemplarily, the field plate 405 can be disposed in the third passivation layer 404 to protect the field plate 405.

[0067] Please refer to Figure 2 , in the embodiment of the present application, along the direction parallel to the current, Figure 1 The width of the interface 204 between the barrier layer 202 and the channel layer 203 is gradually reduced along the direction perpendicular to the current flow. Figure 2Taking the orientation shown as an example, the current direction can be the X direction, and the direction parallel to the current is the direction parallel to the X direction. In the implementation mode in which the first electrode 302 and the second electrode 303 are both in contact with the barrier layer 202, the current direction is parallel to the line connecting the first electrode 302 and the second electrode 303. The direction perpendicular to the current can be the Y direction, and in the implementation mode in which the first electrode 302 and the second electrode 303 are both in contact with the barrier layer 202, the direction perpendicular to the current is perpendicular to the line connecting the first electrode 302 and the second electrode 303. By gradually reducing the width of the interface 204 along the direction parallel to the current, in the on state, the flow speed of the electrons gradually increases as the width of the interface 204 decreases, thereby enabling the electrons to reach the saturation drift speed faster, and then reach the saturation current, thereby reducing the knee voltage and improving the back-off efficiency of the semiconductor structure.

[0068] It can be understood that the fallback efficiency and knee voltage satisfy the following formula:

[0069]

[0070] Where η is the fallback efficiency, R L , Z L are load impedance, V DD is the reference voltage, V knee is the knee voltage. From the above formula, we can see that the back-off efficiency increases as the knee voltage decreases.

[0071] It can be understood that the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 at least partially overlap. In some implementations, the projection of part of the barrier layer 202 on the substrate 101 coincides with the projection of part of the channel layer 203 on the substrate 101, that is, part of the barrier layer 202 and part of the channel layer 203 contact and form an interface 204, and the width of the interface 204 gradually decreases along the direction parallel to the current. In other implementations, the projection of the barrier layer 202 on the substrate 101 is located within the projection of the channel layer 203 on the substrate 101, and accordingly, the surface of the barrier layer 202 facing the channel layer 203 is in contact with the channel layer 203 to form the interface 204. In other implementations, the projection of the channel layer 203 on the substrate 101 is located within the projection of the barrier layer 202 on the substrate 101, and accordingly, the surface of the channel layer 203 facing the barrier layer 202 is in contact with the barrier layer 202 to form the interface 204. In other implementations, the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 completely overlap, that is, the surface of the barrier layer 202 facing the channel layer 203 is completely in contact with the surface of the channel layer 203 facing the barrier layer 202 to form an interface 204 .

[0072] In the implementation method in which the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 completely overlap, the space occupied by the channel layer 203 and the barrier layer 202 can be reduced, thereby reducing the volume of the device structure and further reducing the volume of the semiconductor structure; on the other hand, since the volume of the device structure is smaller, more device structures can be arranged in the semiconductor structure of the same volume, thereby improving the arrangement density of the device structure.

[0073] Continue to refer to Figure 1 and Figure 2 In the semiconductor structure provided by the embodiment of the present application, an active area structure 201 is arranged on a substrate 101, and the active area structure 201 includes a barrier layer 202 and a channel layer 203 that are stacked, and an electrode layer 301 is stacked on the active area structure 201, and the electrode includes a first electrode 302 and a second electrode 303 that are spaced apart, and the first electrode 302 and the second electrode 303 are both connected to the barrier layer 202; wherein, along a direction parallel to the current, the width of an interface 204 between the channel layer 203 and the barrier layer 202 along a direction perpendicular to the current gradually decreases, and in a conducting state, the flow velocity of electrons gradually increases with the decrease in the width of the interface 204, thereby enabling the electrons to reach a saturation drift velocity faster, and then reach a saturation current, thereby reducing the knee voltage, improving the back-off efficiency of the semiconductor structure, and thereby improving the performance of the semiconductor structure.

[0074] In related technologies, such as Figure 3 The semiconductor structure shown includes a substrate 101, an active region structure 201 stacked on the substrate 101, the active region structure 201 includes a barrier layer 202 and a channel layer 203 stacked, and the semiconductor structure also includes a first electrode 302, a second electrode 303 and a gate 501, the first electrode 302, the second electrode 303 and the gate 501 are all arranged on the side of the active region structure 201 away from the substrate 101, the first electrode 302 and the second electrode 303 are arranged at intervals, and the electrodes and the second electrode 303 are both connected to the barrier layer 202, the gate 501 is arranged between the first electrode 302 and the second electrode 303, and is connected to the barrier layer 202 between the first electrode 302 and the second electrode 303, and the back-off efficiency of the semiconductor structure can be adjusted by adjusting the distance LDS between the first electrode 302 and the second electrode 303. Figure 4As shown, the knee voltage Vknee gradually decreases as the distance LDS between the first electrode 302 and the second electrode 303 gradually decreases (the distance between the first electrode 302 and the second electrode 303 decreases from about 6.5μm to about 2μm, and correspondingly, the knee voltage decreases from about 6V to about 3V), and the back-off efficiency gradually increases as the distance between the first electrode 302 and the second electrode 303 gradually decreases. Therefore, the back-off efficiency of the semiconductor structure can be improved by reducing the distance LDS between the first electrode 302 and the second electrode 303. However, reducing the distance LDS between the first electrode 302 and the second electrode 303 will cause the withstand voltage characteristics of the semiconductor structure to deteriorate; in addition, the small distance LDS between the first electrode 302 and the second electrode 303 also increases the difficulty of manufacturing, resulting in a decrease in the yield rate, and also reduces the heat dissipation performance of the semiconductor structure.

[0075] The semiconductor structure in the embodiment of the present application, such as Figure 1 and Figure 2 As shown, the retreat efficiency of the semiconductor structure is improved by gradually reducing the width of the interface 204 between the channel layer 203 and the barrier layer 202 in a direction parallel to the current. Compared with the above-mentioned related technologies, there is no need to change the distance between the first electrode 302 and the second electrode 303, which reduces the manufacturing difficulty, improves the yield rate, and also improves the heat dissipation performance.

[0076] In the embodiment of the present application, the interface 204 can have a variety of shapes, as long as the width of the interface 204 is gradually reduced in a direction parallel to the current. The following will be introduced in multiple scenarios:

[0077] Scene 1

[0078] Continue to refer to Figure 1 and Figure 2 In this scenario, the first electrode 302 and the second electrode 303 can both contact the barrier layer 202. Accordingly, the width of the interface 204 between the first electrode 302 and the second electrode 303, the channel layer 203 and the barrier layer 202 is gradually reduced along the direction perpendicular to the current; that is, the width of the barrier layer 202 between the second electrode 303 and the substrate 101 is smaller than the width of the barrier layer 202 between the first electrode 302 and the substrate 101, and the width of the barrier layer 202 between the second electrode 303 and the substrate 101 is the smallest. In this way, in the on state, the number of electrons at the interface 204 near the first electrode 302 is much larger than that at the interface 204 near the second electrode 303. Under the action of a high electric field, the electrons converge to the interface 204 near the second electrode 303, and the flow speed of the electrons gradually increases, so that the electrons can quickly reach the saturation drift speed, and then reach the saturation current, thereby reducing the knee voltage and improving the back-off efficiency of the semiconductor structure.

[0079] In this scenario, the projection of the interface 204 on the substrate 101 may be a triangle (eg Figure 2 As shown), trapezoid and other regular shapes, of course, the projection of the interface 204 on the substrate 101 may also be other irregular shapes, and the embodiments of the present application are not limited to this, as long as the width of the barrier layer 202 between the second electrode 303 and the substrate 101 is smaller than the width of the barrier layer 202 between the first electrode 302 and the substrate 101, and the width of the interface 204 gradually decreases from the first electrode 302 to the second electrode 303.

[0080] like Figure 2 As shown, in the implementation method in which the projection of the interface 204 on the substrate 101 is triangular, the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 can completely overlap, that is, the projections of the barrier layer 202 and the channel layer 203 on the substrate 101 are both triangular and completely overlap; accordingly, the first electrode 302 can be connected to the barrier layer 202 corresponding to the preset side m of the triangle. Exemplarily, the first electrode 302 can cover the preset side m and part of the barrier layer 202 near the preset side m, and the first electrode 302 is in contact with the barrier layer 202 to achieve connection between the first electrode 302 and the barrier layer 202. The triangle has a preset vertex n corresponding to the preset side m, the preset vertex n is the intersection of two sides of the triangle except the preset side m, and the second electrode 303 is connected to the barrier layer 202 corresponding to the preset vertex n; wherein the second electrode 303 can cover the preset vertex n and part of the barrier layer 202 near the preset vertex n, and the second electrode 303 is in contact with the barrier layer 202 to achieve the connection between the second electrode 303 and the barrier layer 202. Through the above arrangement, the projection of the interface 204 on the substrate 101 is triangular, and the shape of the interface 204 is relatively regular, which reduces the difficulty of manufacturing the semiconductor structure.

[0081] It can be understood that the shortest line between the preset vertex n and the preset side m is parallel to the current direction, so that the width of the interface 204 gradually decreases from the first electrode 302 to the second electrode 303 .

[0082] Continue to refer to Figure 1 and Figure 2 In this scenario, the gate 501 is located between the first electrode 302 and the second electrode 303. In the projection on the substrate 101, the projection of the gate 501 covers at least part of the projection of the interface 204, so that the first electrode 302 and the second electrode 303 can be controlled to be turned on or off by the gate 501. In some embodiments, the projection of the gate 501 can be located within the projection of the interface 204, and the projection of the gate 501 can contact both sides outside the preset side m to increase the area of ​​the gate 501, thereby improving the control ability of the gate 501.

[0083] Figure 5 is a curve diagram of the electric field strength E (unit: MV / cm megavolt per centimeter) of the channel layer 203 and the distance LDS between the first electrode 302 and the second electrode 303. The solid line in the figure is a curve between E and LDS of the semiconductor structure in the embodiment of the present application, and the dotted line is Figure 3 The curve between E and LDS in the related art is shown. Figure 5 It can be seen that Figure 3 Compared with the related art shown in the figure, as the distance between the first electrode 302 and the second electrode 303 increases, the electric field of the channel layer 203 of the semiconductor structure in the embodiment of the present application increases significantly, thereby improving the performance of the semiconductor structure.

[0084] Please refer to Figure 6 In some embodiments, the device structure further includes a second isolation structure 601, which is used to reduce Figure 1 The width of the region for current flow in the active region structure 201 is perpendicular to the current direction. Such a configuration can further increase the electron flow speed, so that the electrons can reach the saturation drift speed faster, and then reach the saturation current, further reducing the knee voltage, so as to further improve the retreat efficiency of the semiconductor structure.

[0085] In some implementations, a groove is provided on the channel layer 203 and / or the barrier layer 202 corresponding to the interface 204, and the first isolation structure 801 includes an insulating filler, which is filled in the groove. In this way, the insulating filler can reduce the width of the interface 204 to increase the electron flow speed. Exemplarily, the material of the insulating filler can include silicon oxide, silicon nitride, etc.

[0086] It can be understood that the groove can extend inward from the edge of the interface 204 perpendicular to the current direction. In some practicable ways, there can be two grooves, which are arranged opposite to each other, that is, the line connecting the two grooves is perpendicular to the current direction. Such an arrangement can further reduce the width of the interface 204 and further increase the electron flow speed.

[0087] In other implementations, the material of the second isolation structure 601 includes P-type gallium nitride (P-GaN), and the second isolation structure 601 is stacked and arranged on Figure 1The active region structure 201 is shown, and the second isolation structure 601 is located between the first electrode 302 and the second electrode 303. The second isolation structure 601 including P-type gallium nitride can remove electrons on the channel layer 203 in the corresponding area, so that no electrons flow through the interface 204 covered by the second isolation structure 601, and the electron flow speed of the interface 204 near the second isolation structure 601 is correspondingly increased. It can be understood that the projection of the second isolation structure 601 on the interface 204 extends inward from the edge of the interface 204 perpendicular to the current direction. The second isolation structure 601 can be two, and the two second isolation structures 601 are arranged oppositely, that is, the connection line of the two second isolation structures 601 is perpendicular to the current direction. Such an arrangement further increases the electron flow speed.

[0088] like Figure 7 As shown, in this scenario, there may be multiple device structures, and the multiple device structures are arranged around the preset center A; that is, the multiple device structures are arranged around the preset center A on the substrate 101. Such an arrangement improves the layout rationality of the device structure, thereby increasing the density of the device.

[0089] In some implementations, the second electrode 303 of each device structure is disposed close to a preset center, and correspondingly, the first electrode 302 of each device structure is disposed away from the preset center. Such an arrangement can further improve the rationality of the layout of the device structure.

[0090] like Figure 7 As shown, in some embodiments, adjacent device structures can be arranged at intervals, that is, the first electrodes 302 of each device structure are arranged at intervals, the second electrodes 303 of each device structure are arranged at intervals, the gates 501 of each device structure are arranged at intervals, and the interfaces 204 of each device structure are arranged at intervals; accordingly, each device structure can be turned on and off individually through the corresponding gate 501.

[0091] In the implementation manner where the interface 204 is triangular, each second electrode 303 is disposed close to the preset center, and correspondingly, each preset vertex n can be disposed close to the preset center. In some implementation manners, each triangle is an equilateral triangle, and there can be 6 device structures, which form a regular hexagonal structure; of course, this scenario does not limit the number of device structures, and the number of device structures can also be 2, 3, etc.

[0092] like Figure 8As shown, in some embodiments, the first electrodes 302 of each device structure are connected, the second electrodes 303 of each device structure are connected, and the gates 501 of each device structure are connected, so that each device structure forms a cell, that is, each device structure is connected in parallel, and each device structure in the cell is turned on and off at the same time. Through the above arrangement, the operating current and power of the semiconductor structure can be increased to further improve the performance of the semiconductor structure.

[0093] In the implementation in which the interface 204 is triangular, each preset vertex n can coincide with the preset center to achieve connection between each second electrode 303; the gates 501 of adjacent device structures are in contact to achieve connection between each gate 501; the first electrodes 302 of adjacent device structures are in contact to achieve connection between each first electrode 302.

[0094] In some implementations, each triangle is an equilateral triangle, and there may be 6 device structures, which form a regular hexagonal cell. Of course, this scenario does not limit the number of device structures, and the number of device structures may also be 2, 3, etc., and the corresponding cells may also have other shapes.

[0095] like Fig. 9 As shown, in some embodiments, there may be multiple cells, and the first electrodes 302 in the multiple cells are connected, the second electrodes 303 in the multiple cells are connected, and the gates 501 in the multiple cells are connected, so that the cells are connected in parallel, and the device structures in the cells are turned on and off at the same time. Through the above arrangement, the working current and power of the semiconductor structure can be further increased.

[0096] It is understandable that the number of cells may be 2, 3, 4, etc., and this embodiment does not limit the number of cells.

[0097] In the above implementation, since the first electrodes 302 are arranged away from the preset center, the first electrodes 302 in adjacent cells can be in contact to achieve connection between the first electrodes 302. Exemplarily, the gates 501 in adjacent cells can be connected through a first auxiliary circuit to achieve connection between the gates 501. The second electrodes 303 in adjacent cells can be connected through a second auxiliary circuit to achieve connection between the second electrodes 303.

[0098] It is understood that the semiconductor structure may include a first metal layer, and the first auxiliary circuit and the second auxiliary circuit may be obtained by patterning the first metal layer. The first auxiliary circuit may be connected to each gate 501 in an adjacent cell through a first conductive hole, and the second auxiliary circuit may be connected to each second electrode 303 in an adjacent cell through a second conductive hole. The first metal layer may be provided at Figure 1The substrate 101 is shown on a side away from the active region structure 201 , or the first metal layer is disposed on a side of the electrode layer 301 away from the substrate 101 . The embodiment of the present application does not limit the position of the first metal layer.

[0099] like Fig.10 As shown, in some embodiments, the semiconductor structure further includes a third electrode 701, a plurality of cells are arranged around the third electrode 701, and each gate 501 in the plurality of cells is connected to the third electrode 701. In this arrangement, the gate 501 in each cell is connected to the third electrode 701, which can improve the voltage uniformity of the gate 501 in each cell.

[0100] In the implementation mode in which the cells are regular hexagonal, every six cells are connected in parallel, and the six cells are arranged around the third electrode 701 to form a substantially hexagonal structure. In some implementation modes, the first electrode 302 of the device structure close to the third electrode 701 in each cell forms an opening 702, or the first electrode 302 is removed to form the opening 702, and a connecting portion 703 is formed in the opening 702, one end of the connecting portion 703 is connected to the gate 501 of the device structure close to the third electrode 701 in the cell, and the other end of the connecting portion 703 is connected to the third electrode 701 to achieve the connection between each gate 501 in the cell and the third electrode 701. Of course, in other implementation modes, the gate 501 of the device structure close to the third electrode 701 in each cell is connected to the third electrode 701 through the connecting portion 703, and the connecting portion 703 is stacked and arranged on the side of the electrode layer 301 away from the substrate 101.

[0101] like Fig.11 As shown, in other embodiments, the width of the barrier layer 202 between the second electrode 303 and the substrate 101 is greater than the width of the barrier layer 202 between the first electrode 302 and the substrate 101, and the width of the barrier layer 202 between the first electrode 302 and the substrate 101 is the smallest. With such a configuration, in the on state, the number of electrons at the interface 204 near the second electrode 303 is much greater than the number of electrons at the interface 204 near the first electrode 302, and under the action of a high electric field, the electrons converge toward the interface 204 near the first electrode 302, and the flow speed of the electrons gradually increases, so that the electrons can quickly reach the saturation drift speed, and then reach the saturation current, thereby reducing the knee voltage and improving the back-off efficiency of the semiconductor structure.

[0102] In an implementation with multiple device structures, the multiple device structures are arranged around a preset center, and accordingly, the first electrode 302 of each device structure is arranged close to the preset center, and accordingly, the second electrode 303 of each device structure is arranged away from the preset center.

[0103] Scene 2

[0104] Please refer to Fig.12 The difference between this scenario and scenario 1 is that the gate 501 is located between the first electrode 302 and the second electrode 303. Figure 1 The width of the interface 204 between the channel layer 203 and the barrier layer 202 along the direction perpendicular to the current gradually decreases from the first electrode 302 to the gate 501, that is, the width of the interface 204 corresponding to the gate 501 is the smallest, and the width of the interface 204 gradually increases from the gate 501 to the first electrode 302. Through the above arrangement, in the implementation mode in which the current flows from the first electrode 302 to the second electrode 303, in the on state, the number of electrons at the interface 204 near the first electrode 302 is much greater than that at the interface 204 near the gate 501. Under the action of the high electric field, the electrons converge to the interface 204 near the gate 501, and the flow speed of the electrons gradually increases. The interface 204 near the gate 501 makes the flow speed of the electrons the largest, and can quickly reach the saturation drift speed, and then reach the saturation current, so as to reduce the knee voltage and improve the back-off efficiency of the semiconductor structure.

[0105] In some implementations, the width of the interface 204 between the channel layer 203 and the barrier layer 202 along the direction perpendicular to the current gradually decreases from the second electrode 303 to the gate 501, that is, the width of the interface 204 corresponding to the gate 501 is the smallest, and the width of the interface 204 gradually increases from the gate 501 to the first electrode 302, and the width of the interface 204 gradually increases from the gate 501 to the second electrode 303. In this way, the first electrode 302 and the second electrode 303 can both have a large area, so as to facilitate the connection between the first electrode 302 and the second electrode 303 and the radio frequency circuit.

[0106] In the above implementation, the partial interface 204 between the gate 501 and the first electrode 302 may be in a first trapezoidal shape, and the partial interface 204 between the gate 501 and the second electrode 303 may be in a second trapezoidal shape, and the smaller bottom sides of the first trapezoidal shape and the second trapezoidal shape correspond to and are connected to the gate 501, so that the width of the interface 204 corresponding to the gate 501 is minimized. The embodiment of the present application does not limit the shapes of the partial interface 204 between the gate 501 and the first electrode 302, and the partial interface 204 between the gate 501 and the second electrode 303.

[0107] Please refer to Fig.13 In this scenario, there are multiple device structures, and the multiple device structures share the same gate 501, that is, the gates 501 of the multiple device structures are the same gate 501. The multiple device structures are arranged around the gate 501, that is, the active region structure 201 (such as Figure 1) is arranged around the gate 501, the first electrode 302 in each device structure is arranged around the gate 501, and the second electrode 303 in each device structure is arranged around the gate 501. It can be understood that the active area structure 201 in each device structure can be an integrated structure, or the active area structures 201 in each device structure can be arranged at intervals.

[0108] In the above implementation, the first electrodes 302 of the plurality of device structures are connected, and the second electrodes 303 of the plurality of device structures are connected to realize the parallel connection of the device structures, and the device structures are turned on and off at the same time. Through the above arrangement, the operating current and power of the semiconductor structure can be increased. It is understandable that the number of device structures connected in parallel can be 2, 3, 4, 5, 6, etc., and the embodiment of the present application does not limit this.

[0109] In this scenario, the adjacent first electrode 302 and the second electrode 303 are isolated by the first isolation structure 801 to avoid short circuit between the first electrode 302 and the second electrode 303. It is understandable that the material of the first isolation structure 801 may include silicon oxide, silicon nitride, etc., and the isolation structure may be provided in the same layer as the electrode layer 301.

[0110] Continue to refer to Fig.13 In some embodiments, each first electrode 302 is located on one side of the first isolation structure 801, and adjacent first electrodes 302 are in contact with each other to achieve connection between each first electrode 302; each second electrode 303 is located on the other side of the isolation structure, and adjacent second electrodes 303 are in contact with each other to achieve connection between each second electrode 303. Through the above arrangement, the connection between each first electrode 302 is facilitated, and the connection between each second electrode 303 is also facilitated, so as to simplify the structural complexity of the semiconductor structure.

[0111] In an implementation in which a portion of the interface 204 between the gate 501 and the first electrode 302 may be in a first trapezoidal shape, and a portion of the interface 204 between the gate 501 and the second electrode 303 may be in a second trapezoidal shape, the number of device structures connected in parallel may be three, and the three device structures may form a regular hexagonal shape, wherein the first electrodes 302 of the three device structures are located on one side of the isolation structure, and the second electrodes 303 of the three device structures are located on the other side of the isolation structure.

[0112] Please refer to Fig.14 In the embodiment thereof, each first electrode 302 and each second electrode 303 are alternately arranged around the gate 501, that is, in the direction around the gate 501, a plurality of first electrodes 302 and a plurality of second electrodes 303 are alternately arranged. Accordingly, a first isolation structure 801 is arranged between each adjacent first electrode 302 and second electrode 303 to prevent a short circuit between the first electrode 302 and the second electrode 303.

[0113] It can be understood that, due to the alternating arrangement of multiple first electrodes 302 and multiple second electrodes 303, each first electrode 302 can be connected through a third auxiliary circuit to achieve connection between each first electrode 302; each second electrode 303 can be connected through a fourth auxiliary circuit to achieve connection between each second electrode 303.

[0114] It can be understood that the semiconductor structure may include a second metal layer, and the third auxiliary circuit and the fourth auxiliary circuit may be obtained by patterning the second metal layer, and the third auxiliary circuit may be connected to each first electrode 302 through a third conductive hole, and the fourth auxiliary circuit may be connected to each second electrode 303 through a fourth conductive hole. The second metal layer may be disposed on a side of the substrate 101 away from the active region structure 201, or the second metal layer may be disposed on a side of the electrode layer 301 away from the substrate 101, and the embodiment of the present application does not limit the position of the second metal layer.

[0115] In the implementation mode where the portion of the interface 204 between the gate 501 and the first electrode 302 is in a first trapezoidal shape, and the portion of the interface 204 between the gate 501 and the second electrode 303 is in a second trapezoidal shape, the number of device structures connected in parallel can be 3, and the 3 device structures form a regular hexagonal shape. Accordingly, each first isolation structure 801 can extend toward the substrate 101, and the first isolation structure 801 can extend to the barrier layer 202 or the channel layer 203, so as to separate adjacent interfaces 204 through the first isolation structure 801.

[0116] The present application also provides a method for manufacturing a semiconductor structure, which can be used to manufacture the semiconductor structure in the above embodiment. The method for manufacturing a semiconductor structure includes:

[0117] S101: forming an active region structure on a substrate, the active region structure comprising a barrier layer and a channel layer stacked in a direction parallel to the current, and a width of an interface between the channel layer and the barrier layer gradually decreases along a direction perpendicular to the current direction.

[0118] like Figure 1 As shown, in the embodiment of the present application, the stacked barrier layer 202 and the channel can be formed by deposition or evaporation, wherein the channel layer 203 can be located between the barrier layer 202 and the substrate 101, and the barrier layer 202 is in contact with the channel layer 203.

[0119] In some implementations, after the channel layer 203 is formed, part of the channel layer 203 can be removed by etching or the like, so that the width of the remaining channel layer 203 along the direction parallel to the current gradually decreases; then the barrier layer 202 is formed, and the barrier layer 202 covers the remaining channel layer 203; that is, the projection of the remaining channel layer 203 on the substrate 101 is located within the projection of the barrier layer 202 on the substrate 101, and at this time, the width of the interface 204 between the barrier layer 202 and the channel layer 203 along the direction parallel to the current gradually decreases.

[0120] In other implementations, the channel layer 203 is formed first, and then the barrier layer 202 is formed on the channel layer 203. Then, part of the barrier layer 202 is removed by etching or the like, so that the width of the remaining barrier layer 202 in a direction parallel to the current gradually decreases, thereby gradually reducing the width of the interface 204 between the barrier layer 202 and the channel layer 203 in a direction parallel to the current.

[0121] In other implementations, after forming the channel layer 203, part of the channel layer 203 may be removed by etching or the like, so that the width of the remaining part of the channel layer 203 along the direction parallel to the current gradually decreases; then the barrier layer 202 is formed, and part of the barrier layer 202 is removed by etching or the like, so that the width of the remaining part of the barrier layer 202 along the direction parallel to the current gradually decreases; and the projections of the remaining part of the barrier layer 202 and the remaining part of the channel layer 203 on the substrate 101 completely overlap, so that the width of the interface 204 between the barrier layer 202 and the channel layer 203 along the direction parallel to the current gradually decreases.

[0122] After forming the active region structure 201, the semiconductor structure manufacturing method provided in the embodiment of the present application further includes:

[0123] S102: forming an electrode layer on the active area structure, wherein the electrode layer comprises a first electrode and a second electrode which are spaced apart from each other, and both the first electrode and the second electrode are connected to the barrier layer.

[0124] For example, an electrode metal layer may be formed on the barrier layer 202 by deposition or evaporation, and then a portion of the electrode metal layer may be removed by etching, thereby forming the electrode layer 301 including the first electrode 302 and the second electrode 303 .

[0125] Continue to refer to Figure 1 and Figure 2The semiconductor structure manufactured by the semiconductor structure manufacturing method provided in the embodiment of the present application comprises an active area structure 201 arranged on a substrate 101, the active area structure 201 comprises a barrier layer 202 and a channel layer 203 which are stacked, an electrode layer 301 is stacked on the active area structure 201, the electrode comprises a first electrode 302 and a second electrode 303 which are spaced apart, and the first electrode 302 and the second electrode 303 are both connected to the barrier layer 202; wherein, along a direction parallel to the current, a width of an interface 204 between the channel layer 203 and the barrier layer 202 along a direction perpendicular to the current gradually decreases, and in a conducting state, a flow velocity of electrons gradually increases with a decrease in the width of the interface 204, thereby enabling the electrons to reach a saturation drift velocity faster, and then reach a saturation current, thereby reducing a knee voltage, and improving a back-off efficiency of the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0126] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0127] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A device structure, wherein the device structure is arranged on the substrate, and the device structure comprises: An active region structure, the active region structure comprising a barrier layer and a channel layer stacked together; Along the direction parallel to the current, the width of the interface between the channel layer and the barrier layer along the direction perpendicular to the current gradually decreases; An electrode layer is stacked on the active area structure, and the electrode layer includes a first electrode and a second electrode that are spaced apart, and both the first electrode and the second electrode are connected to the barrier layer.

2. The semiconductor structure according to claim 1, characterized in that: The first electrode and the second electrode are both in contact with the barrier layer. From the first electrode to the second electrode, the width of the interface between the channel layer and the barrier layer is gradually reduced along a direction perpendicular to the current flow.

3. The semiconductor structure according to claim 2, characterized in that: The projection of the interface between the channel layer and the barrier layer on the substrate is triangular, the first electrode is connected to the barrier layer corresponding to a preset side m of the triangle, and the second electrode is connected to the barrier layer corresponding to a preset vertex n opposite to the preset side m.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: There are multiple device structures, and the multiple device structures are arranged around a preset center.

5. The semiconductor structure according to claim 4, characterized in that: The second electrode of each of the device structures is arranged close to the preset center.

6. The semiconductor structure according to claim 4 or 5, characterized in that: The first electrodes of the device structures are connected, and the second electrodes of the device structures are connected to form a cell.

7. The semiconductor structure according to claim 6, characterized in that: There are a plurality of cells, and the first electrodes in the plurality of cells are connected, and the second electrodes in the plurality of cells are connected.

8. The semiconductor structure according to claim 7, characterized in that: The device structure further includes a gate, which is stacked on the active area structure, located between the first electrode and the second electrode, and connected to the barrier layer; The gates in the plurality of cells are connected; The semiconductor structure further includes a third electrode. The plurality of cells are arranged around the third electrode. The gates in the plurality of cells are connected to the third electrode.

9. The semiconductor structure according to claim 1, characterized in that: The device structure also includes a gate, which is stacked on the active area structure, located between the first electrode and the second electrode, and connected to the barrier layer; the width of the interface between the channel layer and the barrier layer gradually decreases from the first electrode to the gate along a direction perpendicular to the current.

10. The semiconductor structure according to claim 9, characterized in that: The width of the interface between the channel layer and the barrier layer along the direction perpendicular to the current flow gradually decreases from the second electrode to the gate.

11. The semiconductor structure according to claim 10, characterized in that: There are multiple device structures, and the multiple device structures share the same gate. The multiple device structures are arranged around the gate. The first electrodes of the multiple device structures are connected, and the second electrodes of the multiple device structures are connected. Adjacent first electrodes and second electrodes are isolated by a first isolation structure.

12. The semiconductor structure according to claim 11, characterized in that: Each of the first electrodes is located on one side of the first isolation structure, and adjacent first electrodes are in contact with each other; each of the second electrodes is located on the other side of the isolation structure, and adjacent second electrodes are in contact with each other.

13. The semiconductor structure according to claim 11, characterized in that: The first electrodes and the second electrodes are alternately arranged around the gate.

14. The semiconductor structure according to any one of claims 1 to 13, characterized in that: The device structure further includes a second isolation structure, which is used to reduce the width of a region in the active region structure through which current flows, along a direction perpendicular to the current flow.

15. The semiconductor structure according to claim 14, characterized in that: The material of the second isolation structure includes P-type gallium nitride, the second isolation structure is stacked on the active area structure, and the second isolation structure is located between the first electrode and the second electrode.

16. The semiconductor structure according to claim 14, characterized in that A groove is provided on the channel layer and / or the barrier layer corresponding to the interface, and the second isolation structure includes an insulating filler, and the insulating filler is filled in the groove.

17. The semiconductor structure according to any one of claims 1 to 16, characterized in that: Projections of the channel layer and the barrier layer on the substrate completely overlap.

18. A radio frequency device, characterized in that: include: A radio frequency circuit and a semiconductor structure as described in any one of claims 1 to 17, wherein the device structure is connected to the radio frequency circuit.

19. An electronic device, characterized in that: It comprises: a control device and the radio frequency device according to claim 18, wherein the radio frequency device is connected to the control device.

20. A method for manufacturing a semiconductor structure, characterized in that: include: forming an active region structure on the substrate, wherein the active region structure comprises a barrier layer and a channel layer which are stacked; Along the direction parallel to the current, the width of the interface between the channel layer and the barrier layer along the direction perpendicular to the current gradually decreases; An electrode layer is formed on the active region structure, wherein the electrode layer includes a first electrode and a second electrode which are spaced apart from each other, and both the first electrode and the second electrode are connected to the barrier layer.

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