Integration of multi-modal transistors using transistor fabrication processes

Abstract

The invention relates to integration of multi-modal transistors using transistor fabrication processes. A semiconductor device and fabrication method is described for integrating a nanosheet transistor with a multi-mode transistor (MMT) in a single nanosheet process flow by processing a wafer substrate to form buried metal source / drain structures in an MMT region that are laterally spaced apart from each other and positioned below an MMT semiconductor channel layer, a transistor stack of alternating Si and SiGe layers is then formed in the FET region, the alternating Si and SiGe layers being selectively processed to form a gate electrode opening such that a first ALD oxide and metal layer is patterned and etched to form a gate electrode in the transistor stack and a channel control gate electrode over the MMT semiconductor channel layer, and causing a second oxide and conductive layer to be patterned and etched to form a current control gate electrode over the MMT semiconductor channel layer and adjacent to the channel control gate electrode.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices. In one aspect, the present disclosure relates to integrated multimodal transistor devices and field effect transistor (FET) devices and methods of making the same. Background Art

[0002] As semiconductor device sizes shrink, the requirements for device design and manufacturing continue to increase in order to fit more circuit systems on smaller chips. As device sizes shrink, increasingly complex process integration is used to define semiconductor device features and structures. For example, finFET transistors replaced planar FET transistors as the leading-edge transistor architecture at the 1Xnm node, but as next-generation technologies develop, stacked nanosheet transistors will replace finFETs as the leading-edge transistor architecture starting at the 3nm node, followed by forksheet devices, stacked complementary nanosheet FETs, etc. at the 2nm node. However, existing and projected FET devices use a thin-film transistor (TFT) design with a single gate electrode in the channel region to control the charge injection and switching functions of the device, so that the drain current has a quadratic response to the applied gate electrode voltage. Unfortunately, the transfer characteristics of conventional TFT designs are not well suited to the computational methods increasingly required by artificial intelligence applications such as artificial neural networks, which require a rectified linear unit (ReLU) activation function with a linear dependency between the input device voltage and the output (drain) current. Although multimodal transistor (MMT) devices have recently been proposed as TFT devices with a linear drain current response to gate voltage, existing MMTs have been presented on silicon using large dimensions and high operating voltages. Therefore, due to the challenges of manufacturing leading-edge FET devices with additional MMT device circuit elements while meeting performance requirements and cost constraints, existing semiconductor processes for manufacturing leading-edge FET transistors have not been integrated with MMT device manufacturing processes. Other limitations and disadvantages of conventional processes and techniques will become apparent to those skilled in the art after reviewing the remainder of this application with reference to the accompanying drawings and detailed description. Summary of the invention

[0003] A method for forming a semiconductor device having a nanosheet transistor integrated with a multimodal transistor device is provided. In the disclosed method, a wafer substrate is provided, the wafer substrate having an upper semiconductor layer extending across a field effect transistor region and a multimodal transistor (MMT) region. In selected embodiments, the wafer substrate includes a buried oxide substrate layer covered by the upper semiconductor layer. In other embodiments, the wafer substrate includes a single crystal silicon substrate. The disclosed method also includes processing the wafer substrate to form buried metal source / drain structures in the MMT region, the buried metal source / drain structures being laterally spaced apart from each other and positioned below an MMT semiconductor channel layer epitaxially grown from the upper semiconductor layer in the MMT region. In selected embodiments, the buried metal source / drain structure is formed by: selectively etching MMT source / drain openings through the upper semiconductor layer and into an underlying buried oxide layer in the MMT region; sequentially depositing an insulating liner layer, a barrier liner layer, and one or more metal layers to fill the MMT source / drain openings; polishing and / or recess etching the insulating liner layer, the barrier liner layer, and the one or more metal layers to form a metal source / drain structure in the source / drain opening recessed below the upper surface of the upper semiconductor layer; epitaxially growing the MMT semiconductor channel layer from the upper semiconductor layer to bury the metal source / drain structure; and planarizing the upper surfaces of the MMT semiconductor channel layer and the upper semiconductor layer. In addition, the disclosed method includes processing the wafer substrate to form a transistor semiconductor channel in the field effect transistor region of the wafer substrate. In selected embodiments, the transistor semiconductor channel is formed by providing a stack of alternating first and second semiconductor layers at least on the field effect transistor region of the wafer substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack at least on the field effect transistor region of the wafer substrate; processing the transistor stack to form an epitaxial semiconductor current end region adjacent to the transistor stack; and processing the transistor stack to selectively remove at least a portion of the first semiconductor layer, thereby forming a control electrode opening between the second semiconductor layers forming the transistor semiconductor channel, the transistor semiconductor channel connecting the epitaxial semiconductor current end region. In such embodiments, the first semiconductor layer can be a silicon germanium nanosheet layer, and the second semiconductor layer can be a silicon nanosheet layer. In addition, the sequential deposition of the first dielectric layer and the first conductive layer can include: depositing an atomic layer deposition (ALD) oxide layer above the field effect transistor region and the MMT region; and depositing an ALD metal layer above the ALD oxide layer in the field effect transistor region and the MMT region, thereby filling the control electrode opening with the ALD oxide layer and the ALD metal layer.In addition, the selective etching of the first conductive layer and the first dielectric layer can form the control electrode from the ALD oxide layer and the ALD metal layer in the control electrode opening, and the control electrode opening surrounds the transistor semiconductor channel formed by the second semiconductor layer in the transistor stack. In addition, the selective etching of the first conductive layer and the first dielectric layer can form the first MMT channel control electrode in the MMT area, the first MMT channel control electrode is located above the MMT semiconductor channel layer and is laterally positioned between the buried metal source / drain structures. In addition, the selective etching of the second conductive layer can form the second MMT channel control electrode in the MMT area, the second MMT channel control electrode is located above the MMT semiconductor channel layer and is laterally positioned to align with the buried metal source structure. The disclosed method also includes sequentially depositing a first dielectric layer and a first conductive layer above the field effect transistor area and the MMT area. In addition, the disclosed method includes selectively etching the first conductive layer and the first dielectric layer to form the control electrode of the transistor semiconductor channel and to form the first MMT channel control electrode in the MMT area. The disclosed method also includes depositing a second dielectric layer and a second conductive layer at least above the MMT region. In addition, the disclosed method includes selectively etching the second conductive layer to form a second MMT current control electrode, the second MMT current control electrode being positioned adjacent to the first MMT channel control electrode to control current in the MMT semiconductor channel layer. As disclosed, the first MMT channel control electrode, the second MMT channel control electrode, the MMT semiconductor channel layer and the buried metal source / drain structure form a multi-modal transistor device.

[0004] In another form, a method for forming a semiconductor device having a nanosheet transistor integrated with a multimodal transistor device is provided. In the disclosed method, a substrate is provided, the substrate having an upper semiconductor layer formed above a buried oxide layer. In addition, the disclosed method includes forming a buried metal source / drain structure in the substrate below the upper semiconductor layer. In selected embodiments, the buried metal source / drain structure is formed by: selectively etching a multimodal transistor (MMT) source / drain opening through the upper semiconductor layer and into the buried oxide layer; sequentially depositing an insulating liner layer, a barrier liner layer, and one or more metal layers to fill the MMT source / drain opening; and polishing and / or recess etching the insulating liner layer, the barrier liner layer, and the one or more metal layers to form a metal source / drain structure in the source / drain opening recessed below the upper surface of the upper semiconductor layer. The disclosed method also includes epitaxially growing an MMT semiconductor channel layer from the upper semiconductor layer to cover the buried metal source / drain structure. In addition, the disclosed method includes forming a first insulator layer over at least the MMT semiconductor channel layer using a first conformal insulator atomic layer deposition (ALD) process. The disclosed method also includes forming a first conductor layer over the first insulator layer using a first conformal conductor ALD process. In addition, the disclosed method includes selectively etching at least the first conductor layer to form a first MMT channel control electrode, the first MMT channel control electrode being positioned over the MMT semiconductor channel layer to extend between the buried metal source / drain structures. In addition, the disclosed method includes forming a second insulator layer over at least the first MMT channel control electrode and an exposed portion of the MMT semiconductor channel layer. The disclosed method also includes forming a second conductor layer over the second insulator layer. In addition, the disclosed method includes selectively etching at least the second conductor layer to form a second MMT current control electrode, the second MMT current control electrode being positioned over the MMT semiconductor channel layer and adjacent to the first MMT channel control electrode to control the current in the MMT semiconductor channel layer, wherein the second MMT current control electrode is insulated from the first MMT channel control electrode by the second insulator layer. In selected embodiments, the first MMT channel control electrode, the second MMT channel control electrode, the MMT semiconductor channel layer and the buried metal source / drain structure form a multimodal transistor device. In selected embodiments, after epitaxially growing the MMT semiconductor channel layer and before forming the first insulator layer over at least the MMT semiconductor channel layer, the substrate is processed to form a transistor semiconductor channel in a field effect transistor region of the substrate.In such embodiments, the substrate is processed to form the transistor semiconductor channel by providing a stack of alternating first and second semiconductor layers at least on a field effect transistor region of the substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack at least on the field effect transistor region of the substrate; processing the transistor stack to form an epitaxial semiconductor current end region adjacent to the transistor stack; and processing the transistor stack to selectively remove at least a portion of the first semiconductor layer, thereby forming a control electrode opening between the second semiconductor layers forming the transistor semiconductor channel, the transistor semiconductor channel connecting the epitaxial semiconductor current end region. In such embodiments, the first conformal insulator ALD process and the first conformal conductor ALD process sequentially fill the control electrode opening with the first insulator layer and the first conductor layer. In addition, the disclosed method may include selectively etching the first insulator layer and the first conductor layer to form a gate control electrode for the transistor semiconductor channel in the field effect transistor region of the substrate. In selected embodiments, the method selectively etches at least the second conductor layer to form a second MMT current control electrode to be positioned above one of the buried metal source / drain structures.

[0005] In yet another form, a method and semiconductor device are provided including a nanosheet transistor device and a multimodal transistor device formed on a substrate. As disclosed, the nanosheet transistor device includes a nanosheet stack formed on top of the substrate between a first epitaxial current-end semiconductor region and a second epitaxial current-end semiconductor region, wherein the nanosheet stack includes a full surround control electrode formed around a semiconductor layer from the nanosheet stack, the semiconductor layer connecting the first epitaxial current-end semiconductor region and the second epitaxial current-end semiconductor region. In addition, the disclosed multimodal transistor device is integrated with the nanosheet transistor device on top of the substrate to include: recessed metal source / drain structures formed in the substrate and laterally spaced apart from each other; an epitaxial semiconductor channel layer formed in the substrate, covering the recessed metal source / drain structures and extending above the recessed metal source / drain structures; a channel control electrode positioned above the epitaxial semiconductor channel layer and extending between the metal source / drain structures; and a current control electrode positioned above a portion of the epitaxial semiconductor channel layer and above one of the metal source / drain structures to control the current in the epitaxial semiconductor channel layer, wherein the current control electrode is isolated from the channel control electrode by an insulator layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention and the numerous objects, features and advantages achieved thereof will be understood when the following detailed description of the preferred embodiments is considered in conjunction with the following drawings.

[0007] Figure 1 is a partial cross-sectional view of a semiconductor structure having a nanosheet region and a multimodal transistor (MMT) region according to selected embodiments of the present disclosure, the semiconductor structure including a semiconductor layer disposed over a buried oxide substrate.

[0008] Figure 2 Showing selected embodiments according to the present disclosure Figure 1 This is followed by processing to etch buried source / drain openings in the MMT region extending through the semiconductor layer and into the buried oxide substrate.

[0009] Figure 3 Showing selected embodiments according to the present disclosure Figure 2 Processing after etching to form one or more metal source / drain layers in the buried source / drain openings.

[0010] Figure 4 Showing selected embodiments according to the present disclosure Figure 3 This is followed by processing after planarizing the one or more metal source / drain layers and the semiconductor layer.

[0011] Figure 5 Showing selected embodiments according to the present disclosure Figure 4 Processing is then performed after recessing one or more metal source / drain layers below the semiconductor layer to form a recessed buried metal source / drain structure.

[0012] Figure 6 Showing selected embodiments according to the present disclosure Figure 5 This is followed by post processing of epitaxially growing and polishing a semiconductor channel layer over the recessed buried metal source / drain structures.

[0013] Figure 7 Showing selected embodiments according to the present disclosure Figure 6 The processing is followed by forming a masking oxide layer over at least the MMT region.

[0014] Figure 8 Showing selected embodiments according to the present disclosure Figure 7 This is followed by processing after patterning and etching the Si / SiGe superlattice of alternating silicon nanosheets and silicon germanium nanosheets to form a nanosheet transistor stack above the nanosheet region.

[0015] Fig. 9 Showing selected embodiments according to the present disclosure Figure 8 This is followed by processing to form inner nitride spacers on the sidewalls of the nanosheet transistor stack.

[0016] Fig.10 Showing selected embodiments according to the present disclosure Fig. 9 This is followed by processing to form dielectric sidewall spacers on the sidewalls of the nanosheet transistor stack.

[0017] Fig.11 Showing selected embodiments according to the present disclosure Fig.10 This is followed by processing after a photoresist mask is formed to cover the MMT area.

[0018] Fig.12 Showing selected embodiments according to the present disclosure Fig.11 The processing is followed by forming an oxide filler layer to replace the semiconductor layer in at least a portion of the nanosheet region.

[0019] Fig.13 Showing selected embodiments according to the present disclosure Fig.12 This is followed by epitaxial growth and doping or implantation of source / drain regions adjacent to the nanosheet transistor stack.

[0020] Fig.14 Showing selected embodiments according to the present disclosure Fig.13 The process is then followed by forming a nanosheet gate electrode structure and a first MMT control gate electrode structure in the nanosheet transistor stack by sequentially forming an atomic layer deposition (ALD) oxide layer and an ALD metal layer.

[0021] Fig.15 Showing selected embodiments according to the present disclosure Fig.14 This is followed by processing after depositing an insulating oxide layer to cover the nanosheets and MMT regions.

[0022] Fig.16 Showing selected embodiments according to the present disclosure Fig.15 The processing after forming a second MMT control gate over the insulating oxide layer in the MMT region.

[0023] Fig.17 Simplified plan views of nanosheet transistor devices and MMT devices are shown according to selected embodiments of the present disclosure.

[0024] Fig.18 is a partial cross-sectional view of an MMT device formed in accordance with selected embodiments of the present disclosure.

[0025] Fig.19 A simplified process flow for the fabrication of an integrated nanosheet transistor device and an MMT device according to selected embodiments of the present disclosure is shown.

[0026] Fig. 20An MMT transfer characteristic diagram is shown to illustrate the operation of a multi-modal transistor (MMT) device. DETAILED DESCRIPTION

[0027] A semiconductor device and a method of manufacturing are described for integrating the manufacture of a multi-modal (MMT) device with a thin film FET device in a single manufacturing process flow, thereby providing a simple method to integrate an MMT device with an advanced thin film FET device on the same die using additional MMT device processing steps designed to have minimal impact on the thin film FET device. As used herein, an MMT device is a transistor having a metal source / drain region buried below a semiconductor channel region and having a separate or separate gate electrode to separate charge injection from conduction, so that a current control gate electrode determines the amount of charge to be transferred to the drain, and a channel control (independent on / off) gate electrode determines when the charge is transferred to the drain. There is a linear relationship between the input voltage and the output current. Although specific implementation details are described herein with reference to one or more example embodiments, the present disclosure relates to manufacturing an MMT device while manufacturing a thin film FET device to dually use many process steps. The steps for manufacturing an MMT device are standard process steps for manufacturing a thin film FET device, and therefore new manufacturing tools may not be required. For example, a nanosheet transistor semiconductor manufacturing process flow can be used for the manufacture of an integrated MMT device. In selected embodiments, an initial set of fabrication steps may be used to form a semiconductor substrate structure having a buried metal source / drain structure covered by a semiconductor channel layer in a defined MMT region of the semiconductor substrate structure. An initial set of fabrication steps may be performed using existing processing steps to fabricate a buried power rail structure in a semiconductor substrate structure that may be modified according to the present disclosure. For example, a buried power rail lithography and etching process may be modified to selectively etch source / drain openings through the semiconductor layer in the MMT region and into an underlying buried oxide region, followed by forming a recessed tungsten source / drain structure in the source / drain opening covered by an epitaxial semiconductor channel layer formed on the semiconductor substrate structure. Subsequently, the nanosheet region is processed by patterning and etching the initial Si / SiGe superlattice substrate structure to form a separate nanosheet transistor stack with an ALD metal gate electrode in the transistor stack. In selected embodiments, the processing steps for fabricating the ALD metal gate electrode are used to simultaneously form a first MMT metal control gate for each MMT device. Subsequently, the MMT region is processed to selectively form a second MMT metal control gate of each MMT device. For example, an insulating layer and a conductive polysilicon layer may be sequentially formed over the nanosheet and the MMT region, and then the conductive polysilicon layer may be patterned and etched to form the second MMT metal control gate.

[0028] Various illustrative embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Although various details are set forth in the following description, it should be understood that the present invention can be practiced without these specific details, and many implementation-specific decisions can be made to the present invention described herein to achieve the specific goals of the device designer, such as compliance with process technology or related design constraints, which vary from implementation to implementation. Although such research and development work may be complex and time-consuming, it is a routine task for ordinary technicians in the field who benefit from the present disclosure. For example, a simplified cross-sectional view of a reference semiconductor device depicts selected aspects, but does not include every device feature or geometric structure to avoid limiting or obscuring the present invention. Such descriptions and representations are generally used by technicians in the field to describe and convey the main purpose of their work to other technicians in the field. It should also be noted that throughout this specific embodiment, certain elements in the figure are shown for simplicity and clarity, and may not be drawn to scale. In addition, the size of some elements in the figure may be enlarged relative to other elements to help improve the understanding of the embodiments of the present disclosure. For example, the actual lateral size or measurement of the nanosheet transistor device will be much smaller than the actual lateral size or measurement of the MMT device. Furthermore, reference numerals have been repeated in the figures to indicate corresponding or similar elements. Additionally, the depicted device layers shown as being deposited and / or etched are represented with simplified line drawings, but it should be understood that in reality, for example, when the described etching processes are applied to different materials at different rates, or when the described deposition or growth processes generate the layers based on the underlying materials, the actual contours or dimensions of the device layers will be non-linear.

[0029] Now refer to Figure 1-20 Various illustrative embodiments of the present invention are described in detail. It should be noted that throughout this detailed description, certain material layers will be deposited and removed to form semiconductor structures. Where specific procedures for processing such layers or the thickness of such layers are not described in detail below, it is contemplated that such layers will be deposited, removed or otherwise formed with appropriate thicknesses using techniques that are routine to those skilled in the art. Such details are well known and are not considered necessary to teach those skilled in the art how to make or use the present invention.

[0030] One of the limitations of nanosheet transistors and other conventional thin-film FET devices is that the drain current has a quadratic response to the input gate voltage. This performance limitation has been addressed by MMT device designs that use a pair of separately controlled gate electrodes to provide a drain current with a linear response. To achieve this, the MMT device uses a first control gate electrode to set the drain current and a second control gate electrode to open or close the conductive channel between the source and drain. However, existing semiconductor processes used to make nanosheet transistors have not been used to make MMT devices because the processes are not practically suitable for integrating MMT devices that typically require metal source / drain regions and have been implemented using silicon using large sizes and high operating voltages. In addition, the use of separate dies for nanosheet transistors and MMT devices may increase the overall size of the final circuit solution and require additional wiring and connection costs.

[0031] Now go to Figure 1 , a partial cross-sectional view shows a semiconductor structure including a semiconductor layer 11 formed over a buried oxide (BOX) or dielectric substrate 10 according to selected embodiments of the present disclosure. As depicted, the semiconductor structure 10-11 has a nanosheet region 1 and a multimodal transistor (MMT) region 2 in which different devices will be formed, as described more fully below. Although not shown, it should be understood that the semiconductor structure 10-11 is formed over an underlying substrate, which can be implemented as a bulk silicon substrate, single crystal silicon (doped or undoped), or any semiconductor material, including, for example, Si, SiC, SiGe, SiGeC, Ge, GaAs, InAs, InsP, and other III-V compound semiconductors or any combination thereof, and can be formed as a bulk processing wafer. As should be understood, any suitable series of processing steps can be used to form the semiconductor structure 10-11, such as by bonding or implanting oxygen.

[0032] The terms "epitaxial growth", "epitaxial deposition" and "epitaxial formation" generally all refer to a semiconductor process for growing a semiconductor material or layer having a (basic) crystal structure on a deposition surface of a seed semiconductor material or layer having a (basic) crystal structure such that the growing semiconductor material / layer has substantially the same crystal properties as the seed semiconductor material / layer. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move on the surface so that the deposited atoms orient themselves towards the crystal arrangement of the atoms of the deposition surface. As a result, the epitaxially grown semiconductor material has substantially the same crystal properties as the deposition surface on which the epitaxially grown material is formed.

[0033] Figure 2 Showing selected embodiments according to the present disclosure Figure 1The semiconductor structure is then processed after the buried source / drain openings 12A, 12B extending through the semiconductor layer 11 and into the buried oxide substrate layer 10 are etched in the MMT region 2 using a photoetching process 12. Although any suitable photoetching process 12 may be used, a first patterned mask (not shown) may be formed over the semiconductor structure 10-11 by depositing, patterning, etching, or developing a photoresist or hard mask layer on the semiconductor layer 11. With the patterned photoresist mask in place, one or more etching processes are applied to form the buried source / drain openings 12A, 12B in the MMT region 2. The etching process may include performing a series of reactive ion etching (RIE) steps with suitable etching chemistry using the patterned photoresist mask to sequentially remove exposed portions of the semiconductor layer 11 and the underlying buried oxide substrate layer 10. For example, a controlled photoetching process 12 such as timed anisotropic dry etching may be used to remove a portion of the exposed portions of the semiconductor layer 11 and the underlying buried oxide substrate layer 10 to a predetermined depth. As depicted, etching of the semiconductor (Si) layer 11 in the MMT region leaves unetched semiconductor layers 11A-C, including a remaining semiconductor (Si) layer 11B corresponding to the semiconductor channel layer of the ultimately formed MMT device. Additionally, while the sidewalls of the buried source / drain openings 12A, 12B are substantially vertical, it should be appreciated that slight deviations in the sidewall profile may occur at each layer due to etching process variations.

[0034] Figure 3 Showing selected embodiments according to the present disclosure Figure 2 Processing of the semiconductor structure after one or more metal source / drain layers 13-15 are formed in the etched buried source / drain openings 12A, 12B. In selected embodiments, the metal source / drain layers 13-15 are formed by first conformally depositing a first insulating liner layer 13 (e.g., oxide or nitride) over the semiconductor structure to coat the bottom and sidewalls of the buried source / drain openings 12A, 12B. Subsequently, a second conformal barrier liner layer 14 (e.g., TiN) may be conformally deposited over the first insulating liner layer 13 to coat the bottom and sidewalls of the buried source / drain openings 12A, 12B. Finally, one or more conductive layers 15 (e.g., tungsten) are formed or deposited over the semiconductor structure to completely fill the buried source / drain openings 12A, 12B. In selected embodiments, the conductive layer 15 may be formed using any suitable deposition process, such as by depositing one or more conductive layers to fill the buried source / drain openings 12A, 12B using CVD, PECVD, PVD, ALD, sputtering, or any combination thereof.

[0035] Figure 4 Showing selected embodiments according to the present disclosure Figure 3Processing of the semiconductor structure is then performed after planarizing the one or more metal source / drain layers 13-15 with the semiconductor layers 11A-C. While any suitable planarization process may be used, in selected embodiments, a chemical mechanical polishing (CMP) process may be applied to remove portions of the metal source / drain layers 13-15 formed on top of the semiconductor layers 11A-C, wherein the CMP process is controlled to stop at the semiconductor layers 11A-C. As a result of the planarization step, the top of the semiconductor layer is cleared, and the remaining portions of the metal source / drain layers 13A-15A, 13B-15B fill the buried source / drain openings 12A, 12B.

[0036] Figure 5 Showing selected embodiments according to the present disclosure Figure 4 Processing of the semiconductor structure is then performed after recessing one or more metal source / drain layers 13A-15A, 13B-15B below the semiconductor layer 11 to form recessed buried metal source / drain structures 13C-15C, 13D-15D. While any suitable recess etching process may be used, in selected embodiments, the metal source / drain layers 13A-15A, 13B-15B may be selectively recess etched by applying one or more reactive ion etching (RIE) steps having suitable etching chemistry to remove upper portions of the metal source / drain layers 13A-15A, 13B-15B while leaving the semiconductor layers 11A-C and the recessed buried metal source / drain structures 13C-15C, 13D-15D in place. In selected embodiments, the recess etching process is controlled to stop at the top of the buried oxide substrate layer 10, but the depth of the recess etching can be adjusted to remove more or less of the upper portion of the metal source / drain layer 13C-15C, 13D-15D, provided that the remaining semiconductor (Si) layer 11A-C extends over the recessed buried metal source / drain structures 13C-15C, 13D-15D. At this point in the manufacturing process, the recessed buried metal source / drain structures 13C-15C, 13D-15D form buried metal source / drain regions 17 below the semiconductor channel layer 16. Although the recess etching process will clear the top of the metal source / drain layer 15C, 15D, an additional cleaning process may be required to clear the top surface of the recessed buried metal source / drain structures 13C-15C, 13D-15D. In other embodiments, one or more liner layers (not shown) may be included to facilitate good ohmic contact with the subsequently formed epitaxial semiconductor channel layer 16 .

[0037] Figure 6 Showing selected embodiments according to the present disclosure Figure 5Processing of the semiconductor structure after epitaxially growing and polishing the semiconductor channel layer 16 over the recessed buried metal source / drain structures 13C-15C, 13D-15D. Although any suitable manufacturing process may be used, the semiconductor channel layer 16 may be formed by epitaxially growing or depositing a semiconductor layer (e.g., silicon) on the semiconductor structure using the remaining semiconductor layer 11A-C to completely cover the recessed buried metal source / drain structures 13C-15C, 13D-15D in the MMT region 2. As should be appreciated, the epitaxial silicon deposition or growth process forms the semiconductor channel layer 16 from the remaining single crystal silicon layer 11A-C. Subsequently, one or more etching or polishing steps may be applied to planarize the top surface of the epitaxial semiconductor channel layer 16 with the remaining semiconductor (Si) layer 11A-C. In other embodiments, an oxide mask layer (not shown) may be formed over the remaining semiconductor layer 11A in the nanosheet region 1 to block epitaxial growth in that region when the semiconductor channel layer 16 is formed.

[0038] Figure 7 Showing selected embodiments according to the present disclosure Figure 6 Processing of the semiconductor structure after forming a masking oxide layer 18 over at least the MMT region 2. Depending on the requirements for protecting the nanosheet region 1, the masking oxide layer 18 can be formed by depositing or otherwise forming a protective masking layer having a thickness of about 20-200 angstroms over the semiconductor structure using chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, or any combination thereof, although thinner or thicker oxide layers may also be used. In addition, the masking oxide layer 18 can be selectively patterned and etched using any suitable selective etching process, such as by depositing, patterning, etching, or developing a photoresist or hard mask layer on the oxide layer 18, to expose the semiconductor (Si) layer 11 in at least a portion of the nanosheet region 1.

[0039] Figure 8 Showing selected embodiments according to the present disclosure Figure 7Processing of the semiconductor structure after patterning and etching the Si / SiGe superlattice of alternating silicon nanosheets and silicon germanium nanosheets to form a nanosheet transistor stack 20-26 covered by an oxide layer 27 over the nanosheet region 1. Depending on the requirement to protect the nanosheet transistor stack 20-26 from subsequent oxide etching steps, an additional protective nitride layer 28A may also be formed on the protective oxide layer 27. As should be appreciated, any suitable series of processing steps may be used to form the Si / SiGe superlattice on the remaining semiconductor layer 11A, such as by epitaxially growing a plurality of nanosheet semiconductor layers having alternating silicon germanium (SiGe) and silicon (Si), which are subsequently patterned and etched to form the nanosheet transistor stack. As shown, the depicted Si / SiGe superlattice is a stack of alternating layers, the stack comprising a first set of layers 20, 22, 24, 26 comprising silicon germanium and a second set of layers 21, 23, 25 comprising silicon. Although the Si / SiGe superlattice is shown as having four silicon germanium nanosheets 20, 22, 24, 26, it should be understood that the number of silicon germanium nanosheets can be reduced or increased (e.g., 5 SiGe nanosheets) to optimize transistor performance. If necessary, individual layers of the Si / SiGe superlattice can be doped or implanted with impurities to control the conductivity of the Si / SiGe superlattice.

[0040] After forming the Si / SiGe superlattice 20-26, a first oxide layer 27 is deposited or otherwise formed over the semiconductor structure using any suitable process (e.g., CVD, PECVD, PVD, ALD, thermal oxidation, or any combination thereof). In addition, a protective insulator or dielectric may be formed on the semiconductor structure, for example, by depositing or otherwise forming a protective nitride layer 28 of a predetermined thickness to cover the protective oxide layer 27 in the nanosheet region 1 and the MMT region 2. Subsequently, the Si / SiGe superlattice 20-26, the oxide layer 27, and the protective nitride layer 28 are patterned and etched to form a nanosheet transistor stack 20-26 including the oxide layer 27 and the protective nitride layer 28A on top. Although any suitable patterning and etching process may be used, a first patterned mask (not shown) may be formed on the semiconductor structure by depositing, patterning, etching, or developing a photoresist or hard mask layer on the protective nitride layer 28 to protect the nanosheet region 1 and the MMT region 2. With the first patterned mask in place, one or more etching processes may then be applied to form the nanosheet transistor stack 20-26, as well as the remaining oxide layer 27 and nitride layer 28A in the nanosheet region 1. Application of one or more etching processes may also form the remaining nitride layer 28B and the underlying oxide layer 18A in the MMT region 2. The etching process may include a series of reactive ion etching (RIE) steps with appropriate etching chemistry to sequentially remove the protective nitride layer 28, oxide layer 27, and exposed portions of the underlying layers of the Si / SiGe superlattice 20-26. As will be appreciated, the sidewalls of the resulting nanosheet transistor stack 20-26 are substantially vertical, but slight deviations in the sidewall profile may occur at each layer due to etching process variations.

[0041] Fig. 9 Showing selected embodiments according to the present disclosure Figure 8Processing of the semiconductor structure after forming inner nitride spacers 29 on the sidewalls of the nanosheet transistor stack 20-26. Although any suitable manufacturing process may be used, the inner nitride spacers 29 may be formed by selectively recessing the SiGe layers 20, 22, 24, 26 to form recess openings on the exposed sides of the nanosheet transistor stack. Although any suitable SiGe etching process may be used, a controlled SiGe recess etching process such as a timed isotropic dry etch may be used to remove a portion of each SiGe layer 20, 22, 24, 26 from the exposed side of the nanosheet transistor stack. At the end of the etching process, the remaining SiGe portions 20, 22, 24, 26 remain at locations where the recess openings were not formed and will define the first gate length dimension Lg of the subsequently formed nanosheet transistor. As will be appreciated, the etched sidewall edges of the remaining SiGe portions 20, 22, 24, 26 may have a substantially vertical or slightly curved profile resulting from the selective SiGe recess etching.

[0042] After forming the recess openings in the SiGe layers 20, 22, 24, 26, one or more dielectric layers are deposited or otherwise formed over the semiconductor structure to fill the recess openings, and subsequently etched to remove the dielectric layers from the top and sides of the nanosheet transistor stacks but leave the remaining dielectric spacers 29. For example, a nitride layer may be deposited over the semiconductor structure to a predetermined thickness sufficient to cover at least the nanosheet transistor stacks 20-26 and fill the recess openings on the exposed sides of the nanosheet transistor stacks 20-26. The remaining inner nitride spacers 29 are formed as sidewall spacers by applying an isotropic nitride etching process (e.g., RIE) to remove the nitride layer from the top and sides of the nanosheet transistor stacks 20-26. As will be appreciated, the etched sidewall edges of the remaining nitride spacers 29 may have a substantially vertical or slightly curved profile resulting from the applied isotropic nitride etching process.

[0043] Fig.10 Showing selected embodiments according to the present disclosure Fig. 9 Processing of the semiconductor structure is then performed after dielectric sidewall spacers 30 are formed on the sidewalls of the nanosheet transistor stack. While any suitable spacer formation process may be used, the sidewall spacers 30 may be formed by depositing one or more dielectric layers, such as an oxide layer, over the semiconductor structure and then applying an anisotropic etching process to remove the dielectric layers from horizontal surfaces of the semiconductor structure but leaving residual sidewall spacers 30 on the sides of the nanosheet transistor stack 20-26 and the patterned protective nitride layers 28A, 28B (not shown).

[0044] Fig.11 Showing selected embodiments according to the present disclosure Fig.10Processing of the semiconductor structure is then performed after a photoresist mask 31 is formed to cover the MMT region 2. Although not shown, the photoresist mask 31 is defined to also protect the exposed ends (in the z-direction) of the nanosheet transistor stacks 20-26. In this way, the photoresist mask 31 protects the semiconductor channel layer 16 in the MMT region 2 and the silicon layers 21, 23, 25 in the nanosheet transistor stack from subsequent silicon etching process steps. As shown, the patterned photoresist layer 31 is formed to leave an opening on the nanosheet transistor stack adjacent to the sidewall spacer 30, which exposes the bottom silicon nanosheet layer 11A.

[0045] Fig.12 Showing selected embodiments according to the present disclosure Fig.11 Processing of the semiconductor structure is then performed after forming an oxide filler layer 32 to replace at least a portion of the semiconductor layer 11A in at least a portion of the nanosheet region 1. While any suitable process may be used to form the replacement oxide filler layer 32, in selected embodiments, a suitable lateral silicon etch (e.g., an isotropic silicon wet etch) is applied with the patterned photoresist layer 31 in place to remove the bottom silicon nanosheet layer 11A except for the stack ends in the width dimension (e.g., perpendicular to the gate length dimension) that remains to support the nanosheet transistor stack 20-26. After etching at least a portion of the bottom silicon nanosheet layer 11A, the resulting openings are filled with one or more oxide layers to form the replacement oxide filler layer 32. For example, one or more conformal CVD oxide layers may be formed to fill the openings and form the replacement oxide filler layer 32. The remaining stack ends of the bottom silicon nanosheet layer 11A may be etched away in subsequent processing.

[0046] Fig.13 Showing selected embodiments according to the present disclosure Fig.12Processing of the semiconductor structure after epitaxially growing and doping or implanting source / drain regions 33 adjacent to the nanosheet transistor stack 20-26, 29. As depicted, at this point in the fabrication process, the sidewall spacers 30 must be removed prior to forming the epitaxial source / drain regions 33 by using a suitable isotropic oxide etch chemistry. The source / drain regions 33 may be formed by epitaxially growing or depositing a semiconductor layer (e.g., silicon) using the silicon layer 21, 23, 25 in a region adjacent to the nanosheet transistor stack, although any suitable source / drain fabrication process may be used. As should be appreciated, the epitaxial silicon deposition or growth process forms the epitaxial source / drain regions 33 from the exposed silicon layer 21, 23, 25. At this point, the epitaxial source / drain regions 33 may be doped using any suitable doping technique. For example, the epitaxial source / drain regions 33 may be doped in situ during the epitaxial process, for example, by doping the epitaxially grown source / drain features with boron, arsenic, and / or phosphorus to form doped epitaxial source / drain regions 33. In some embodiments, the source / drain features are not doped in situ, but instead an implantation process is performed to dope the epitaxial source / drain regions 33. As will be appreciated, the doping dose used to dope the epitaxial source / drain regions 33 is greater than the doping dose used to dope the channel regions in the silicon layers 21, 23, 25, if present. In addition, the processing of the source / drain regions 33 may be performed in separate processing steps for each of the N-type and P-type source / drain features. In some embodiments, after forming the source / drain regions 33, an epitaxial annealing process may be performed, for example, by applying a high thermal budget process, etc. to promote the formation of a crystalline structure in the epitaxial source / drain regions 33. In addition, one or more selective etching steps may be applied to allow the epitaxial source / drain regions 33 to have a uniform thickness.

[0047] Fig.14 Showing selected embodiments according to the present disclosure Fig.13Processing of the semiconductor structure after forming the gate electrode structures 34A, 35A in the nanosheet region 1 and the MMT control gate electrode structures 34B, 35B in the MMT region 2 by sequentially forming an atomic layer deposition (ALD) oxide layer 34 and an ALD metal layer 35. While any suitable manufacturing process may be used to form the gate electrode structures, the processing may begin with patterning and etching the nanosheet transistor stack with active photo / etching and a SiGe access process to expose the SiGe layers 20, 22, 24, 26 in the nanosheet transistor stack to a subsequent SiGe etching process. Although the depicted cross-sectional view does not show etching openings exposing the SiGe layers 20, 22, 24, 26, it should be understood that etching openings may be formed in the z-axis plane (in and out of the paper) to expose the peripheral ends of the SiGe layers 20, 22, 24, 26. Additionally, the active photo / etch and SiGe access process may include forming a patterned mask (not shown) over the semiconductor structure by depositing, patterning, etching, or developing a photoresist or hard mask layer on the epitaxial source / drain regions 33 and the nitride layer 28A over the nanosheet transistor stack.

[0048] Using the openings formed in the patterned photoresist / hard mask, the active photo / etch and SiGe access process may be followed by the application of one or more etching processes applied through the patterned photoresist / hard mask to etch and remove at least the exposed SiGe layers 20, 22, 24, 26. The etching process may include performing a series of reactive ion etching (RIE) steps with suitable etching chemistry to selectively etch and remove the exposed SiGe layers 20, 22, 24, 26. While any suitable SiGe etching process may be used, a selective isotropic SiGe etching process such as a timed isotropic dry etch may be used to remove the exposed remaining SiGe layers 20, 22, 24, 26 from the transistor stack. At the end of the SiGe etching process, the remaining SiGe layers 20, 22, 24, 26 of the nanosheet transistor stack are replaced with gate openings, where gate electrodes will be formed in the nanosheet transistor stack. At this point, a patterned photoresist mask layer may be formed over the nanosheet region 1, and the protective nitride layer 28B in the MMT region 2 may be selectively etched and removed. The oxide layer 18A may also be patterned and etched at this point to define a remaining oxide layer over the semiconductor channel layer 16 of the MMT region 2, but this is not necessarily required.

[0049] After forming the gate opening in the nanosheet transistor stack, a conformal gate dielectric layer 34 is deposited over the semiconductor structure, thereby forming a liner layer 34A in the gate opening of the nanosheet transistor stack in at least the nanosheet region 1. The deposition of the conformal gate dielectric layer 34 also covers the oxide layer 18A in the MMT region 2. In selected embodiments, the conformal gate dielectric layer 34 is formed using atomic layer deposition (ALD) to conformally deposit the ALD oxide layer 34A on the inner surface of the gate opening to a desired gate dielectric thickness (e.g., 5-50 angstroms) without completely filling the gate opening. In selected embodiments, the ALD oxide deposition process can be performed by exposing the semiconductor structure to a precursor, evacuating or purging the precursor and byproducts from the chamber, exposing the semiconductor structure to a reactant species (e.g., an oxidant or other reagent), and evacuating or purging the reactant and byproduct molecules from the chamber. Thus, the ALD oxide deposition process provides accurate control of film thickness and composition and the ability to achieve excellent uniformity over a large area at relatively low temperatures. In addition to forming gate dielectric layer 34A in the gate opening, the resulting ALD oxide 34 forms a substantially conformal gate dielectric layer over the upper surface of the semiconductor structure, including forming ALD oxide layer 34B on oxide layer 18A.

[0050] After forming the conformal gate dielectric layer 34, one or more conductive gate electrode layers are formed in the nanosheet region 1 to cover the nanosheet transistor stack and fill at least the remaining gate opening of the nanosheet transistor stack and cover the MMT region 1. In selected embodiments, the conductive gate electrode layer 35 is formed using an atomic layer deposition (ALD) process to conformally deposit at least a first ALD metal layer 35A on the ALD oxide layer 34A to a sufficient thickness to fill the remaining gate opening in the nanosheet transistor stack. In selected embodiments, the ALD metal deposition process can be performed by exposing the semiconductor structure to a precursor, evacuating or purging the precursor and byproducts from the chamber, exposing the semiconductor structure to a reactant species (e.g., a metal or other reagent), and evacuating or purging the reactant and byproduct molecules from the chamber. In addition to forming the gate electrode layer 35A in the gate opening, the ALD metal process forms an ALD metal layer as a substantially conformal layer over the upper surface of the semiconductor structure, including forming an ALD metal layer 35B on the ALD oxide layer 34B.

[0051] After forming the conductive gate electrode layer, one or more etching processes are applied to selectively pattern the ALD metal layer 35 and the ALD oxide layer 34 from the nanosheet region 1 and the MMT region 2. While any suitable etching process may be used, the etching process may use a patterned etching mask to apply one or more isotropic metal etching steps (e.g., RIE) with suitable etching chemistry to leave only the ALD metal layer 35A, 35B on the surface of the semiconductor structure while leaving the underlying ALD oxide layer 34 in place. Subsequently, the etching process may use a patterned etching mask to apply one or more isotropic and / or anisotropic oxide etching steps (e.g., RIE) with suitable etching chemistry to remove the ALD oxide layer 34 from the surface of the semiconductor structure, thereby leaving only the patterned ALD oxide layer 34A, 34B in place under the gate electrodes 35A, 35B.

[0052] Although not shown, there may be additional processing steps, such as formation of nitride sidewall spacers and / or silicidation of gate electrodes and / or epitaxial source / drain regions 33. However, at this point in the fabrication process, fabrication of the nanosheet transistor in nanosheet region 1 is substantially complete, as long as the nanosheet transistor includes a first gate electrode structure 34A, 35A formed around the nanosheet silicon channel layer 21, 23, 25 connecting the epitaxial source / drain regions 33. However, the MMT transistor in MMT region 2 is not yet complete, as only one of the control gate electrode structures 34B, 35B has been formed over the semiconductor channel layer 16 connecting the buried metal source / drain structures 13C-15C, 13D-15D. Therefore, additional steps are required to form a second control gate structure for the MMT device, as described below.

[0053] Fig.15 Showing selected embodiments according to the present disclosure Fig.14 Processing of the semiconductor structure is then performed after depositing an insulating layer 36 to cover the nanosheet region 1 and the MMT region 2. While any suitable insulating layer deposition step may be used, in selected embodiments, one or more oxide or dielectric layers 36 may be formed over the semiconductor structure to cover the nanosheet region 1 and the MMT region 2 so that the nanosheet transistor stack and the first gate electrode structure 34A, 35A conformally cover the top and sidewall surfaces. In selected embodiments, the oxide layer 36 may be deposited using CVD, PECVD, PVD, ALD, or any combination thereof to form a conformal oxide layer having a predetermined thickness (e.g., about 20 to 200 angstroms) that will separate the second control gate structure from the first control gate structure and the semiconductor channel layer 16.

[0054] Fig.16 Showing selected embodiments according to the present disclosure Fig.15Processing of the semiconductor structure is then performed after forming a second MMT control gate structure 37 over the insulating oxide layer 36 in the MMT region. While any suitable polysilicon gate formation process steps may be used, in selected embodiments, the second MMT control gate structure 37 may be formed on the insulating layer 36 by depositing a conductive polysilicon layer 37 to conformally cover the semiconductor structure (e.g., by using CVD, PECVD, PVD, ALD, or any combination thereof) to a predetermined thickness covering the top and sidewall surfaces of the semiconductor structure. The deposited first polysilicon layer 37 may then be selectively etched by forming a patterned photoresist or etch mask and applying a series of reactive ion etching (RIE) steps with suitable etching chemistry, leaving only the patterned polysilicon layer 37 in place as the second MMT control gate structure 37 of the MMT device. In defining the location of the patterned polysilicon layer 37 to form the MMT control gate structure, the inner or rightmost sidewall edge of the second MMT control gate structure 37 is substantially aligned to have a minimum specified overlap with the leftmost sidewall edge of the first MMT control gate structure 35B.

[0055] As Figure 1-16 The result of the processing steps shown in , provides a nanosheet transistor device 38 integrated with an MMT device 39 on a single die through a single nanosheet process flow, thereby providing a simple method for integrating an MMT device with an advanced nanosheet transistor on the same die. Although specific implementation details for integrating the manufacture of an MMT device with a nanosheet transistor process flow to dually use manufacturing steps are described herein, it should be understood that additional or fewer processing steps may be used and / or combined. For example, depending on the electrical connections and structures of the source / drain regions 33, gate electrodes 35A, polysilicon MMT control gate structures 37, metal MMT control gates 35B, and buried metal source / drain structures 15C, 15D, the semiconductor structure may be configured in a variety of different circuit configurations. In a first example configuration, the metal gate electrode 35A of the first nanosheet transistor may be directly electrically connected to the polysilicon MMT control gate structure 37 of the MMT device and electrically connected to the metal gate electrode 35A of the second nanosheet transistor. Additionally or alternatively, one or more buried conductor structures (not shown) may be formed as part of a backside power distribution network to electrically connect either or both of the buried metal source / drain structures 15C, 15D to other circuit elements, such as a control electrode (e.g., a gate or source / drain) in another nanosheet transistor.

[0056] In order to provide additional details to improve the understanding of the present disclosure, reference is now made to Fig.17, which shows a simplified plan view of a nanosheet transistor device 38 and an MMT device 39 formed according to selected embodiments of the present disclosure. Although not every device feature or layer is shown in the simplified plan view, it can be seen that the nanosheet transistor device 38 includes an ALD metal gate electrode 35A, which is a full-surround gate electrode extending along the side of the Si / SiGe epitaxial stack (not visible) covered by the protective nitride layer 28A. In addition, the nanosheet transistor device 38 includes an epitaxial source / drain region 33 connected across the silicon nanosheet layers 21, 23, 25 in the Si / SiGe epitaxial stack (not visible) covered by the protective nitride layer 28A. In addition, it can be seen that the MMT device 39 includes a patterned polysilicon layer 37 (which is a first control gate) and an ALD metal gate electrode 35B (which is a second control gate) positioned above the silicon semiconductor channel layer 16 to control the current between the buried metal source structure and the drain structure (shown in dashed lines). In this configuration, the patterned polysilicon layer 37 (first control gate) controls the amount of current in the MMT device 39 , and the ALD metal gate electrode 35B (second control gate) turns the semiconductor channel region 16 “on” or “off”.

[0057] To illustrate an example implementation of an MMT device formed in accordance with selected embodiments of the present disclosure, reference will now be made to Fig.18, which depicts a partial cross-sectional view of an MMT device including a source 15C and a drain 15D formed in a buried oxide substrate layer 10 below a semiconductor channel region 16 controlled by a first MMT control gate structure 37 and a second MMT control gate structure 35B. The construction of the buried source / drain regions in the buried oxide substrate layer 10 eliminates the sidewall charge injection problem that may occur when the semiconductor channel is located between the source region and the drain region. Therefore, the total charge injection of the MMT device is more uniform and may be more linear than that of a conventional thin film transistor device. Another benefit of the MMT device design is that the MMT device is a majority carrier device that operates using the characteristics of a Schottky junction and a MOSFET due to the metal source / drain structure. Specifically, for an n-type semiconductor channel region 16, if the first MMT control gate structure 37 receives a positive voltage when a ground voltage is applied to the second MMT control gate structure 35B, there is no current conducted across the semiconductor channel region 16 between the source region and the drain region. Additionally, if the second MMT control gate structure 35B receives a positive voltage when a ground voltage is applied to the first MMT control gate structure 37, the conduction channel in the semiconductor channel region 16 is turned on, but no current flows between the source and drain regions even at a large source-drain voltage VDS. However, if a positive voltage is applied to both the first MMT control gate structure 37 and the second MMT control gate structure 35B, current will flow across the semiconductor channel region 16 between the source and drain regions, and the magnitude of the current will be explicitly set by the voltage on the first MMT control gate structure 37 rather than other factors.

[0058] Now turn to see Fig.19, a simplified process flow 100 for the fabrication of an integrated nanosheet transistor device and an MMT device according to selected embodiments of the present disclosure is shown. In general, the process includes an initial set of fabrication steps 110 for fabricating a wafer substrate having a buried power rail / source / drain structure below an epitaxial semiconductor channel formed in an MMT region of the wafer substrate. A second set of fabrication steps 120 forms a nanosheet transistor stack in the nanosheet region of the wafer substrate by fabricating a Si / SiGe superlattice structure having alternating silicon nanosheets and silicon germanium nanosheets patterned and etched to form the nanosheet transistor stack. A third set of fabrication steps 130 processes the nanosheet transistor stack to partially etch the exposed SiGe nanosheets and form recess openings in the Si / SiGe superlattice, the recess openings being filled with inner nitride spacers to define the remaining SiGe nanosheets. A fourth set of fabrication steps 140 masks or protects the MMT region of the wafer substrate and the nanosheet transistor stack before replacing the semiconductor channel layer in the nanosheet region with a replacement dielectric layer. The fifth set of fabrication steps 150 forms epitaxial source / drain regions on the nanosheet transistor stack. The sixth set of fabrication steps 160 selectively processes the nanosheet transistor stack to remove the remaining SiGe nanosheet layer and form a gate etch opening, followed by sequential application of atomic layer deposition (ALD) oxide and metal layers to form transistor gate electrodes in the transistor stack and a first MMT metal control gate in the MMT region. The seventh set of fabrication steps 170 selectively processes the MMT region to form an MMT polysilicon control gate for the MMT device. The eighth set of fabrication steps 180 applies any desired middle of the line (MEOL) and back end of the line (BEOL) processing to the wafer substrate.

[0059] As will be appreciated, each set of manufacturing steps 110, 120, 130, 140, 150, 160, 170, 180 may be implemented in different embodiments using the process steps disclosed herein or modifications to the process steps, as will be appreciated by those skilled in the art. However, by illustrating selected example embodiments of the present disclosure, each set of manufacturing steps 110, 120, 130, 140, 150, 160, 170, 180 is described below in an example process step sequence.

[0060] Beginning with an initial set of fabrication steps 110, process 100 may begin at step 111 by selectively etching power rails and source / drain openings through at least a portion of a semiconductor layer formed in at least one multimodal transistor (MMT) region of a wafer substrate. In selected embodiments, the power rails and source / drain openings are formed by depositing, patterning, and developing a photoresist layer to form a patterned photoresist or hard mask layer on the semiconductor layer and then applying one or more etching processes to create the power rails and source / drain openings by etching through at least a portion of the semiconductor layer in the MMT region. The etching process may include a series of reactive ion etching (RIE) steps with appropriate etching chemistry to sequentially remove exposed portions of the semiconductor layer.

[0061] The initial set of fabrication steps 110 may also include forming recessed buried metal power rail and source / drain structures in the power rail and source / drain openings at step 112. For example, an insulator layer (e.g., oxide or nitride), a liner layer (e.g., TiN), and a conductive metal layer (e.g., W) may be sequentially deposited to fill the power rail and source / drain openings, followed by planarization or polishing with a CMP process before applying a recess etch to form the recessed buried metal power rail and source / drain structures in the power rail and source / drain openings. The recess etch process may include a timed RIE step that is controlled to remove exposed upper portions of the insulator layer, the liner layer, and the conductive metal layer such that the recessed buried source / drain structure is recessed below the unetched portion of the semiconductor layer.

[0062] The initial set of manufacturing steps 110 may also include forming a semiconductor channel layer above the recessed buried source / drain structure in the MMT region at step 113. For example, a first epitaxial silicon deposition or growth process may be used to selectively form a first epitaxial silicon layer from an unetched portion of the semiconductor layer above the recessed buried source / drain structure. When formed, the first epitaxial silicon layer should be formed to at least the height of the semiconductor layer by a controlled epitaxial growth process or an overgrowth process combined with an epitaxial silicon etching and / or polishing step. As will be appreciated, the first epitaxial silicon region may be doped or implanted with N-type or P-type impurities.

[0063] The second set of fabrication steps 120 may include forming a stacked silicon / silicon germanium superlattice structure over the semiconductor layer in the nanosheet region of the wafer substrate at step 121. In selected embodiments, the silicon / silicon germanium superlattice structure is formed as a Si / SiGe epitaxial stack by epitaxially growing alternating layers of Si and SiGe on the semiconductor substrate layer and then capping the Si / SiGe epitaxial stack by depositing an oxide protective layer and / or a protective nitride layer.

[0064] At step 122, the silicon / silicon germanium superlattice structure is processed using a gate length photo / etch process to form a nanosheet transistor stack. For example, a photoresist layer may be deposited, patterned, etched, and developed to form a patterned photoresist or hard mask layer on the protective oxide or nitride layer. With the patterned photoresist / hard mask layer in place, the processing at step 122 may include applying one or more etching processes to produce the nanosheet transistor stack. The etching process may include a series of reactive ion etching (RIE) steps with suitable etching chemistry to sequentially remove the exposed portions of the protective oxide or nitride layer and the underlying layers of the Si / SiGe epitaxial stack.

[0065] The third set of fabrication steps 130 may include selectively recessing the exposed SiGe nanosheets in the nanosheet transistor stack to form SiGe recess openings at step 131. For example, a controlled etching process such as timed isotropic dry etching may be applied to selectively recess the SiGe layer exposed at the sides of the nanosheet transistor stack, thereby forming SiGe recess openings in the nanosheet transistor stack by partially recessing the SiGe layer.

[0066] At step 132, a first dielectric spacer is formed in the SiGe recess opening of the nanosheet transistor stack. For example, an inner nitride layer may be deposited over the semiconductor structure, then patterned and isotropically etched to leave the inner nitride layer only in the SiGe recess opening of the nanosheet transistor stack.

[0067] The fourth set of fabrication steps 140 may include forming insulator spacers and / or a photoresist / mask layer at step 141 to protect the nanosheet transistor stack sidewalls and the MMT region from subsequent processing steps that replace the semiconductor channel layer in the nanosheet region with an alternative dielectric layer. For example, dielectric sidewall spacers may be formed on the sidewalls of the nanosheet transistor stack. Additionally, a photoresist mask may be formed to cover the MMT region and protect the exposed ends (in the z-direction) of the nanosheet transistor stack, thereby protecting the semiconductor channel layer in the MMT region and the silicon layer in the nanosheet transistor stack from subsequent silicon etching processing steps.

[0068] At step 142, the semiconductor layer in the nanosheet region is replaced with a replacement dielectric layer. For example, a suitable lateral silicon etch (e.g., an isotropic silicon wet etch) is applied to selectively remove the semiconductor layer from below the nanosheet transistor stack, except for the stack end that remains in the width dimension (e.g., perpendicular to the gate length dimension) to support the nanosheet transistor stack. After etching the semiconductor layer, the resulting opening is filled with one or more dielectric layers to form the replacement dielectric layer. For example, one or more conformal CVD oxide layers can be formed to fill the opening and form the replacement dielectric layer.

[0069] The fifth set of fabrication steps 150 may include one or more etching and / or cleaning steps 151 to remove the dielectric spacers and mask. For example, any suitable stripping process may be applied to remove the photoresist material, and a suitable oxide etching process may be used to selectively remove the dielectric sidewall spacers.

[0070] At step 152, a doped source / drain epitaxial layer is formed around and adjacent to the nanosheet transistor stack. In selected embodiments, an epitaxial semiconductor process may be applied to form an epitaxial semiconductor layer in a given source / drain region, which may be doped, for example, by using in-situ doping during the epitaxial semiconductor process and / or by implanting the epitaxial source / drain region with an N-type or P-type dopant, followed by one or more annealing processes to promote formation of a crystalline structure in the epitaxial source / drain region.

[0071] The sixth set of fabrication steps 160 for forming the gate electrode may include an active photo / etch step 161 to access the underlying SiGe layer in the nanosheet transistor stack. For example, a photoresist layer may be deposited, patterned, etched, and developed to form a patterned photoresist or hard mask layer, wherein the mask opening is positioned above the nanosheet transistor stack to access the underlying SiGe layer in the transistor stack. With the patterned photoresist / hard mask layer in place, the photo / etch process may include applying one or more etching processes to access the underlying SiGe layer in the nanosheet transistor stack. The etching process may include a series of reactive ion etching (RIE) steps with suitable etching chemistry to sequentially remove exposed portions of the underlying layer without removing the adjacent SiGe layer.

[0072] At step 162, the SiGe layer at the exposed nanosheet transistor stack is selectively etched to form a gate etch opening by removing the remaining SiGe layer in the nanosheet transistor stack. For example, a controlled etching process such as timed isotropic dry etching can be applied to selectively etch and remove the exposed SiGe layer at the nanosheet transistor stack, thereby forming a gate etch opening where the remaining SiGe layer was in the nanosheet transistor stack.

[0073] At step 163, a gate electrode is formed on the MMT region and in the gate etch opening of the nanosheet transistor stack. For example, the gate electrode may be formed by depositing an ALD oxide layer to form a conformal thin dielectric layer in the gate etch opening of the nanosheet transistor stack, followed by depositing an ALD metal layer to form the gate electrode by filling the gate etch opening.

[0074] At step 164, the ALD metal layer and the ALD oxide layer are patterned and etched to form a nanosheet gate stack in the nanosheet transistor stack and to form a first MMT metal control gate in the MMT region. For example, a photoresist layer may be deposited, patterned, etched, and developed to form a patterned photoresist or hard mask layer having mask openings such that a subsequent photo / etch process will sequentially remove exposed portions of the ALD metal layer and the ALD oxide layer, leaving only the ALD metal layer on the surface of the nanosheet transistor stack where the nanosheet gate electrode is located and on the surface of the MMT region where the first MMT metal control gate is located.

[0075] At this stage of the process, the front-end processing of the nanosheet transistor stack is substantially complete. However, additional processing of the MMT region is required to form a second MMT polysilicon control gate electrode. To this end, the seventh group of manufacturing steps 170 includes an oxide layer formation step 171. For example, one or more oxide layers having a predetermined thickness may be deposited using CVD, PECVD, PVD, ALD, or any combination thereof to form a conformal oxide layer over at least the first MMT metal control gate in the MMT region.

[0076] At step 172, a polysilicon layer is deposited on the oxide layer to cover at least the MMT region, and then the polysilicon layer is patterned and etched using any suitable selective etching process to form a second MMT polysilicon control gate. For example, the deposited polysilicon layer may be selectively etched by forming a patterned photoresist or etch mask and applying a series of reactive ion etching (RIE) steps with suitable etching chemistry, thereby leaving only the patterned polysilicon layer in place as the second MMT polysilicon control gate structure of the MMT device. When defining the location of the patterned polysilicon layer to form the second MMT polysilicon control gate, there should be a minimum specified amount of overlap between the first MMT metal control gate and the second MMT polysilicon control gate.

[0077] The eighth set of fabrication steps 180 may include any desired middle of the line (MEOL) and back end of the line (BEOL) processing steps to complete the fabrication of the nanosheet transistor and MMT device into a functional device. For example, one or more sacrificial oxide formation, stripping, isolation region formation, spacer formation, thermal drive or annealing steps, and polishing steps, as well as MEOL and BEOL processing, may be performed to form one or more levels of interconnects used to connect the transistors in a desired manner to achieve the desired functionality. Thus, the specific sequence of steps used to complete the fabrication of the nanosheet transistor and MMT device may vary depending on process and / or design requirements.

[0078] In order to provide additional details to enhance the understanding of selected embodiments of the present disclosure, reference is now made to Fig. 20 , which shows MMT transfer characteristic graphs 200, 210, 240 to illustrate the operation of a multi-modal transistor (MMT) device. Unlike other thin film field effect transistors where a single gate electrode in the channel region is responsible for controlling both charge injection and switching functions, an MMT device uses two control gates, one to control charge injection and one to control switching functions.

[0079] Specifically, the first control gate (G1) is positioned to overlap the buried source to control the magnitude of charge injection only in the source-G1 overlap region (SGO), and is therefore referred to as a current controlled gate. Thus, the G1 transfer characteristic 200 is similar to that of any transistor, except that, for second control gate (G2) voltage values ​​203 exceeding a predetermined minimum threshold, the dependence of the drain current on the G1 voltage is not quadratic, but linear. As depicted, the dependence of the drain current on the G1 voltage is only for small second control gate (G2) voltage values ​​201, 202 (e.g., V G2 = 0 unit volt or V G2 =0.2 unit volt) is nonlinear, but for larger second control gate (G2) voltage values ​​203 (e.g., V G2 = 0.4 unit volt or V G2 = 0.7 unit volt or V G2 = 1.0 unit volt) is linear.

[0080] In addition, a second control gate (G2) is positioned adjacent to the first control gate and above the semiconductor channel to control the channel switch of the MMT device after the channel is sufficiently accumulated without affecting the magnitude of the drain current. For this reason, the second control gate (G2) is referred to as a channel control gate. As shown by the G2 transfer characteristic 210, the curves 211-220 flatten out, where the intervals between the curves 211-220 are equal (linear). And as shown by the drain voltage transfer characteristic 240, the output characteristics of the MMT device flatten out, where the intervals between the output characteristics are equal (linear). The buried metal power rail / source / drain structure is a Schottky junction engineered to control current in and out of the MMT device.

[0081] Although the described exemplary embodiments disclosed herein relate to various semiconductor device structures and methods of manufacturing the same, the present invention is not necessarily limited to exemplary embodiments illustrating inventive aspects of the present invention applicable to a wide variety of semiconductor processes and / or devices. Therefore, the specific embodiments disclosed above are merely illustrative and should not be considered as limiting the present invention, as the present invention may be modified and implemented in different but equivalent ways that are apparent to those skilled in the art having the benefit of the teachings herein. For example, the depicted nanosheet transistor structure may be formed by different processing steps that may be combined and integrated with the MMT device manufacturing steps, and may utilize Si / SiGe superlattice structures having different numbers of SiGe and Si layers. In addition, the MMT processing steps may be integrated with processing steps for manufacturing other types of thin film FET devices other than nanosheet transistors, including but not limited to processing steps for manufacturing bulk planar FET devices, fully depleted SOI planar devices, bulk and SOI FinFET devices, bulk planar floating gate non-volatile devices, bulk planar thin film storage (TFS) non-volatile devices, etc. In addition, the various silicon-based constituent layers may be formed of conductive materials different from those disclosed. In addition, the epitaxial source and drain may be p-type or n-type, depending on whether a p-type or n-type semiconductor device is formed. In addition, the thickness of the described layers may deviate from the disclosed thickness values. Therefore, the foregoing description is not intended to limit the invention to the specific form set forth, but on the contrary, it is intended to cover such alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims, so that those skilled in the art will understand that they can make various changes, substitutions and modifications without departing from the spirit and scope of the invention in its broadest form.

[0082] Benefits, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these benefits, advantages, solutions to problems, and any elements that may make any benefit, advantage, or solution occur or become more significant should not be construed as important, necessary, or essential features or elements of any or all of the claims. As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements, but may include other elements that are not explicitly listed or that are not inherent to such process, method, article, or apparatus.

Claims

1. A method for forming a semiconductor device, characterized in that include: providing a wafer substrate, the wafer substrate comprising a field effect transistor region and a multi-modal transistor (MMT) region; processing the wafer substrate to form metal source / drain structures in the MMT region, the metal source / drain structures being laterally spaced apart from each other and positioned below the MMT semiconductor channel layer; processing the wafer substrate to form a transistor semiconductor channel in the field effect transistor region of the wafer substrate; Depositing a first dielectric layer and a first conductive layer sequentially over the field effect transistor region and the MMT region; Selectively etching the first conductive layer and the first dielectric layer to form a control electrode of the transistor semiconductor channel and to form a first MMT channel control electrode in the MMT region; depositing a second dielectric layer and a second conductive layer over at least the MMT area; as well as The second conductive layer is selectively etched to form a second MMT current control electrode positioned adjacent to the first MMT channel control electrode to control current in the MMT semiconductor channel layer.

2. The method according to claim 1, characterized in that: Processing the wafer substrate to form a metal source / drain structure includes: selectively etching MMT source / drain openings through the upper semiconductor layer and into an underlying buried oxide layer in the MMT region; Depositing an insulating liner layer, a barrier liner layer, and one or more metal layers in sequence to fill the MMT source / drain openings; polishing and / or recess etching the insulating liner layer, the barrier liner layer and the one or more metal layers to form a metal source / drain structure in the source / drain opening recessed below the upper surface of the upper semiconductor layer; epitaxially growing the MMT semiconductor channel layer from the upper semiconductor layer to bury the metal source / drain structure; and The upper surfaces of the MMT semiconductor channel layer and the upper semiconductor layer are planarized.

3. The method according to claim 1, characterized in that Processing the wafer substrate to form the transistor semiconductor channel includes: providing a stack of alternating first and second semiconductor layers at least on said field effect transistor region of said wafer substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack at least on the field effect transistor region of the wafer substrate; and The transistor stack is processed to selectively remove at least a portion of the first semiconductor layer, thereby forming a control electrode opening between the second semiconductor layers forming a semiconductor channel of the transistor.

4. The method according to claim 3, characterized in that: Sequentially depositing the first dielectric layer and the first conductive layer comprises: depositing an atomic layer deposition (ALD) oxide layer over the field effect transistor region and the MMT region; and An ALD metal layer is deposited over the ALD oxide layer in the field effect transistor region and the MMT region, thereby filling the control electrode opening with the ALD oxide layer and the ALD metal layer.

5. The method according to claim 3, characterized in that: The first conductive layer and the first dielectric layer are selectively etched to form the first MMT channel control electrode in the MMT region, the first MMT channel control electrode being located above the MMT semiconductor channel layer and laterally positioned between the metal source / drain structures.

6. A method for forming a semiconductor device, characterized in that include: providing a substrate comprising an upper semiconductor layer formed above a buried oxide layer; forming a metal source / drain structure in the substrate below the upper semiconductor layer; epitaxially growing a multimodal transistor (MMT) semiconductor channel layer from the upper semiconductor layer to cover the metal source / drain structure; forming a first insulator layer over at least the MMT semiconductor channel layer using a first conformal insulator atomic layer deposition (ALD) process; forming a first conductor layer over the first insulator layer using a first conformal conductor ALD process; selectively etching at least the first conductor layer to form a first MMT channel control electrode positioned above the MMT semiconductor channel layer to extend between the metal source / drain structures; forming a second insulator layer at least over the first MMT channel control electrode and the exposed portion of the MMT semiconductor channel layer; forming a second conductor layer over the second insulator layer; At least the second conductor layer is selectively etched to form a second MMT current control electrode, which is positioned above the MMT semiconductor channel layer and adjacent to the first MMT channel control electrode to control the current in the MMT semiconductor channel layer, wherein the second MMT current control electrode is insulated from the first MMT channel control electrode by the second insulator layer.

7. The method according to claim 6, characterized in that Forming a metal source / drain structure includes: selectively etching MMT source / drain openings through the upper semiconductor layer and into the buried oxide layer; Depositing an insulating liner layer, a barrier liner layer, and one or more metal layers in sequence to fill the MMT source / drain openings; and The insulating liner layer, the barrier liner layer, and the one or more metal layers are polished and / or recess-etched to form a metal source / drain structure in the source / drain opening recessed below an upper surface of the upper semiconductor layer.

8. The method according to claim 6, characterized in that Also included is processing the substrate to form a transistor semiconductor channel in a field effect transistor region of the substrate after epitaxially growing the MMT semiconductor channel layer and before forming the first insulator layer over at least the MMT semiconductor channel layer.

9. The method according to claim 8, characterized in that Processing the substrate to form the transistor semiconductor channel includes: providing a stack of alternating first and second semiconductor layers at least on a field effect transistor region of the substrate; selectively etching the stack of alternating first and second semiconductor layers to form a transistor stack at least on the field effect transistor region of the substrate; processing the transistor stack to form an epitaxial semiconductor current termination region adjacent to the transistor stack; and The transistor stack is processed to selectively remove at least a portion of the first semiconductor layer, thereby forming a control electrode opening between the second semiconductor layers forming the transistor semiconductor channel, the transistor semiconductor channel connecting the epitaxial semiconductor current terminal region.

10. A semiconductor device, characterized in that: include: substrate; a nanosheet transistor device comprising a nanosheet stack formed on top of the substrate between a first epitaxial current-end semiconductor region and a second epitaxial current-end semiconductor region, wherein the nanosheet stack comprises a fully surrounding control electrode formed around a semiconductor layer from the nanosheet stack, the semiconductor layer connecting the first epitaxial current-end semiconductor region and the second epitaxial current-end semiconductor region; as well as a multimodal transistor device integrated with the nanosheet transistor device on top of the substrate, the multimodal transistor device comprising: recessed metal source / drain structures formed in the substrate and laterally spaced apart from each other; an epitaxial semiconductor channel layer formed in the substrate, covering the recessed metal source / drain structure and extending above the recessed metal source / drain structure; a channel control electrode positioned above the epitaxial semiconductor channel layer and extending between the metal source / drain structures; and A current control electrode is positioned over a portion of the epitaxial semiconductor channel layer and over one of the metal source / drain structures to control current in the epitaxial semiconductor channel layer, wherein the current control electrode is isolated from the channel control electrode by an insulator layer.

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