Group III nitride semiconductor stress relaxation grid structure and preparation method thereof

Abstract

The invention discloses a group III nitride semiconductor stress relaxation grid structure and a preparation method thereof, and the structure comprises a substrate of a multi-layer structure, and the uppermost layer is a grid-shaped group III nitride semiconductor layer; the superlattice relaxation grid layer is arranged on the upper surface of the substrate and comprises at least two semiconductor layers which are alternately stacked and are of grid structures, and lattice constants of the two adjacent semiconductor layers are different; and the In-containing active layer is arranged on the upper surface of the superlattice relaxation grid layer, and the In-containing active layer comprises at least one layer of In-containing III nitride semiconductor layer with a grid structure. According to the III-group nitride semiconductor stress relaxation grid structure provided by the invention, due to the three-dimensional grid structure and the superlattice relaxation layer, the stress during growth of the lattice mismatch In-containing active layer can be effectively relaxed, and the in-plane lattice constant is expanded, so that the energy required by In incorporation can be reduced, and the In incorporation efficiency can be improved. And the high-quality semiconductor containing the In III nitride is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a group III nitride semiconductor stress relaxation grid structure and a preparation method thereof. Background Art

[0002] III-nitride semiconductor materials represented by GaN are widely used in the field of optoelectronics due to their excellent properties. GaN-based light-emitting diodes have been widely used in solid-state lighting, display and backlighting fields due to their advantages such as small size, long life and energy saving. In the spectrum of visible light, the wavelength of light emitted by III-nitride semiconductor materials mainly depends on the In content. By changing the In content, red, green and blue primary colors can be achieved, which is suitable for the preparation of light-emitting diode chips.

[0003] III-nitride semiconductor materials also have important applications in photoluminescence, such as InGaN multiple quantum wells as light converters from one color of light to another color of light in LEDs. In addition, by changing the In content, the bandgap width of III-nitride semiconductors can be adjusted within a large range, covering almost the entire solar spectrum, and is widely used in solar cells, photodetectors and other fields.

[0004] However, In-containing III-group nitride semiconductors face the problem of poor quality. Taking the current mature InGaN / GaN quantum well light-emitting diodes as an example, the In-N bond length is longer than the Ga-N bond. Due to the increase in In content, there is a large lattice mismatch between InGaN and GaN in the quantum well. The stress accumulated in the epitaxial growth relaxes in the form of a large number of dislocations, thereby generating non-radiative recombination centers, resulting in a decrease in the internal quantum efficiency of the LED. On the other hand, the incorporation of In is related to the strain energy required for the In-N bond to bind. When there is strong compressive strain in the quantum well, the incorporation of In will be more difficult due to the need for higher strain energy. Summary of the invention

[0005] The embodiment of the present invention provides a stress relaxation grid structure of a group III nitride semiconductor and a preparation method thereof, which can solve the problem of poor quality of current In-containing group III nitride semiconductors.

[0006] In a first aspect, an embodiment of the present invention provides a group III nitride semiconductor stress relaxation grid structure, comprising:

[0007] A substrate having a multi-layer structure, wherein the top layer is a grid-shaped III-nitride semiconductor layer;

[0008] A superlattice relaxed grid layer, which is arranged on the upper surface of the substrate and includes at least two semiconductor layers of a grid structure stacked alternately, wherein the lattice constants of two adjacent semiconductor layers are different;

[0009] The In-containing active layer is arranged on the upper surface of the superlattice relaxed grid layer, and the In-containing active layer comprises at least one In-containing III-group nitride semiconductor layer of a grid structure.

[0010] In a second aspect, an embodiment of the present invention provides a method for preparing a stress relaxation grid structure of a group III nitride semiconductor, comprising:

[0011] S1, photolithography is performed on the surface of the group III nitride template using a grid shape, and then the template is etched and cleaned to obtain a substrate;

[0012] S2. Depositing or growing at least two semiconductor layers of a staggered and stacked grid structure on the upper surface of the substrate to form a superlattice relaxed grid layer, wherein the lattice constants of two adjacent semiconductor layers are different;

[0013] S3. Depositing or growing at least one In-containing Group III nitride semiconductor layer having a grid structure on the upper surface of the superlattice relaxed grid layer to form an In-containing active layer.

[0014] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: according to the stress relaxation grid structure of the III-nitride semiconductor provided by the present invention, the stress during the growth of the lattice-mismatched In-containing active layer can be effectively relaxed due to the three-dimensional grid structure and the superlattice relaxation layer, and the in-plane lattice constant can be expanded, thereby reducing the energy required for In incorporation and realizing high-quality In-containing III-nitride semiconductors. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic structural diagram of a Group III nitride semiconductor stress relaxation grid structure provided by an embodiment of the present invention;

[0016] Figure 2 A schematic structural diagram of a substrate provided in an embodiment of the present invention;

[0017] Figure 3 A schematic structural diagram of a superlattice relaxed grid layer provided in an embodiment of the present invention;

[0018] Figure 4 A schematic diagram of a grid shape provided by an embodiment of the present invention;

[0019] Figure 5a A schematic diagram of an In-containing active layer structure including three quantum well layers provided in an embodiment of the present invention;

[0020] Figure 5b A schematic structural diagram of a single-layer In-containing active layer provided in an embodiment of the present invention;

[0021] Figure 6 A flowchart of a method for preparing a stress relaxation grid structure of a group III nitride semiconductor provided in an embodiment of the present invention;

[0022] Figure 7a , Figure 7b A schematic diagram of steps for preparing a substrate provided by an embodiment of the present invention;

[0023] Figure 8 A schematic diagram of the horizontal width of a grid provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0025] Figure 1 The structure diagram of a stress relaxation grid structure of a III-nitride semiconductor provided by an embodiment of the present invention is shown. As an example but not a limitation, see Figure 1 The stress relaxation grid structure of the group III nitride semiconductor may include a substrate 1, a superlattice relaxation grid layer 2, and an In-containing active layer 3 stacked in sequence from bottom to top.

[0026] Specifically, see Figure 2 The substrate 1 may be a multi-layer structure, with the top layer being a grid-shaped III-nitride semiconductor layer. Figure 3 The superlattice relaxation grid layer 2 may include at least two semiconductor layers in a grid structure that are alternately stacked, and the lattice constants of two adjacent semiconductor layers are different, thereby forming a patterned superlattice stress relaxation layer that is conducive to stress relaxation. Figure 1 The In-containing active layer 3 may also include at least one In-containing group III nitride semiconductor layer in a grid structure.

[0027] For example, see Figure 1-Figure 3 The lateral characteristic size of each layer of the grid in the stress relaxation grid structure of the group III nitride semiconductor can be micrometer or nanometer scale, so that the stress when growing the lattice-mismatched In-containing group III nitride quantum well on the superlattice relaxation grid layer 2 can be effectively relaxed, thereby improving the incorporation of In.

[0028] In some embodiments, see Figure 1-Figure 3 In the stress relaxation grid structure of the group III nitride semiconductor, the grid shapes of the upper surface of the substrate 1, the superlattice relaxation grid layer 2 and the In-containing active layer 3 can be the same, and the grid positions of each part are aligned.

[0029] In one possible implementation, see Figure 4The grid shape in the stress relaxation grid structure of the III-nitride semiconductor can be a polygonal hole such as a triangle, a circle, a square, a rectangle, a round hole, or a combination of these shapes. The grid shape is periodic, and the range of its arrangement period can include 0.05μm-20μm.

[0030] In one example, the width of the mesh shape in the III-nitride semiconductor stress relaxation mesh structure may range from 0.01 μm to 10 μm.

[0031] The grid shape with arrangement period and width within this range has a better effect on stress relaxation.

[0032] In some embodiments, see Figure 2 The substrate 1 may include a substrate layer 11, a nucleation layer 12, an unintentional doping layer 13, a group III nitride doping layer 14 and a grid-shaped group III nitride semiconductor layer 15 stacked in sequence from bottom to top.

[0033] Exemplarily, the III-nitride doped layer 14 and the grid-shaped III-nitride semiconductor layer 15 may be n-type, p-type, or unintentionally doped.

[0034] For example, the Ga content of the grid-shaped group III nitride semiconductor layer 15 may be not less than 60%.

[0035] In a possible implementation, the material of the substrate layer 11 may include sapphire, sapphire, silicon, silicon carbide, gallium oxide, zinc oxide, boron nitride, lithium aluminate, lithium niobate, germanium, aluminum nitride or lithium gallate; its thickness range may include 400μm-1000μm. The material of the nucleation layer 12 may be a group III nitride, such as GaN, and its thickness may include 20nm; the material of the unintentionally doped layer 13 may be the same as the nucleation layer 12, and its thickness may include 1μm; the material of the group III nitride doping layer 14 may be an n-type doped group III nitride, and its thickness may include 2μm; the material of the grid-shaped group III nitride semiconductor layer 15 may be an n-type doped group III nitride.

[0036] In one example, the doping concentration of the grid-shaped group III nitride semiconductor layer 15 may include 5×10 18 cm -3 .

[0037] In some embodiments, see Figure 3 The semiconductor layer in the superlattice relaxed grid layer 2 may also be a group III nitride semiconductor layer, wherein the materials of the two adjacent semiconductor layers may be In x Al y Ga 1-x-y N、In z Alw Ga 1-z-w N, x≠z, y≠w, and x, y, z, w are all numbers between 0 and 1. For example, the materials of two adjacent semiconductor layers in the superlattice relaxed grid layer 2 can be In 0.02 Ga 0.98 N and GaN.

[0038] Exemplarily, the vertical thickness of each semiconductor layer in the superlattice relaxed grid layer 2 may range from 1 nm to 10 nm.

[0039] In some embodiments, the In-containing active layer 3 may include at least one In-containing group III nitride semiconductor layer in a grid structure.

[0040] In a possible implementation, the In-containing active layer 3 may include a first barrier layer of a grid structure and at least one group of quantum confinement layers of a grid structure. The first barrier layer is the uppermost layer of the In-containing active layer 3. The quantum confinement layer may include barrier layers and quantum well layers stacked in sequence from bottom to top. Figure 5a The schematic diagram of the structure of the In-containing active layer 3 including three quantum well layers is exemplarily shown.

[0041] In one example, the quantum well layer may be an In-containing Group III nitride semiconductor layer.

[0042] Exemplarily, the quantum well layer may contain more than 5% In, and its vertical thickness may range from 1 nm to 10 nm.

[0043] Exemplarily, the first barrier layer and the barrier layer may not contain In; if the material of the barrier layer contains In, its In content is less than the In content of the quantum well layer; its vertical thickness range may include 3nm-150nm.

[0044] In another possible implementation, the In-containing active layer 3 may include an In-containing group III nitride semiconductor layer with a grid structure.

[0045] In one example, the In content of the single-layer In-containing active layer 3 may be greater than 5%, and the vertical thickness thereof may range from 11 nm to 500 nm. Figure 5b The schematic structural diagram of a single-layer In-containing active layer 3 is exemplarily shown.

[0046] According to the stress relaxation grid structure of the III-group nitride semiconductor provided by the present invention, the stress during the growth of the lattice-mismatched In-containing active layer can be effectively relaxed due to the three-dimensional grid structure and the superlattice relaxation layer, and the in-plane lattice constant is expanded, thereby reducing the energy required for In incorporation and realizing high-quality In-containing III-group nitride semiconductors.

[0047] Figure 6 The flowchart shown is a method for preparing a stress relaxation grid structure of a group III nitride semiconductor provided by an embodiment of the present invention. As an example but not a limitation, the preparation method may include steps S1-S3, and each step is described below.

[0048] S1, photolithography is performed on the surface of the III-nitride template in a grid shape, and then the template is etched and cleaned to obtain a substrate.

[0049] In a possible implementation, a group III nitride template may be prepared before photolithography of the grid shape. Specifically, a nucleation layer 12, an unintentional doping layer 13, and a group III nitride layer may be sequentially deposited on the substrate layer 11 to obtain a group III nitride template (see Figure 7a ).

[0050] In one example, a substrate layer 11 with a thickness of 650 μm and made of sapphire can be prepared first, and the substrate layer 11 can be placed in a metal organic vapor deposition system reaction chamber, and the substrate is heated to raise the temperature to 1100° C. The substrate layer 11 is subjected to high temperature treatment for 20 minutes in a hydrogen atmosphere, and the temperature is reduced to 515° C. Ammonia gas is introduced into the reaction chamber for 3 minutes, and then TMGa is introduced to epitaxially grow a 20 nm nucleation layer 12, and the temperature is raised to 1050° C., and TMGa and ammonia gas are introduced to epitaxially grow a 1 μm thick non-intentionally doped GaN layer 13 and a 2 μm thick n-type doped GaN layer (i.e., a group III nitride layer), and SiH4 is introduced simultaneously when growing the n-type doped GaN layer, and the doping concentration is 5×10 18 cm -3 , completing the preparation of the planar n-type doped III-nitride template.

[0051] In one possible implementation, a photoresist can be spin-coated on the surface of a III-nitride template, and a photolithography machine can be used to expose a micrometer / nanometer scale grid shape, and then developed to obtain a mask layer (see Figure 7b ). Then, the III-nitride template with the photoresist layer is placed in the chamber of the inductively coupled plasma etcher, and the upper surface of the III-nitride layer in the III-nitride template that is not covered by the photoresist is etched and cleaned until a preset depth. Exemplarily, the preset depth is less than the thickness of the III-nitride layer. In this way, the III-nitride layer is formed into a III-nitride doping layer 14 and a grid-shaped III-nitride semiconductor layer 15, respectively, to obtain a substrate 1 (see Figure 2 ).

[0052] In one example, a photoresist with a thickness of 1000 nm can be uniformly spin-coated on the surface of a group III nitride template, and a stepper lithography machine is used to expose the grid shape, and then developed to obtain a photoresist grid layer (i.e., a mask layer) having a hexagonal micro-nano grid pattern.

[0053] For example, see Figure 7b The inscribed circle diameter of the mesh hole can be 1000nm, and the mesh width can be 300nm.

[0054] In one example, the n-type III-nitride template can be etched 700 nm using an inductively coupled plasma etching process in an atmosphere of chlorine and argon, the GaN not covered by the photoresist grid is etched, and the area covered by the photoresist grid layer forms a grid-shaped III-nitride semiconductor layer 15, which is then placed in a degumming solution and heated in a water bath at 80°C until the remaining photoresist grid is removed, thereby obtaining a substrate 1.

[0055] S2, depositing or growing at least two semiconductor layers with an alternating and stacked grid structure on the upper surface of the substrate to form a superlattice relaxed grid layer.

[0056] In a possible implementation, a superlattice relaxed grid layer 2 can be deposited on the upper surface of the substrate 1 by metal organic chemical vapor deposition or a superlattice relaxed grid layer 2 can be grown on the upper surface of the substrate 1 by molecular beam epitaxy to obtain Figure 2 The structure shown.

[0057] For example, see Figure 3 The superlattice relaxed grid layer 2 may include 15 groups of semiconductor layers, each group of semiconductor layers includes a 5 nm thick In 0.02 Ga 0.98 N layer and a 5nm thick GaN layer.

[0058] In one example, In can be deposited by metal organic chemical vapor deposition at a temperature of 640°C, a reaction chamber pressure of 90 mbar, triethyl gallium (TEGa), trimethyl indium (TMIn), ammonia and nitrogen, with a specific TEGa flow rate of 10 μmol / min, a TMIn flow rate of 0.3 μmol / min, and an ammonia flow rate of 450 μmol / min. 0.02 Ga 0.98 N layers.

[0059] In another example, the temperature can be 620°C, the nitrogen flow rate of the nitrogen plasma source is 0.8 sccm, and the Ga beam equivalent pressure is set to 5.4×10 -7 Torr, the equivalent pressure of In beam is 9×10 -8 Torr, In was grown by molecular beam epitaxy.0.02 Ga 0.98 N layers.

[0060] S3, depositing or growing at least one In-containing Group III nitride semiconductor layer having a grid structure on the upper surface of the superlattice relaxed grid layer to form an In-containing active layer.

[0061] In a possible implementation, similarly, a 100 nm GaN layer as a barrier layer, a 5 nm In layer, and a 100 nm GaN layer as a barrier layer can be grown on the upper surface of the superlattice relaxed grid layer 2 by metal organic chemical vapor deposition or molecular beam epitaxy. 0.07 Ga 0.93 The N layer is used as a quantum well layer, and the 100 nm GaN layer is used as a first barrier layer, thereby forming an In-containing active layer 3 .

[0062] For example, see Figure 8 The lateral width of the grid shape of the In-containing active layer 3, that is, the wall thickness w inside the grid, can be 330 nm.

[0063] In one example, In can be deposited by metal organic chemical vapor deposition at a temperature of 640°C, a reaction chamber pressure of 90 mbar, triethyl gallium (TEGa), trimethyl indium (TMIn), ammonia and nitrogen, with a specific TEGa flow rate of 9 μmol / min, a TMIn flow rate of 1 μmol / min, and an ammonia flow rate of 450 μmol / min. 0.07 Ga 0.98 N layers.

[0064] In another example, the temperature can be 600°C, the nitrogen flow rate of the nitrogen plasma source is 0.8 sccm, and the Ga beam equivalent pressure is set to 5.4×10 -7 Torr, the equivalent pressure of In beam is 2.4×10 -7 Under the conditions of Tor, In was grown by molecular beam epitaxy. 0.07 Ga 0.98 N layers.

[0065] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0066] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0067] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0068] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, any modifications made without departing from the concept of the present invention should be deemed to belong to the protection scope of the present invention.

Claims

1. A group III nitride semiconductor stress relaxation grid structure, characterized in that: include: A substrate, wherein the substrate is a multi-layer structure, and the top layer is a grid-shaped group III nitride semiconductor layer; A superlattice relaxed grid layer, which is arranged on the upper surface of the substrate and includes at least two semiconductor layers of a grid structure stacked alternately, and the lattice constants of two adjacent semiconductor layers are different; An In-containing active layer is arranged on the upper surface of the superlattice relaxed grid layer, and the In-containing active layer comprises at least one In-containing III-group nitride semiconductor layer in a grid structure.

2. The III-nitride semiconductor stress relaxation grid structure according to claim 1, characterized in that: The Ga content of the uppermost Group III nitride semiconductor layer of the substrate is not less than 60%.

3. The III-nitride semiconductor stress relaxation grid structure according to claim 1, characterized in that: The semiconductor layer in the superlattice relaxed grid layer is a group III nitride semiconductor layer, and the materials of the two adjacent semiconductor layers include In x Al y Ga 1-x-y N、In z Al w Ga 1-z-w N, where x≠z, y≠w.

4. The III-nitride semiconductor stress relaxation grid structure according to claim 3, characterized in that: The vertical thickness of the semiconductor layer in the superlattice relaxed grid layer ranges from 1 nm to 10 nm.

5. The III-nitride semiconductor stress relaxation grid structure according to claim 1, characterized in that: The grid shapes of the substrate, the superlattice relaxed grid layer, and the In-containing active layer are the same, and the grid positions are aligned; the grid shapes are arranged periodically, and the arrangement period range of the grid shapes includes 0.05 μm-20 μm.

6. The III-nitride semiconductor stress relaxation grid structure according to claim 5, characterized in that: The width of the grid shape ranges from 0.01 μm to 10 μm.

7. The III-nitride semiconductor stress relaxation grid structure according to claim 6, characterized in that: The grid shapes include: regular polygons, circles, and figures composed of regular polygons and / or circles.

8. The III-nitride semiconductor stress relaxation grid structure according to claim 1, characterized in that: The In-containing active layer comprises a first barrier layer of a grid structure and at least one group of quantum confinement layers of a grid structure, wherein the first barrier layer is the uppermost layer of the In-containing active layer, and the quantum confinement layer comprises barrier layers and quantum well layers stacked in sequence from bottom to top; the quantum well layer is an In-containing III-group nitride semiconductor layer; The In content of the quantum well layer is greater than 5%, and the vertical thickness range of the quantum well layer includes 1nm-10nm; the In content of the first barrier layer and the barrier layer is less than the In content of the quantum well layer, and the vertical thickness range of the first barrier layer and the barrier layer includes 3nm-150nm.

9. The III-nitride semiconductor stress relaxation grid structure according to claim 1, characterized in that: The In-containing active layer comprises an In-containing group III nitride semiconductor layer with a grid structure. The In content of the In-containing active layer is greater than 5%. The vertical thickness range of the In-containing active layer is 11 nm-500 nm.

10. A method for preparing a stress relaxation grid structure of a group III nitride semiconductor, characterized in that: include: S1, photolithography is performed on the surface of the group III nitride template using a grid shape, and then the template is etched and cleaned to obtain a substrate; S2, depositing or growing at least two semiconductor layers of a staggered and stacked grid structure on the upper surface of the substrate to form a superlattice relaxed grid layer, wherein the lattice constants of two adjacent semiconductor layers are different; S3, depositing or growing at least one In-containing Group III nitride semiconductor layer in a grid structure on the upper surface of the superlattice relaxed grid layer to form an In-containing active layer.

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