Configurable transmitter device based on data rate

Abstract

The transmitter device includes a configurable timer circuit that adjusts the timing of the input data for serial transmission of the input data. The configurable timer circuit may be configured according to a configured data rate of the transmitter device. In one embodiment, a configurable timer circuit includes a plurality of configurable retimers that retime input data, where at least a portion of one of the plurality of configurable retimers is enabled based on a configured data rate.

Description

background 1. Technical Field

[0002] The present disclosure relates generally to transmitter devices and, more particularly, to a configurable transmitter device including a reconfigurable timer circuit that is configurable based on a data rate of the transmitter device.

[0003] 2. Description of Related Technology

[0004] High-speed communication systems transmit data over a communication link at high data rates (e.g., 10 GS / s and above). Conventional transmitter devices in high-speed communication systems are configured to operate at a single data rate. Therefore, conventional transmitter devices lack the flexibility to operate in different environments that require different data rates. In addition, conventional transmitter devices are configured to process incoming digital data for transmission in a parallel manner. However, the parallel processing of digital data results in increased delays in conventional transmitter devices. Summary of the invention

[0005] In one embodiment, the transmitter device includes a configurable timer circuit that adjusts the timing of input data for serial transmission of the input data. The configurable timer circuit can be configured according to a configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers and a plurality of configurable multiplexers connected to the plurality of configurable retimers.

[0006] Each of the configurable retimers is configured to receive input data for corresponding bits of the input data and adjust the timing of the input data to generate retimed input data. Each configurable multiplexer is connected to a corresponding configurable retimer and receives the retimed input data output by the configurable retimer. The configurable multiplexer selects a portion of the retimed input data for output according to a plurality of different selection signals so as to serialize the retimed input data for output by the transmitter device. Different portions of the configurable retimers and the configurable multiplexers are enabled and disabled according to a configured data rate of the transmitter device so as to transmit the retimed input data at the configured data rate.

[0007] The features and advantages described in the specification are not all-inclusive, and in particular, many additional features and advantages will be apparent to those of ordinary skill in the art in view of the drawings, the specification and the claims. In addition, it should be noted that the language used in the specification is primarily selected for readability and instructional purposes only, and is not selected to describe or limit the subject matter of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Advantages and features of the disclosed embodiments will become more readily apparent from the detailed description, the appended claims and the accompanying drawings (or figures).The following is a brief description of the drawings.

[0009] Attached photos( Figure 1 ) shows a high-speed communication system including a configurable transmitter device and a receiver device communicating via a channel according to an embodiment.

[0010] Figure 2 is a detailed block diagram of a configurable transmitter device according to an embodiment.

[0011] Figure 3 is a detailed block diagram of a configurable timer circuit included in a configurable transmitter device according to an embodiment.

[0012] Figure 4A is a detailed view of a configurable retimer included in a configurable timer circuit during a first mode of a configurable transmitter device according to an embodiment.

[0013] Figure 4B is a detailed view of a configurable multiplexer included in a configurable timer circuit during a first mode of a configurable transmitter device according to an embodiment.

[0014] Figure 4C is a waveform diagram of a clock signal of a configurable transmitter device during a first mode according to an embodiment.

[0015] Figure 5A is a detailed view of a configurable retimer included in a configurable timer circuit during a second mode of a configurable transmitter device according to an embodiment.

[0016] Figure 5B is a detailed view of a configurable multiplexer included in a configurable timer circuit during a second mode of a configurable transmitter device according to an embodiment.

[0017] Figure 5C is a waveform diagram of a clock signal of a transmitter device configurable during a second mode according to an embodiment.

[0018] Fig. 6A is a detailed view of a configurable retimer included in a configurable timer circuit during a third mode of a configurable transmitter device according to an embodiment.

[0019] Figure 6Bis a detailed view of a configurable multiplexer included in a configurable timer circuit during a third mode of a configurable transmitter device according to an embodiment.

[0020] Figure 6C is a waveform diagram of a clock signal of a configurable transmitter device during a third mode according to an embodiment.

[0021] Figure 7 A method flow chart describing a method for a configurable transmitter device to transmit data according to an embodiment is shown. DETAILED DESCRIPTION

[0022] The accompanying drawings (figures) and the following description relate to embodiments only by way of illustration. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as feasible alternatives that can be adopted without departing from the principles claimed. Reference will now be made in detail to several embodiments, examples of which are shown in the accompanying drawings. Note that, where feasible, similar or similar reference numerals may be used in the figures and may indicate similar or similar functions.

[0023] System environment

[0024] According to an embodiment, Figure 1 The invention is a high-speed communication system 100 including a configurable transmitter device 101 (hereinafter referred to as "transmitter device 101") and a receiver device 103, which are coupled to each other via a communication channel 105. The communication channel 105 can be a copper communication channel carrying single-ended or differential signals, such as found in a computing backplane. The communication channel 105 can also be an optical communication channel carrying optical signals, for example.

[0025] The transmitter device 101 transmits a channel signal to the receiver 103 via the channel 105. The channel signal is an analog signal representing digital data transmitted by the transmitter device 101. Figure 1 As shown, according to one embodiment, the transmitter device 101 includes a clock circuit 107 configured to generate a clock signal, a transmitter circuit 109 configured to transmit a channel signal according to the generated clock signal, and a configurable timer circuit 111 configured to convert data included in the channel signal into a serial form. The transmitter device 101 may have Figure 1 Other circuits than shown. In some embodiments, the transmitter device 101 may be a stand-alone device or a component of a larger device, such as an application specific integrated circuit (ASIC).

[0026] The receiver device 103 recovers digital data from a channel signal received from the transmitter device 101 via the channel 105. In one embodiment, the receiver device 103 generates a digital data output representing an estimated digital value of the channel signal. In some embodiments, the receiver device 103 may be a stand-alone device or a component of a larger device, such as an application-specific integrated circuit (ASIC).

[0027] Transmitter device architecture

[0028] Figure 2 Detailed view of a transmitter device 101 according to one embodiment is shown. As described above, the transmitter device 101 includes a clock circuit 107, a transmitter circuit 109, and a configurable timer circuit 111. The clock circuit 107 includes a clock generator circuit 201. In one embodiment, the clock generator circuit 201 generates a clock signal 203. The clock signal 203 includes a clock signal 203A transmitted to the transmitter circuit 109, and the clock signal 203A controls the timing when the transmitter circuit 109 transmits the channel signal to the receiver device 103. The clock signal 203 also includes a configurable clock signal 203B and a configurable clock signal 203C, the configurable clock signal 203B is a selection signal that controls the timing when the configurable timer circuit 111 outputs serial data to the transmitter circuit 109 for transmission in the channel signal, and the configurable clock signal 203C controls the timing when adjusting (e.g., retiming) the data for transmission, which will be further described below. The configuration of the configurable clock signal 203B and the configurable clock signal 203C depends on the configured data rate of the transmitter device 101 .

[0029] In one embodiment, the transmitter device 101 may be configured to operate at one of a plurality of data rates. For example, the transmitter device 101 may operate in a first mode associated with transmitting data at a first data rate (e.g., 56G baud rate), which corresponds to a maximum data rate of the transmitter device 101, may operate in a second mode associated with transmitting data at a second data rate (e.g., 16G baud rate), which corresponds to a minimum data rate of the transmitter device 101, or may operate in a third mode associated with transmitting data at a third data rate (e.g., 32G baud rate), which corresponds to an intermediate data rate of the transmitter device 101. By being able to reconfigure the transmitter device 101, the transmitter device 101 may support legacy communication standards. For example, the settings configuring the data rate for the transmitter device may be stored in a register 219 included in the configurable timer circuit 111.

[0030] As described above, the configurable clock signal 203B and the configurable clock signal 203C are configured according to the data rate of the operation (e.g., mode) of the transmitter device 101. For example, when the transmitter device 101 operates at a first data rate (e.g., 56G baud rate) corresponding to the maximum data rate of the transmitter device 101, the configurable clock signal 203C may be a 64T clock signal, when the transmitter device 101 operates at a second data rate (e.g., 16G baud rate) corresponding to the minimum data rate of the transmitter device 101, the configurable clock signal 203C may be a 16T clock signal, or when the transmitter device 101 operates at a third data rate (e.g., 32G baud rate) corresponding to the intermediate data rate of the transmitter device 101, the configurable clock signal 203C may be a 32T clock signal.

[0031] In one embodiment, the configurable timer circuit 111 serializes the input data 209 for transmission by the transmitter circuit 109. In one embodiment, the configurable timer circuit 111 includes a configurable retimer circuit 205 and a configurable multiplexer circuit 207. As will be further described below, the components of the configurable retimer circuit 205 and the configurable multiplexer circuit 207 are reconfigured based on the data rate at which the transmitter device 101 is operating.

[0032] In general, the configurable retimer circuit 205 receives input data 209 to be included in a channel signal transmitted to the receiver device 103. For example, the data 209 is digital data. In one embodiment, the input data 209 for inclusion in the channel signal is too large to be processed within one cycle of the configurable clock signal 203C. Therefore, the configurable retimer circuit 205 retimes the input data 209 to generate retimed data 211. In one embodiment, the configurable retimer circuit 205 retimes the data by adjusting the timing of the input data 209 so that the data can be processed according to one cycle of the configurable clock signal 203C.

[0033] The configurable multiplexer circuit 207 receives the retimed data 211 from the configurable timer circuit 211. The configurable multiplexer circuit 207 is configured to select the retimed data for output to the transmitter circuit 109 as serialized data 217 for transmission in the channel signal according to the configurable clock signal 203B. By outputting the data 217 serially, the delay is reduced compared to conventional transmitter devices that process data in parallel.

[0034] The transmitter circuit 109 receives the serialized data 217 from the configurable timer circuit 111, and transmits a channel signal including the serialized data 217 to the receiving device 103 via the channel 105. In one embodiment, the transmitter circuit 109 includes a multiplexer 213 and a driver circuit 215. The multiplexer 213 selects the serialized data to be output via the driver circuit 215 according to the clock signal 203A. The driver circuit 215 outputs the channel signal including the selected serialized data to the receiving device 103.

[0035] Configurable timer circuit architecture

[0036] Figure 3 1 is a detailed block diagram of a configurable timer circuit 111 included in a configurable transmitter device 101 according to an embodiment. In one embodiment, the configurable retimer circuit 205 includes a plurality of configurable retimers 301A to 301G. Each configurable retimer 301 is configured to receive a specific bit N of the input data 209 and generate retimed data 211 for bit N of the data input to the configurable retimer 301 according to the clock signal 203C, where N is an integer from 0 to 7 in one embodiment. For example, the configurable retimer 301A receives the most significant bit (MSB) of the input data 209A and outputs the retimed data 211A for the MSB, the configurable retimer 301B receives the second most significant bit of the input data 209B and outputs the retimed data 211B for the second most significant bit, the configurable retimer 301C receives the third most significant bit of the input data 209C and outputs the retimed data 211C for the third most significant bit, and the configurable retimer 301D receives the fourth most significant bit of the input data 209D and outputs the retimed data 211C for the third most significant bit. The configurable retimer 301E receives the fifth most significant bit of the input data 209E and outputs the retimed data 211E for the fifth most significant bit, the configurable retimer 301F receives the sixth most significant bit of the input data 209F and outputs the retimed data 211F for the sixth most significant bit, and the configurable retimer 301G receives the least significant bit (LSB) of the input data 209G and outputs the retimed data 211G for the LSB.

[0037] In one embodiment, the configurable multiplexer (MUX) circuit 207 includes a plurality of configurable multiplexers (MUX) 303A to 303G that receive the retimed data 211. The configurable MUX 303A to 303G output serialized data 217A to 217G to the transmitter circuit 109, wherein each configurable multiplexer 303 outputs serialized data 217 for a corresponding bit N based on the received retimed data 211.

[0038] like Figure 3 As shown, each configurable MUX 303 is connected to a corresponding one of the plurality of configurable retimers 301 and receives retimed data from the configurable retimer 201 . For example, configurable MUX 303A is connected to configurable retimer 301A and receives retimed data 211A to output as serialized data 217A, configurable MUX 303B is connected to configurable retimer 301B and receives retimed data 211B to output as serialized data 217B, configurable MUX 303C is connected to configurable retimer 301C and receives retimed data 211C to output as serialized data 217C, configurable MUX 303D is connected to configurable retimer 301D and receives retimed data 211D to output as serialized data 217D, configurable MUX 303E is connected to configurable retimer 301E and receives retimed data 211E to output as serialized data 217E, and configurable MUX 303C is connected to configurable retimer 301C and receives retimed data 211C to output as serialized data 217C. 303F is connected to the configurable retimer 301F and receives the retimed data 211F to output as serialized data 217F, and the configurable MUX 303G is connected to the configurable retimer 301G and receives the retimed data 211G to output as serialized data 217G.

[0039] Each configurable MUX 303 is configured to select the retimed data received from the configurable retimer 301 corresponding to each configurable MUX 303 to output as the serialized data 217 according to the clock signal 203B. In one embodiment, the clock signal 203B includes a plurality of selection signals sel which control which portion of the retimed data 211 is output as the serialized data 217. <n>, which will be further described below.

[0040] Reconfiguration of configurable timer circuit 111

[0041] As previously described, the transmitter device 101 may be configured to operate at one of a plurality of data rates, wherein each data rate corresponds to a different mode of operation of the transmitter device 101. In one embodiment, the configurable timer circuit 111 is reconfigured according to the mode of operation of the transmitter device 101. Generally, portions of the configurable retimers 301A to 301G and portions of the configurable MUXs 303A to 303G are enabled or disabled according to the mode of operation of the transmitter device 101, as will be further described below.

[0042] First Mode

[0043] Figure 4A is a high-level block diagram of configurable retimers 301A-301G during a first mode of the transmitter device 101 according to an embodiment. As previously described, the first mode of the transmitter device 101 corresponds to a maximum data rate of the transmitter device 101 .

[0044] In one embodiment, each configurable retimer 301A to 301G includes a plurality of registers (e.g., flip-flops) 403A to 403L. The plurality of registers 403 are arranged into a plurality of rows of registers. The plurality of rows of registers are divided into a first group of registers including registers 403A to 403D and a second group of registers including registers 403E to 403L. In one embodiment, the first group of registers 403A to 403D is configured to receive a first half (e.g., a first portion) of input data 209, and to generate retimed data 211 for the first half of the input data based on a clock signal 203C that is a 64T clock in a first mode. In contrast, the second group of registers 403E to 403L is configured to receive a second half (e.g., a second portion) of the input data 209, and to generate retimed data 211 for the second half of the input data based on the clock signal 203C.

[0045] In the first mode, each register 403 in the first group of registers receives a corresponding portion of the first half of the input data 209. In one embodiment, during the first mode, each portion may have a size of 8 bits. For example, the register 403A included in each configurable retimer 301 receives data D63 to data D56 corresponding to bit N and outputs retimed data D63 to retimed data D56, the register 403B included in each configurable retimer 301 receives data D55 to data D48 corresponding to bit N and outputs retimed data D55 to retimed data D48, the register 403C included in each configurable retimer 301 receives data D47 to data D40 corresponding to bit N and outputs retimed data D47 to output retimed data D40, and the register 403D receives data D39 to data D32 corresponding to bit N and outputs retimed data D39 to retimed data D32.

[0046] In the second group of registers, the second register pairs are connected to each other in series to output the second half of the input data 209 based on the clock signal 203C. For example, the register 403E included in each configurable retimer 301 receives the corresponding N-bit data D31 to data D24, and outputs the retimed data D31 to the retimed data D24 to the input D of the register 403I, and the register 403I further delays the output of the retimed data D31 to the retimed data D24, and the register 403F included in each configurable retimer 301 receives the corresponding N-bit data D23 to data D16, and outputs the retimed data D23 to the retimed data D26 to the input D of the register 403J, and the register 403J further delays the output of the retimed data D23 to the retimed data D16. ; The register 403G included in each configurable retimer 301 receives the corresponding N-bit data D15 to data D08 and outputs the retimed data D15 to retimed data D08 to the input D of the register 403K, and the register 403K further delays the output of the retimed data D15 to retimed data D08; and the register 403H included in each configurable retimer 301 receives the corresponding N-bit data D07 to data D00 and outputs the retimed data D07 to retimed data D00 to the input D of the register 403L, and the register 403L further delays the output of the retimed data D07 to retimed data D00. The second group of registers is configured to delay the output of the second half of the retimed input data so that the input data 209 can be serially output during one cycle of the clock signal 203C. For example, data D63 to data D32 are output during a “high” level period of the clock signal 203C, and data D31 to data D00 are output during a “low” level period of the clock signal 203C, which will be further described below.

[0047] Figure 4B is a high-level block diagram of configurable MUX 303A to configurable MUX 303G during a first mode of the transmitter device 101 according to an embodiment. In one embodiment, each of the plurality of configurable MUX 303A to 303G includes a plurality of switches 407A to 407H. Each of the plurality of switches 407 included in a given configurable MUX 303 is connected to an output (e.g., a Q node) of a corresponding one of the registers 403 included in the configurable retimer 301, which is connected to the given configurable MUX 303. For example, the input of switch 407A is connected to the output of register 403A, the input of switch 407B is connected to the output of register 403B, the input of switch 407C is connected to the output of register 403C, the input of switch 407D is connected to the output of register 403D, the input of switch 407E is connected to the output of register 403I, the input of switch 407F is connected to the output of register 403J, the input of switch 407G is connected to the output of register 403L, and the input of switch 407H is connected to the output of register 403L.

[0048] Each of the plurality of switches 407 is configured to receive a corresponding portion of the retimed data 211 output by the register 403 connected to the switch 405. For example, the switch 407A receives the portion of the retimed data 211 including the retimed D63 to the retimed D56, the switch 407B receives the portion of the retimed data 211 including the retimed D55 to the retimed D48, the switch 407C receives the portion of the retimed data 211 including the retimed D47 to the retimed D40, and the switch 407D receives the portion of the retimed data 211 including the retimed D39 to the retimed D32. , switch 407E receives a portion of the retimed data 211 including retimed D31 to retimed D24, switch 407F receives a portion of the retimed data 211 including retimed D23 to retimed D16, switch 407G receives a portion of the retimed data 211 including retimed D15 to retimed D08, and switch 407H receives a portion of the retimed data 211 including retimed D07 to retimed D00.

[0049] The plurality of switches 407 are configured to sequentially output the retimed data 211 as serialized data 217 based on the clock signal 203B. In one embodiment, during the first mode, the clock signal 203B includes a plurality of selection signals sel <7> 、sel <6> 、sel <5> 、sel <4> 、sel <3> 、sel <2> 、sel <1> and sel <0> Each switch 407 is configured to output a corresponding portion of the retimed data 211 input to the switch 407 in response to one of the selection signals to generate the serialized data 217. For example, the switch 407A is configured to output a corresponding portion of the retimed data 211 input to the switch 407 in response to the selection signal sel <7> , outputs the retimed data D63 to the retimed D56; the switch 407B responds to the selection signal sel <6> , outputs the retimed data D55 to the retimed D48; the switch 407C responds to the selection signal sel <5> , outputs the retimed data D47 to the retimed D40; the switch 407D responds to the selection signal sel <4> , outputs the retimed data D39 to the retimed D32; the switch 407E responds to the selection signal sel <3> , outputs the retimed data D31 to the retimed D24; the switch 407F responds to the selection signal sel <2> , outputs the retimed data D23 to the retimed D16; the switch 407G responds to the selection signal sel <1> , outputting the retimed data D15 to D08 after retime; and the switch 407H responds to the selection signal sel <0> , outputting the retimed data D07 to the retimed D0 to generate serialized data 217.

[0050] In one embodiment, during a first mode in which the transmitter device 101 transmits data at a first data rate (e.g., 56G baud rate) corresponding to a maximum data rate of the transmitter device 101, all of the plurality of configurable MUXs 303A to 303F and all of the plurality of switches 407A to 407H included in the plurality of configurable MUXs 303A to 303F are enabled. That is, none of the configurable MUXs 303A to 303F are disabled, and none of the switches 407A to 407H for each of the configurable MUXs 303A to 303F are disabled.

[0051] Figure 4C is a waveform diagram of the clock signal 203 of the transmitter device 101 during the first mode according to an embodiment. As described above, during the first mode, all of the registers 403 included in the configurable retimer 301 are enabled, and all of the switches 407 included in the configurable MUX 4305 are enabled. During the first mode, the configurable clock signal 203C that controls the retiming of the input data 209 is, for example, a 64T clock signal. One cycle of the clock signal 203C includes a first portion 409 corresponding to a "low" level of the clock signal 203C and a second portion 411 corresponding to a "high" level of the clock signal 203C.

[0052] The input data 209 input to the configurable retimers 301A to 301G includes data D63 to data D00 for each bit N, where N is an integer from 0 to 6. During the first mode, during the first portion 409 of the clock signal 203C, all of the input data 209 cannot be processed. In one embodiment, the plurality of configurable retimers 301 adjust the timing of the input data 209 so that during the first portion 409 of the clock signal 203C, a first half of the input data 209 (e.g., D63 to D32 for bit N of the input data) is output by the configurable retimers 301 as a first half of the retimed data 211A, and during the second portion 411 of the clock signal 411, a second half of the input data 209 (e.g., D31 to D00 for bit N of the input data) is output by the configurable retimers 301 as a second half of the retimed data 211B, as shown in FIG. Figure 4C shown.

[0053] The retimed data 211 (eg, the first half of the retimed data 211A and the second half of the retimed data 211B) is input to the configurable MUX 303A to the configurable MUX 303G. Each of the configurable MUX 303A to the configurable MUX 303G is responsive to a selection signal sel. <7> to sel <0> The clock signal 203B of the configurable MUX 303A to the configurable MUX 303G is selected to sequentially output the retimed data 211 as the serialized data 217. For example, the configurable MUX 303A to the configurable MUX 303G are responsive to the selection signal sel <7> , outputting serialized data 217A including retimed data D63 to retimed data D56 for bit N from the first half of the retimed data 211A; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <6> , outputting serialized data 217B including retimed data D55 to retimed data D48 for bit N from the first half of the retimed data 211A; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <5> , outputting serialized data 217C including retimed data D47 to retimed data D40 for bit N from the first half of the retimed data 211A; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <4> , outputting serialized data 217D including retimed data D39 to retimed data D32 for bit N from the first half of the retimed data 211A; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <3> , outputting serialized data 217E including retimed data D31 to retimed data D24 for bit N from the second half of the retimed data 211B; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <2> , outputting serialized data 217F including retimed data D23 to retimed data D16 for bit N from the second half of the retimed data 211B; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <1> Outputs serialized data 217G including retimed data D15 to retimed data D08 for bit N from the second half of the retimed data 211B; and finally, the configurable MUX 303A to the configurable MUX 303G are responsive to the selection signal sel <0> , outputting serialized data 217H including retimed data D07 to retimed data D00 for bit N from the second half of the retimed data 211B.

[0054] Second Mode

[0055] Figure 5A According to an embodiment, during the second mode of the transmitter device 101 Figure 3 1 is a high-level block diagram of a configurable retimer 301 in FIG. 1 . In one embodiment, the second mode of the transmitter device 101 is a "half rate" mode. For example, during the second mode, the transmitter device 101 transmits data at a second data rate (e.g., 32G baud rate) corresponding to half of the maximum data rate of the transmitter device 101. In one embodiment, the input data 209 for transmission during the second mode is half the size of the input data 209 during the first mode. For example, the input data 209 in the second mode has a size of 32 bits for each of the data bits N (e.g., Data D31 to Data D0), while the input data 209 in the first mode has a size of 64 bits for each of the bits N (e.g., Data D63 to Data D0), where N is 0 to 6.

[0056] In one embodiment, during the second mode, all of the configurable retimers 301A through 301G are still enabled. However, half of the rows of registers are enabled, and half of the rows of registers 403 are disabled. Figure 5A As shown, in one example, the register rows enabled during the second mode include registers 403A, 403F, 403G, 403H, 403J, 403K, and 403L, and the register rows disabled include registers 403B, 403C, 403D, 403E, and 403I.

[0057] Similar to the first mode, in the second mode, the enabled registers are further subdivided into a first group of registers including register 403A and a second group of registers including a pair of second registers 403E to 403L. In one embodiment, the first group of registers including register 403A is configured to receive a first portion of input data 209 and generate retimed data 211 for the first portion of the input data based on a clock signal 203C that is a 32T clock in the second mode. In contrast, the second group of registers 403E to 403L is configured to receive a second portion of the input data 209 and generate retimed data 211 for the second portion of the input data based on the clock signal 203C.

[0058] According to one embodiment, in the second mode, each enabled register receives 8 bits of data from the input data 209. For example, the register 403A included in the first group of registers receives data D31 to data D24 of bit N and outputs retimed data D31 to retimed data D24. In the second group of registers, the second register pairs are connected in series to retime the output of the second part of the input data 209 based on the clock signal 203C. For example, register 403F receives data D23 to data D16 of bit N and outputs data D23 to data D16 to input D of register 403J, which further delays the output of data D23 to data D16 to generate retimed data D23 to retimed data D16; register 403G receives data D15 to data D08 of bit N and outputs retimed data D15 to data D08 to input D of register 403K, which further delays the output of data D15 to data D08 to generate retimed data D15 to retimed data D08; and register 403H receives data D07 to data D00 of bit N and outputs data D07 to data D00 to input D of register 403L, which further delays the output of data D07 to data D00 to generate retimed data D07 to retimed data D00. The second group of registers is configured to delay the output of the second portion of the input data so that the input data 209 can be serially output by the configurable retimer 301 during one cycle of the clock signal 203C. For example, during the "high" level of the clock signal 203C, data D31 to data D24 for bit N are output by the configurable retimer 301, and during the "low" level of the clock signal 203C, data D23 to data D00 for bit N are output by the configurable retimer 301, which will be further described below.

[0059] Figure 5B According to an embodiment, during the second mode of the transmitter device 101 Figure 3 A high-level block diagram of configurable MUX 303A through configurable MUX 303G is shown in FIG.

[0060] In one embodiment, during the second mode in which the transmitter device 101 transmits data at a second data rate (e.g., 32G baud rate) corresponding to half of the maximum data rate of the transmitter device 101, all of the configurable MUXs 303A to 303G are enabled. However, a first portion (e.g., half) of the plurality of switches 407 included in each of the configurable MUXs 303 is enabled, and a second portion (e.g., the remaining half) of the plurality of switches 407 is disabled. Figure 5C As shown, in one example, a first portion of switches 407 enabled during the second mode includes switches 407A, 407F, 407G, and 407H, and a second portion of switches 407 disabled during the second mode includes switches 407B, 407C, 407D, and 407E.

[0061] The enabled switch 407 is configured to sequentially output the retimed data 211 input to the enabled switch 407 as serialized data 217 based on the clock signal 203B. In one embodiment, during the second mode, the clock signal 203B includes a portion (e.g., half) of the selection signal included in the first mode. For example, during the second mode, the clock signal 203B includes the selection signal sel <7> , select signal sel <2> , select signal sel <1> And the selection signal sel <0> Each enabled switch 407 is configured to output a portion of the retimed data 211 input to the switch 407 in response to one of the selection signals to generate the serialized data 217 .

[0062] For example, the switch 407A responds to the selection signal sel <7> , outputting the retimed data D31 to the retimed data D24, the switch 407F responds to the selection signal sel <2> , outputting the retimed data D23 to the retimed D16, the switch 407G responds to the selection signal sel <1> , outputs the retimed data D15 to D08, and the switch 407H responds to the selection signal sel <0> , outputting the retimed data retimed D07 to retimed D00 to generate serialized data 217. The disabled switches 407B to 407E do not receive any retimed data during the second mode, and thus do not output serialized data during the second mode.

[0063] Figure 5C 2 is a waveform diagram of the clock signal 203 of the transmitter device 101 operating in the second mode according to an embodiment. As described above, during the second mode, a portion of the register 403 included in each of the configurable retimers 301 is enabled, and a portion of the switch 407 included in each of the configurable MUXs 303 is enabled. During the second mode, the configurable clock signal 203C that controls the retiming of the input data 209 is, for example, a 32T clock signal. One cycle of the clock signal 203C includes a first portion 501 corresponding to a "low" level of the clock signal 203C and a second portion 503 corresponding to a "high" level of the clock signal 203C.

[0064] The input data 209 input to the configurable retimers 301A to 301G includes data D31 to data D00 for each bit N, where N is an integer from 0 to 6. During the second mode, during the first portion 501 of the clock signal 203C, all of the input data 209 cannot be output by the configurable timer circuit 111. In one embodiment, the plurality of configurable retimers 301 included in the configurable retimer circuit 111 retimes the input data 209 so that a first portion of the input data (e.g., D31 to D24 for bit N of the input data 209) is output by the configurable retimer 301 as a first portion of the retimed data 211A during a first segment of the first portion 501 of the clock signal 203C, and a second portion of the input data 209 (e.g., D23 to D00 for bit N of the input data 209) is output by the configurable retimer 301 as a second portion of the retimed data 211B during the remaining segments of the first portion 501 of the clock signal 203C and the second portion 503 of the clock signal 203C, as shown in FIG. Figure 5C shown.

[0065] The retimed data 211 (eg, the first portion of the retimed data 211A and the second portion of the retimed data 211B) is input to the configurable MUX 303A to the configurable MUX 303G. Each of the configurable MUX 303A to the configurable MUX 303G is responsive to a selection signal sel. <7> , select signal sel <2> , select signal sel <1> And the selection signal sel <0> The clock signal 203B of the configurable MUX 303A to the configurable MUX 303G is selected to sequentially output the retimed data 211 as the serialized data 217. For example, the configurable MUX 303A to the configurable MUX 303G are responsive to the selection signal sel <7> , outputting the serialized data 217A including the retimed data D31 to D24 for bit N from the first portion of the retimed data 211A; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <2> , outputting the serialized data 217B including the retimed data D23 to D16 for bit N from the second portion of the retimed data 211B; then the configurable MUX 303A to the configurable MUX 303G respond to the selection signal sel <1> , outputting serialized data 217C including retimed data D15 to D08 for bit N from the second portion 211B of the retimed data; and finally, configurable MUX 303A to configurable MUX 303G in response to the selection signal sel <0> , outputting serialized data 217D including the retimed data D07 to D00 for bit N from the second portion 211B of the retimed data.

[0066] Third Mode

[0067] Fig. 6A During the third mode of the transmitter device 101 according to an embodiment, Figure 3 . A high-level block diagram of the configurable retimers 301A to 301G shown in . In one embodiment, the third mode of the transmitter device 101 is a "quarter rate" mode. For example, during the third mode, the transmitter device 101 transmits data at a third data rate (e.g., 16G baud rate) corresponding to one-quarter of the maximum data rate of the transmitter device 101. In one embodiment, the input data 209 for transmission during the third mode is one-quarter the size of the input data 209 during the first mode. For example, the input data 209 in the third mode has a size of 16 bits for each of the bits N (e.g., Data D15 to Data D00), while the input data 209 in the first mode has a size of 64 bits for each of the bits N (e.g., Data D63 to Data D00), where N is an integer from 0 to 6.

[0068] In one embodiment, during the third mode, all of the configurable retimers 301A to 301G are still enabled. However, similar to the second mode, in the third mode, the first row of the multi-row registers 403 included in each of the configurable retimers 301 is enabled, and the second row of the multi-row registers 403 is disabled. In one embodiment, the first row of the multi-row registers that are enabled is one quarter of the total number of the multi-row registers. Fig. 6A As shown, in one example, a first row of multiple rows of registers 403 enabled during the third mode includes register 403A, register 403H, and register 403L, and a second row of multiple rows of registers disabled during the third mode includes register 403B, register 403C, register 403D, register 403E, register 403F, register 403G, register 403I, register 403J, and register 403K.

[0069] Similar to the first mode and the second mode, in the third mode, the enabled registers are further subdivided into a first group of registers including register 403A and a second group of second register pairs including register pairs 403H and 403L. The first group of registers including register 403A is configured to receive the first half of the input data 209, and generate the retimed data 211 for the first half of the input data based on the clock signal 203C which is a 16T clock in the third mode. In contrast, the second group of registers 403H and 403L is configured to receive the second half of the input data 209, and generate the retimed data 211 for the second half of the input data 209 based on the clock signal 203C.

[0070] According to one embodiment, in the third mode, each enabled register receives 8 bits of data from the input data 209. For example, the register 403A included in the first group of registers receives data D15 to data D08 of bit N and outputs retimed data D15 to retimed data D08. In the second group of registers, pairs of second registers are connected to each other in series to retime the output of the second half of the input data 209 based on the clock signal 203C. For example, the register 403H receives data D07 to data D00 for bit N and outputs data D07 to data D00 to the input D of the register 403L, and the register 403L further delays the output of data D07 to data D00 to generate retimed data D07 to retimed data D00. The second group of registers is configured to delay the output of the second half of the input data so that the input data 209 can be serially output by the configurable retimer 301 during one cycle of the clock signal 203C. For example, during the "high" level of the clock signal 203C, data D15 to data D08 for bit N are output by the configurable retimer 301, and during the "low" level of the clock signal 203C, data D07 to data D00 for bit N are output by the configurable retimer 301, which will be further described below.

[0071] Figure 6B During the third mode of the transmitter device 101 according to an embodiment, Figure 3 . In one embodiment, during a third mode in which the transmitter device 101 transmits data at a third data rate corresponding to one-fourth of the maximum data rate of the transmitter device 101 (e.g., a 16G baud rate), all of the configurable MUXs 303A to 303G are enabled. However, a first portion of the plurality of switches 407 included in each of the configurable MUXs 303 is enabled, and a second portion of the plurality of switches 407 is disabled. Figure 6B As shown, in one example, a first portion of switches 407 enabled during the third mode includes switches 407A and 407H, and a second portion of switches 407 disabled during the third mode includes switches 407B to 407G.

[0072] The enabled switch 407 is configured to sequentially output the retimed data 211 input to the enabled switch 407 as serialized data 217 based on the clock signal 203B. In one embodiment, during the third mode, the clock signal 203B includes a portion of the selection signal included in the first mode. For example, during the third mode, the clock signal 203B includes the selection signal sel <7> and select signal sel <0> Each enabled switch 407 is configured to output a portion of the retimed data 211 input to the switch 407 in response to one of the selection signals to generate the serialized data 217. For example, the switch 407A is enabled in response to the selection signal sel <7> , outputs the retimed data D15 to D08, and the switch 407H responds to the selection signal sel <0> , outputting the retimed data retimed D07 to retimed D00 to generate serialized data 217. The disabled switches 407B to 407G do not receive any retimed data during the third mode, and thus do not output serialized data during the third mode.

[0073] Figure 6C 2 is a waveform diagram of the clock signal 203 of the transmitter device 101 operating in the third mode according to an embodiment. As described above, during the third mode, a portion of the register 403 included in each of the configurable retimers 301 is enabled, and a portion of the switch 407 included in each of the configurable MUXs 303 is enabled. During the third mode, the configurable clock signal 203C that controls the retiming of the input data 209 is, for example, a 16T clock signal. One cycle of the clock signal 203C includes a first portion 601 corresponding to a "low" level of the clock signal 203C and a second portion 603 corresponding to a "high" level of the clock signal 203C.

[0074] The input data 209 input to the configurable retimers 301A to 301G includes data D15 to data D00 for each bit N, where N is an integer from 0 to 6. During the third mode, during the first portion 601 of the clock signal 203C, all of the input data 209 cannot be output by the configurable timer circuit 111. In one embodiment, the plurality of configurable retimers 301 included in the configurable retimer circuit 111 retimes the input data 209 so that a first half of the input data (e.g., D15 to D08 for bit N of the input data 209) is output by the configurable retimer 301 as a first half of the retimed data 211A during a first portion 601 of the clock signal 203C, and a second half of the input data 209 (e.g., D07 to D00 for bit N of the input data 209) is output by the configurable retimer 301 as a second half of the retimed data 211B during a second portion 603 of the clock signal 203C, as shown in FIG. Figure 6C shown.

[0075] The retimed data 211 (e.g., the first half of the retimed data 211A and the second half of the retimed data 211B) is input to the configurable MUX 303A to the configurable MUX 303G. During the third mode, each of the configurable MUX 303A to the configurable MUX 303G is responsive to a selection signal sel <7> and select signal sel <0> The clock signal 203B of the configurable MUX 303A to the configurable MUX 303G is selected to sequentially output the retimed data 211 as the serialized data 217. For example, the configurable MUX 303A to the configurable MUX 303G are responsive to the selection signal sel <7> , outputting serialized data 217A including retimed data D15 to D08 for bit N from the first half of the retimed data 211A, and configurable MUX 303A to configurable MUX 303G in response to the selection signal sel <0> , outputting serialized data 217B including retimed data D07 to D00 for bit N from the second half 211B of the retimed data.

[0076] Method flow chart

[0077] Figure 7 is a flowchart of a method for data transmission of the transmitter device 101 according to one embodiment. Note that in other embodiments, Figure 7 Additional steps beyond those shown in .

[0078] In one embodiment, the transmitter device 101 sets 701 a data rate at which the transmitter device operates. For example, the data rate may be selected from a plurality of different data rates corresponding to a maximum data rate of the transmitter device 101 , a minimum data rate of the transmitter device, and an intermediate data rate of the transmitter device 101 .

[0079] According to the set data rate, a configurable timer circuit 111 included in the transmitter device 101 is configured 703. In one embodiment, the configurable timer circuit 111 is configured by enabling at least a portion of each configurable retimer 301 and enabling a portion of each configurable MUX 303 included in the configurable timer circuit 111 according to the data rate.

[0080] The transmitter device 101 receives 705 input data for transmission and retimes 707 the input data for transmission using the configuration of the configurable timer circuit 111. The transmitter device 101 transmits 709 the retimed data retimed by the configurable timer circuit 111.

[0081] Additional Configuration Notes

[0082] Throughout this specification, multiple instances can be implemented as components, operations or structures described as single instances. Although the separate operations of one or more methods are shown and described as independent operations, the one or more separate operations can be performed in parallel, and there is no need to perform the operations in the order shown. The structure and function presented as independent components in the example configuration can be implemented as a combined structure or component. Similarly, the structure and function presented as independent components can be implemented as independent components. These and other variations, modifications, additions and improvements all fall within the scope of this paper theme.

[0083] As used herein, any reference to "one embodiment" or "an embodiment" means that a particular element, feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in one embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment.

[0084] Some embodiments may be described using the expressions "coupled" and "connected" and their derivatives. For example, some embodiments may be described using the term "coupled" to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other. Embodiments are not limited to this context.

[0085] As used herein, the terms "comprises," "comprising," "includes," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive or and not an exclusive or. For example, a condition A or B is satisfied by any of the following: A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), and both A and B are true (or exists).

[0086] In addition, "a" or "an" is used to describe elements and components of the embodiments herein. This is done only for convenience and to give a general sense of the present disclosure. Unless it is obvious that it is meant otherwise, the description should be understood to include one or at least one, and the singular also includes the plural.

[0087] After reading this disclosure, those skilled in the art will recognize additional alternative structural and functional designs for a receiver having an ADC with an adjustable sampling clock through the principles disclosed herein. Therefore, although specific embodiments and applications have been shown and described, it should be understood that the disclosed embodiments are not limited to the precise construction and components disclosed herein. Various modifications, changes and variations can be made to the arrangement, operation and details of the methods and apparatus disclosed herein without departing from the spirit and scope defined by the appended claims, which will be apparent to those skilled in the art.< / n>

Claims

1. A transmitter device, comprising: a clock circuit configured to generate a clock signal associated with a data rate of the transmitter device; a configurable timer circuit comprising a plurality of retimers configured to receive input data and adjust timing of the input data according to the clock signal to generate retimed input data; as well as a transmitter circuit coupled to a communication channel, the transmitter circuit being configured to transmit serialized data based on the retimed input data to a receiver device through the communication channel at the data rate, wherein, in response to the transmitter device being configured to operate at a data rate that is a fraction of the maximum data rate of the transmitter device, a portion of at least one of the plurality of retimers is enabled to adjust the timing of the input data and a remainder of the at least one of the plurality of retimers is disabled.

2. The transmitter device according to claim 1, wherein The input data received by each of the plurality of retimers is associated with a different bit of the input data.

3. The transmitter device according to claim 1, wherein: Each of the plurality of retimers comprises a plurality of registers arranged into a plurality of rows of registers, the plurality of registers comprising: a first set of registers, each register in the first set configured to receive a different portion of the input data and output a corresponding portion of the retimed input data according to the clock signal; and A second group of registers includes a plurality of second register pairs, wherein a first register included in each second register pair is configured to receive different portions of the input data and output corresponding portions of the retimed input data to a second register included in the pair and connected in series with the first register, and the second register in each pair delays output of the corresponding portion of the retimed input data according to the clock signal.

4. The transmitter device according to claim 3, wherein: In response to the data rate being a fraction of the maximum data rate, a total number of enabled registers included in each of the plurality of retimers is less than a total number of enabled registers during the maximum data rate of the transmitter device.

5. The transmitter device according to claim 4, wherein: In response to the data rate being half the maximum data rate, half of the plurality of rows of registers are enabled and a remaining half of the plurality of rows of registers are disabled, The enabled half of the plurality of rows includes registers in the first group of registers and a plurality of second register pairs in the second group of registers.

6. The transmitter device according to claim 4, wherein: In response to the data rate being one quarter of the maximum data rate, one quarter of the plurality of rows of registers are enabled and the remaining rows of registers are disabled, The enabled quarter of the plurality of rows includes a register of the first group of registers and a second register pair of the second group of registers.

7. The transmitter device according to claim 3, wherein: The configurable timer circuit also includes a plurality of multiplexers, each of the plurality of multiplexers being coupled to a corresponding retimer of the plurality of retimers and configured to receive the retimed input data output by the corresponding retimer and select the retimed input data to be output as part of the serialized data based on a plurality of selection signals.

8. The transmitter device according to claim 7, wherein: Each of the plurality of multiplexers includes a plurality of switches, each of the plurality of switches being configured to receive a different portion of the retimed input data received from the corresponding retimer and to output a different portion of the serialized data in response to a corresponding select signal of the plurality of select signals.

9. The transmitter device according to claim 8, wherein: In response to the data rate being a fraction of the maximum data rate, a total number of enabled switches included in each of the plurality of multiplexers is based on a ratio of the data rate to the maximum data rate of the transmitter device.

10. The transmitter device according to claim 9, wherein: In response to the data rate being half the maximum data rate, half of the plurality of switches in each of the plurality of multiplexers are enabled and a remaining half of the switches are disabled.

11. The transmitter device according to claim 10, wherein: In response to the data rate being one quarter of the maximum data rate, one quarter of the plurality of switches in each of the plurality of multiplexers are enabled and the remaining switches of the plurality of switches are disabled.

12. The transmitter device according to claim 11, wherein The clock circuit is configured to generate a plurality of different clock signals, each clock signal being associated with a respective data rate of a plurality of data rates of the transmitter device.

13. The transmitter device according to claim 12, wherein: A first clock signal among the plurality of clock signals is associated with the maximum data rate and has a first frequency, a second clock signal among the plurality of clock signals is associated with one quarter of the maximum data rate and has a second frequency less than the first frequency, and a third clock signal among the plurality of clock signals is associated with half of the maximum data rate and has a third frequency less than the first frequency but greater than the second frequency.

14. A method of a transmitter device comprising a configurable timer circuit, the configurable timer circuit comprising a plurality of retimers, the method comprising: setting a data rate at which the transmitter device operates from a plurality of data rates; in response to the data rate being a fraction of a maximum data rate of the transmitter device, reconfiguring the configurable timer circuit by enabling a portion of at least one of the plurality of retimers and disabling a remainder of the at least one of the plurality of retimers; receiving input data to be transmitted by the transmitter device at the data rate; adjusting the timing of the input data using an enabled portion of at least one retimer of the plurality of retimers according to a clock signal associated with the data rate to generate retimed input data; as well as Serialized data based on the retimed input data is transmitted to a receiver device over a communication channel at the data rate.

15. The method according to claim 14, wherein: Each of the plurality of retimers receives input data associated with a different bit of the input data.

16. The method according to claim 14, wherein: Each of the plurality of retimers includes a plurality of registers arranged into a plurality of rows of registers, and the method further includes: In response to the data rate being half of the maximum data rate, half of the plurality of rows of registers included in each of the plurality of retimers are enabled, and a remaining half of the plurality of rows of registers included in each of the plurality of retimers are disabled.

17. The method according to claim 16, further comprising: In response to the data rate being one quarter of the maximum data rate, one quarter of the plurality of rows of registers included in each of the plurality of retimers are enabled, and the remaining rows of registers included in each of the plurality of retimers are disabled.

18. The method according to claim 14, wherein: The configurable timer circuit further includes a plurality of multiplexers coupled to the plurality of retimers, each of the plurality of multiplexers including a plurality of switches, each of the plurality of switches configured to: receive a different portion of the retimed input data received from a corresponding retimer and output a different portion of the serialized data in response to a corresponding select signal of the plurality of select signals, the method further comprising: In response to the data rate being half the maximum data rate, half of the plurality of switches in each of the plurality of multiplexers are enabled to select different portions of the retimed input data to output as part of the serialized data, and a remaining half of the switches are disabled.

19. The method according to claim 18, further comprising: In response to the data rate being one quarter of the maximum data rate, one quarter of the plurality of switches of each of the plurality of multiplexers are enabled to select different portions of the retimed input data to output as portions of the serialized data, and remaining switches of the plurality of switches are disabled.

20. The method according to claim 19, further comprising: generating a plurality of clock signals, each clock signal being associated with a different data rate among the plurality of data rates, the plurality of clock signals comprising a first clock signal, a second clock signal, and a third clock signal, wherein the first clock signal is associated with the maximum data rate and has a first frequency, the second clock signal is associated with one quarter of the maximum data rate and has a second frequency less than the first frequency, and the third clock signal is associated with half of the maximum data rate and has a third frequency less than the first frequency but greater than the second frequency.

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