Semiconductor device and method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of suppressing positional displacement when an electrode terminal is mounted on a circuit pattern of an insulating substrate. A semiconductor device is provided with: an insulating substrate (1) having a circuit pattern (3) formed on the upper surface thereof; a semiconductor element (5) mounted on the circuit pattern (3); and an electrode terminal (6) that has a joining section (6a) joined to the upper surface of the circuit pattern (3) and that is electrically connected to the semiconductor element (5), a fitting section is provided in the circuit pattern (3), and a section to be fitted that fits into the fitting section is provided on the joining section (6a) of the electrode terminal (6).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a pad having a step is formed on an insulating substrate, and a lead (equivalent to an electrode terminal) is mounted in accordance with the step of the pad, thereby preventing the position of the lead from being misaligned (for example, see Patent Document 1). Prior art literature Patent Literature

[0003] Patent Document 1: Japanese Patent Publication No. 5-67871 Summary of the invention Technical problem to be solved by the invention

[0004] However, the step of the pad described in Patent Document 1 is provided to suppress the flow of solder during the reflow process, and the size of the step is formed to be larger than the size of the joint portion of the lead by the size of the solder applied on the step. Therefore, when the lead is placed on the step of the pad mechanically or manually, positional deviation is likely to occur. In the case of positional deviation, there is a problem of poor quality of the semiconductor device.

[0005] Therefore, an object of the present disclosure is to provide a technology capable of suppressing positional deviation when an electrode terminal is mounted on a circuit pattern of an insulating substrate. Technical means for solving technical problems

[0006] The semiconductor device involved in the present disclosure includes: an insulating substrate with a circuit pattern formed on the upper surface; and an electrode terminal having a joining portion joined to the upper surface of the circuit pattern, a fitting portion is provided in the circuit pattern, and a fitting portion that fits with the fitting portion is provided in the joining portion of the electrode terminal. Effects of the Invention

[0007] According to the present disclosure, by fitting the fitted portion of the electrode terminal into the fitting portion of the circuit pattern, it is possible to suppress positional deviation when the electrode terminal is mounted on the circuit pattern of the insulating substrate.

[0008] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a schematic cross-sectional view of a junction portion of an electrode terminal included in the semiconductor device according to the first embodiment and its surroundings. Figure 2 It is a schematic cross-sectional view of a junction portion of an electrode terminal included in a semiconductor device according to a second embodiment and its surroundings. Figure 3 It is a schematic cross-sectional view of a joint portion of an electrode terminal provided in a semiconductor device according to a third embodiment and its periphery before caulking. Figure 4 It is a schematic cross-sectional view of a joint portion of an electrode terminal provided in a semiconductor device according to a third embodiment and its periphery after caulking. DETAILED DESCRIPTION

[0010] <Implementation method 1> Embodiment 1 will be described below using the drawings. Figure 1 It is a schematic cross-sectional view of a bonding portion 6 a of an electrode terminal 6 included in the semiconductor device according to the first embodiment and its surroundings.

[0011] like Figure 1 As shown, the semiconductor device includes an insulating substrate 1, a semiconductor element 5 and an electrode terminal 6. The insulating substrate 1 includes an insulating layer 2, a circuit pattern 3 and a base plate 4. The insulating layer 2 is made of ceramic or the like. A plurality of conductive circuit patterns 3 are provided on the upper surface of the insulating layer 2. The circuit pattern 3 is made of, for example, copper (Cu). A base plate 4 is provided on the lower surface of the insulating layer 2.

[0012] The electrode terminal 6 is bonded to the upper surface of the circuit pattern 3 by a bonding material 7. In addition, on the upper surface of the circuit pattern 3 adjacent to the circuit pattern 3 bonded with the electrode terminal 6, a plurality of semiconductor elements 5 such as IGBT (Insulated Gate Bipolar Transistor) and FWDI (Free Wheeling Diode) are bonded by solder (not shown). Adjacent circuit patterns 3 and circuit patterns 3 are connected by aluminum wires (not shown). In addition, the insulating substrate 1, the semiconductor element 5 and the electrode terminal 6 are protected by a housing (not shown) and a sealing material such as gel (not shown). As the semiconductor element 5, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be mounted instead of an IGBT. In addition, an SBD (Schottky diode) may be mounted instead of an FWDI.

[0013] The electrode terminal 6 is electrically connected to the semiconductor element 5 via an aluminum wire (not shown). The electrode terminal 6 is made of Al, for example. The electrode terminal 6 includes a joint portion 6a provided on one end side of the electrode terminal 6 and a bent portion 6b bent upward from the joint portion 6a. The joint portion 6a is a portion extending parallel to the upper surface of the circuit pattern 3 and is a portion joined to the upper surface of the circuit pattern 3. The lower surface of the joint portion 6a is planar, and the entire surface is in contact with the circuit pattern 3. A collapsed edge surface 6c protruding downward from the outer peripheral surface is provided in the joint portion 6a. The collapsed edge surface 6c is provided on a portion or the entire circumference of the outer peripheral surface of the joint portion 6a of the electrode terminal 6. In the case where the collapsed edge surface 6c is provided only on a portion of the outer peripheral surface of the joint portion 6a, it is preferably provided on the front end side of the joint portion 6a. The front end side of the joint portion 6a is Figure 1 The left side, that is, the side opposite to the curved portion 6b.

[0014] A recess 3a that can be engaged with the collapsed edge surface 6c is provided at a portion of the upper surface of the circuit pattern 3 that is joined to the electrode terminal 6. Specifically, the front end of the collapsed edge surface 6c is engaged with the recess 3a. The recess 3a is provided at a position on the upper surface of the circuit pattern 3 that is opposite to the collapsed edge surface 6c, and is formed to a size that can be engaged with the front end of the collapsed edge surface 6c. By engaging the collapsed edge surface 6c with the recess 3a, the electrode terminal 6 is positioned on the circuit pattern 3. Here, the recess 3a is equivalent to the engaging portion, and the collapsed edge surface 6c is equivalent to the engaged portion.

[0015] The bonding material 7 is arranged so as to cover a part of the bonding portion 6a and the bent portion 6b of the electrode terminal 6. The bonding material 7 is, for example, solder.

[0016] Next, the method for forming the collapsed edge surface 6c included in the method for manufacturing a semiconductor device will be simply described without using drawings. First, a metal plate that will become the electrode terminal 6 is arranged in a lower mold. Next, in order to plastically deform the metal plate, a gap is left between the lower mold and the upper mold opposite thereto, and the metal plate is punched. In this way, an electrode terminal 6 having a collapsed edge surface 6c is manufactured. In a general semiconductor device, in order to avoid forming the collapsed edge surface 6c, the gap between the upper mold and the lower mold is set to a minimum to manufacture the electrode terminal 6, but in the present embodiment, the gap between the upper mold and the lower mold is made wider than that to manufacture the electrode terminal 6 having a collapsed edge surface 6c.

[0017] As described above, the semiconductor device according to the first embodiment includes an insulating substrate 1 having a circuit pattern 3 formed on its upper surface and an electrode terminal 6 having a joint portion 6a joined to the upper surface of the circuit pattern 3, wherein a fitting portion is provided in the circuit pattern 3, and a fitting portion to be fitted with a collapsed edge surface 6c is provided in the joint portion 6a of the electrode terminal 6. Specifically, the fitting portion is a recess 3a provided in the circuit pattern 3, and the fitting portion is a collapsed edge surface 6c protruding downward from the outer peripheral surface of the joint portion 6a of the electrode terminal 6, and the electrode terminal 6 is positioned in the circuit pattern 3 by fitting the collapsed edge surface 6c with the recess 3a.

[0018] Therefore, by fitting the collapsed edge surface 6c of the fitted portion of the electrode terminal 6 with the recess 3a of the fitting portion of the circuit pattern 3, it is possible to suppress positional deviation when the electrode terminal 6 is mounted on the circuit pattern 3 of the insulating substrate 1. Thus, it is also possible to suppress positional deviation when the circuit pattern 3 and the electrode terminal 6 are joined.

[0019] Furthermore, by providing the collapsed surface 6c on the electrode terminal 6, it is easy to form a solder fillet. This improves the yield of the semiconductor device and improves the durability.

[0020] In addition, in the method for manufacturing a semiconductor device according to the first embodiment, a metal plate to be the electrode terminal 6 is placed in a lower die, and the metal plate is punched with a gap between the lower die and an upper die opposite thereto, so that the metal plate is plastically deformed to form a collapsed edge surface 6c. Therefore, the collapsed edge surface 6c can be formed in the punching process for manufacturing the electrode terminal 6, thereby suppressing an increase in the number of manufacturing processes.

[0021] <Implementation method 2> Next, a semiconductor device according to Embodiment 2 will be described. Figure 2 It is a schematic cross-sectional view of a bonding portion 6a of an electrode terminal 6 and its surroundings provided in a semiconductor device according to Embodiment 2. In Embodiment 2, the same components as those described in Embodiment 1 are denoted by the same reference numerals and their description is omitted.

[0022] like Figure 2 As shown, in the second embodiment, the collapsed edge surface 6c is not provided at the joint portion 6a of the electrode terminal 6 (see Figure 1 ), but the entire lower end portion of the joint 6a functions as the engaged portion.

[0023] The recess 3a provided in the circuit pattern 3 is formed to a size capable of fitting the entire lower end of the joint portion 6a. In addition, the maximum depth of the recess 3a is less than 1 / 2 of the thickness of the circuit pattern 3. More preferably, the maximum depth of the recess 3a is not less than 1 / 4 and not more than 1 / 2 of the thickness of the circuit pattern 3.

[0024] As described above, in the semiconductor device involved in embodiment 2, the embedding portion is a recess 3a provided in the circuit pattern 3, the maximum depth of the recess 3a is less than 1 / 2 of the thickness of the circuit pattern 3, and the embedded portion is the lower end portion of the joint portion 6a of the electrode terminal 6. The electrode terminal 6 is positioned in the circuit pattern 3 by embedding the lower end portion of the joint portion 6a of the electrode terminal 6 with the recess 3a.

[0025] Therefore, by fitting the lower end of the joint portion 6a, which is the fitted portion of the electrode terminal 6, with the recess 3a, which is the fitting portion of the circuit pattern 3, it is possible to suppress positional deviation when the electrode terminal 6 is mounted on the circuit pattern 3 of the insulating substrate 1. Thus, it is also possible to suppress positional deviation when the circuit pattern 3 and the electrode terminal 6 are joined.

[0026] Furthermore, by reducing the thickness of the portion of the circuit pattern 3 bonded to the electrode terminal 6, the thermal resistance from the electrode terminal 6 to the heat sink (not shown) mounted on the lower surface of the substrate 4 is reduced. As a result, the heat generated in the electrode terminal 6 can be easily dissipated from the heat sink.

[0027] <Implementation method 3> Next, a semiconductor device according to Embodiment 3 will be described. Figure 3 It is a schematic cross-sectional view of a joining portion 6 a of an electrode terminal 6 provided in a semiconductor device according to the third embodiment and its surroundings before caulking. Figure 4 It is a schematic cross-sectional view of a bonding portion 6a of an electrode terminal 6 and its surroundings after caulking in a semiconductor device according to Embodiment 3. In Embodiment 3, the same components as those described in Embodiments 1 and 2 are denoted by the same reference numerals and their description is omitted.

[0028] like Figure 3 As shown, in the third embodiment, a protrusion 8 protruding upward is provided on the upper surface of the circuit pattern 3. The protrusion 8 is formed in a columnar or cylindrical shape and is formed integrally with the circuit pattern 3. The vertical length of the protrusion 8 is formed to be longer than the thickness of the joint 6a of the electrode terminal 6.

[0029] The through hole 6d capable of fitting the protrusion 8 is provided at the joint portion 6a of the electrode terminal 6. In order to allow the protrusion 8 to deform when the front end of the protrusion 8 is riveted, the diameter of the through hole 6d is formed to be slightly larger than the diameter of the protrusion 8. By fitting the through hole 6d and the protrusion 8, the electrode terminal 6 is positioned on the circuit pattern 3. Then, after being positioned, as shown in FIG. Figure 4 As shown, the tip of the protrusion 8 is riveted in a state of being fitted into the through hole 6d. Thus, the electrode terminal 6 and the circuit pattern 3 are connected without using the bonding material 7 (see Figure 1 Here, the protrusion 8 corresponds to the fitting portion, and the through hole 6d corresponds to the fitted portion.

[0030] Next, a method for riveting the front end of the protrusion 8 included in the method for manufacturing the semiconductor device will be briefly described. Figure 3 As shown in FIG. 1 , the electrode terminal 6 is arranged on the circuit pattern 3 so that the through hole 6d of the bonding portion 6a is engaged with the protrusion 8 of the circuit pattern 3. Next, a load is applied to the tip of the protrusion 8 using an ultrasonic bonding tool (not shown). As a result, Figure 4 As shown, the front end of the projection 8 is riveted.

[0031] As described above, in the semiconductor device involved in embodiment 3, the engaging portion is a protrusion 8 provided in the circuit pattern 3, and the engaged portion is a through hole 6d provided in the joint 6a of the electrode terminal 6. The electrode terminal 6 is positioned in the circuit pattern 3 by engaging with the protrusion 8 through the through hole 6d.

[0032] Therefore, by fitting the through hole 6d of the joint portion 6a, which is the fitted portion of the electrode terminal 6, with the protrusion 8, which is the fitting portion of the circuit pattern 3, it is possible to suppress positional deviation when the electrode terminal 6 is mounted on the circuit pattern 3 of the insulating substrate 1. Thus, it is also possible to suppress positional deviation when the circuit pattern 3 and the electrode terminal 6 are joined.

[0033] Furthermore, since the tip end of the protrusion 8 is swaged in a state of being fitted into the through hole 6 d , the circuit pattern 3 and the electrode terminal 6 can be joined without using the joining material 7 .

[0034] In addition, the electrical connection between the electrode terminal 6 and the circuit pattern 3 is also facilitated, which is difficult to bond without increasing the temperature. In addition, the reliability of the bonding between the electrode terminal 6 and the circuit pattern 3 is improved by riveting the front end of the protrusion 8 while it is engaged with the through hole 6d.

[0035] Furthermore, since the protrusion 8 is integrated with the circuit pattern 3 , it is not necessary to join the protrusion 8 with the circuit pattern 3 , so the reliability of the joining between the electrode terminal 6 and the circuit pattern 3 is further improved.

[0036] Furthermore, since the protrusion 8 is formed in a columnar or cylindrical shape, it is possible to closely contact the through hole 6d by uniform deformation of the protrusion 8. Thus, the connection between the circuit pattern 3 and the electrode terminal 6 becomes more secure.

[0037] The present disclosure has been described in detail, but the above description is in all aspects illustrative and not restrictive, and it is understood that numerous modifications not shown are conceivable.

[0038] The embodiments can be freely combined, or can be appropriately modified or omitted. Description of symbols

[0039] 1 insulating substrate, 3 circuit pattern, 3a recess, 6 electrode terminal, 6a bonding portion, 6c collapsed edge surface, 6d through hole, 8 protrusion.

Claims

1. A semiconductor device, characterized in that: include: An insulating substrate having a circuit pattern formed on an upper surface; as well as an electrode terminal having a bonding portion bonded to an upper surface of the circuit pattern, A fitting portion is provided in the circuit pattern, The joint portion of the electrode terminal is provided with an engaged portion that engages with the engaging portion.

2. The semiconductor device according to claim 1, wherein The engaging portion is a recess provided in the circuit pattern. The engaged portion is a collapsed surface that protrudes downward from the outer peripheral surface of the joint portion of the electrode terminal. The electrode terminal is positioned on the circuit pattern by the engagement of the collapsed surface with the recess.

3. The semiconductor device according to claim 1, wherein: The engaging portion is a recess provided in the circuit pattern. The maximum depth of the depression is less than 1 / 2 of the thickness of the circuit pattern, The engaged portion is a lower end portion of the engaging portion of the electrode terminal, The electrode terminal is positioned with respect to the circuit pattern by the lower end portion of the joint portion of the electrode terminal being fitted into the recess.

4. The semiconductor device according to claim 1, wherein: The engaging portion is a protrusion provided on the circuit pattern. The engaged portion is a through hole provided in the joint portion of the electrode terminal, The electrode terminal is positioned on the circuit pattern by the through hole being engaged with the protrusion.

5. The semiconductor device according to claim 4, wherein: The front end portion of the protrusion is caulked in a state of being fitted into the through hole.

6. The semiconductor device according to claim 5, wherein: The protrusion is integrated with the circuit pattern.

7. The semiconductor device according to any one of claims 4 to 6, wherein: The protrusion is formed in a columnar or cylindrical shape.

8. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to claim 2, characterized in that: A metal plate to be the electrode terminal is placed in a lower die, and the metal plate is punched out with a gap between the lower die and an upper die facing the lower die, thereby plastically deforming the metal plate to form the collapsed surface.

9. A method for manufacturing a semiconductor device, for manufacturing the semiconductor device according to claim 5, characterized in that: The electrode terminal is arranged on the circuit pattern, and a load is applied to the tip of the protrusion using an ultrasonic bonding tool to rivet the tip of the protrusion so that the through hole of the bonding portion is engaged with the protrusion of the circuit pattern.

Images