Method for realizing digital wave control of phased array radar

Abstract

The invention relates to the technical field of phased array radars, in particular to an implementation method for digital wave control of a phased array radar. A data transceiving scheduling module is respectively connected with a TR assembly and a data exchange module through optical fibers to complete wave control code analysis and storage scheduling; the storage control module is used for controlling the N groups of storage units to work according to a radar time sequence, and only one storage unit needs to be controlled to work in one PRI period; the storage unit stores wave control codes of each TR subarray, each group comprises M RAM storage units, the main function can be realized by an internal IP core RAM of the FPGA, and external storage chips such as DDR3 / SRAM and the like can also be externally connected to realize. According to the invention, the radar can randomly define the beam direction of each channel of the radar in real time according to the requirements of a user.

Description

Technical Field

[0001] The present invention relates to the technical field of phased array radars, and in particular to a method for realizing digital wave control of phased array radars. Background Art

[0002] Phased array radar is a new type of radar that mainly uses electronic scanning. It is deeply favored by users for its advantages of short beam forming time and flexible beam pointing change. It is the main direction of current radar research and development.

[0003] Phased array radars currently include analog phased array and digital phased array radars. Among them, digital phased array radars are more advanced and more complex. They use digital multi-beam forming technology to form wide / narrow beams in space by individually controlling the amplitude, phase, waveform and other parameters of each TR channel, scanning and tracking specific targets. This radar has a large amount of data and high real-time data, making it difficult to develop. However, it has the advantages of fast beam scanning, flexible spatial directivity, simultaneous synthesis of multiple independent receiving beams, and real-time detection and tracking of multiple targets. It has been increasingly widely used in both military and civilian fields. Existing digital phased array radars have problems such as inflexible parameter configuration modification and low real-time performance when working.

[0004] The present invention mainly solves the difficulties of digital phased array radar, such as large amount of beam control data, high real-time requirements, and data synchronization. Its application can also be extended to existing parabolic radars and analog phased array radars. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a method for realizing digital beam control of phased array radar. The present invention can not only dispatch the whole radar to form a wide beam to scan the target, but also dispatch some TR components in real time to form a separate narrow beam to track a specific target, thereby increasing the flexibility and convenience of using the phased array radar.

[0006] The technical solution of the present invention is: a method for realizing digital wave control of phased array radar, characterized in that:

[0007] Step 1, set the wave control code parameters and transmit them to the wave control code calculation module;

[0008] Step 2: The wave control code calculation module analyzes the parameters and calculates the wave control codes of L groups of M TR components; and stores all the wave control codes;

[0009] Step 3: The wave control code calculation module sends a group of wave control codes from the stored database to the data exchange module, and the data exchange module unpacks the received data to obtain the nth group of wave control codes;

[0010] Step 4, the data exchange module sends the nth group of wave control codes to the data transceiver scheduling module of the FPGA module; the data transceiver scheduling module taps the data and restores the nth group of wave control codes; extracts valid data from the data according to the frame header and the cutoff code, and parses the values ​​of n and m; according to the value of n, the group of wave control codes will be stored in the corresponding storage unit n, and according to the value of m, the wave control codes will be stored in the corresponding mth RAM, and the corresponding data will be stored in the address of the RAM according to the data / address line;

[0011] Step 5: The host computer sets the beam n working times a n , the working times are sent to the data transceiver scheduling module, and the data is tapped to obtain the working times a n , the number of work times a n Send to storage control module;

[0012] The storage control module controls the storage unit n to select one of the S51 and S52 schemes:

[0013] S51, controlled by FIFO: FIFO continuously receives a n Each PRI executes a read FIFO, reads storage unit n, and generates beam n; during this period, writes a to the FIFO. n+1 Read the instruction of beam n+1 again; execute a n After that, at the next PRI, FIFO will output the instruction to read beam n+1, and so on, completing the function of the storage control module;

[0014] S52, controlled by RAM: RAM receives beams 1-N for a1-a1 times N , stored at address 1 to address N; define a counter to count PRI and read data a at RAM address n n , then next a n During a PRI period, the control reads storage unit n, generates beam n, and each PRI counter increases by 1; when the counter is equal to a n When the counter is reset, the next PRI reads the data a at RAM address n+1. n+1 , the counter recounts a n+1 The functions of the storage control module are completed.

[0015] Step 6: During a PRI period, the storage control module controls the storage unit n to read a group of wave control codes; the FPGA module receives the wave control code transmission signal generated by the radar, and then sends the group of wave control codes to the corresponding TR components through M optical fibers at the same time;

[0016] Step 7: Read the number of times a in the storage control module according to the selected S51 or S52 solution. n, execute the control method of step 6, cycle work a n After the execution is completed, the storage control module automatically switches to the control of forming beam n+1;

[0017] Step 8, the echo data generated by the TR component is transmitted to the FPGA module through optical fiber multiplexing. After receiving the data, the FPGA module splits the optical fiber data into multi-channel data; by identifying the data frame header, the data in the multi-channel is beamformed in the azimuth and elevation planes to obtain DBF data, the data frame header is inserted into the DBF data and transmitted to the data exchange module, and the data exchange module transmits it to the wave control code calculation module;

[0018] Step 9: When the wave control code calculation module identifies that the wave control code n has been sent through the TR control module based on the frame header information in the returned data, it sends subsequent wave control codes.

[0019] The beneficial effects of the present invention are: making the multi-beam scheduling of the phased array radar flexible when working, the beam pointing is adjustable according to the parameter setting, the parameter configuration modification is flexible and convenient, and the real-time performance is high, so that the radar can arbitrarily and in real time define the beam pointing of each channel of the radar according to the needs of the user. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The figure is a schematic diagram of the overall structure of a method for realizing digital wave control of a phased array radar.

[0021] Figure 2 Construct a graph for a storage unit. DETAILED DESCRIPTION

[0022] In order to make the technical solution, implementation process and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The design requirements in the specific embodiments described here are only used as a design reference for the present invention and are not used to limit the present invention.

[0023] In the embodiments, the difference between "a group", "one" and "a packet" should be understood. The "frame header" and "cutoff code" in the data are expressed in the same way, and the content can be defined by the implementer and will not conflict with the data that may be contained in the data. The implementer can correctly parse out the valid data.

[0024] The present invention provides a method for realizing digital wave control of phased array radar, using Figure 1 A digital wave control device for phased array radar. The device comprises: a host computer, a wave control code calculation module, a data exchange module, an FPGA module and a TR control module. The FPGA module of the present invention comprises a data transceiver scheduling module, a storage control module and a storage unit. The FPGA module is also connected to a radar wave control signal for receiving the radar wave control signal.

[0025] The host computer of the present invention is mainly a radar wave control terminal, which is connected to the wave control code calculation module by a 10 Gigabit network and can be customized according to user needs. When the host computer sets the working mode, the radar should automatically switch to the corresponding working sequence.

[0026] The wave control code calculation module of the present invention is a server, which is implemented by a CPU or a GPU and is suitable for large-scale data calculation radar wave control codes. The data exchange module of the present invention communicates with the wave control code calculation module by PCIE, and the wave control code calculation module detects the number of frame headers in the received data, determines the number of radar working cycles and the beam pointing information of the data, and realizes the cycle synchronization between the wave control code calculation module and the FPGA module.

[0027] The data conversion module of the present invention mainly completes the data conversion between optical fiber communication and PCIE or Rapidio, and does not perform data parsing and storage. In actual use, valid data can be parsed for forwarding (for example, K codes and invalid bytes in optical communication are eliminated), reducing the amount of data and improving transmission efficiency.

[0028] The FPGA module of the present invention is a board with FPGA as the main chip, and its structure includes power supply, optical module, etc., which plays a connecting role. It includes: 1. Data transceiver scheduling module, which is connected to TR component and data exchange module respectively through optical fiber to complete wave control code analysis and storage scheduling. 2. Storage control module, whose main function is to control N groups of storage units to work according to radar timing, and only one storage unit needs to be controlled to work in one PRI cycle. 3. Storage unit, which mainly stores the wave control code of each TR sub-array, and its number is divided into N groups (N≥2), and each group consists of M RAM storage units (M=TR number). Its main function can be realized by FPGA internal IP core RAM, and can also be realized by external storage chips such as DDR3 / SRAM. When using external storage chips, the storage space can be divided according to the chip address bits to form N groups of storage units. While completing the above functions, the FPGA module can also complete functions such as DBF data synthesis.

[0029] The TR control module of the present invention receives wave control code data including frequency code, amplitude code and phase code, downlink TR status, AD sampling and post-filtering data, etc. through its internal FPGA via high-speed optical fiber.

[0030] A set of wave control codes of the present invention includes wave control codes of M TR components and is stored in a storage unit; one wave control code only controls the direction of one beam of one TR component, and a set of wave control codes composed of all TR components can form a set of directional beams in space. The FPGA module is connected to the TR component through an optical fiber, and one TR component is connected to two optical fibers to respectively complete the transmission and reception of data, thereby realizing real-time synchronous control of all TR components of the radar array.

[0031] The data transmission between the modules of the present invention needs to be customized according to the communication protocol. The sending end can accurately send data according to the communication protocol and data format, and the receiving end can accurately receive the data and parse out the valid data.

[0032] A method for implementing digital wave control of a phased array radar of the present invention comprises the following steps:

[0033] Step 1: Set the wave control code parameters and transmit them to the wave control code calculation module.

[0034] The host computer sets the radar working mode, and the radar generates corresponding timing signals such as PRI according to the working mode. Then the host computer performs beam scheduling control, sets parameters such as beam pointing, beam number L, beam width, working frequency, etc., and sends the parameters to the wave control code calculation module through the 10 Gigabit network. Set the working times of each group of wave control codes a n The working times can be sent synchronously or sent by the host computer during working and then executed in step 5.

[0035] Step 2: The wave control code calculation module analyzes the parameters and calculates the wave control codes of L groups of M TR components according to the requirements. The wave control code related parameters include: frequency code, waveform code, transmission DBF coefficient, delay compensation code, correction coefficient, reception DBF coefficient, etc. That is, L*M wave control codes are generated, and the module stores all the wave control codes.

[0036] The wave control code calculation module is a server, which is implemented by CPU or GPU. It is suitable for large-scale data calculation of radar wave control codes. It is connected to the data exchange module through the PCIE interface, reducing the calculation amount and storage resources of the FPGA module.

[0037] Step 3: The wave control code calculation module packages and sends a group of wave control codes from the stored database to the data exchange module at a time. The data exchange module unpacks the received data to obtain the nth group of wave control codes (each group of wave control codes points to one wave position). Figure 1 The data exchange module in the PCIE interface is used. The data adopts a mutually defined protocol, as shown in Table 1. A group of wave control codes includes M wave control codes, that is, M wave control codes as shown in Table 1 are sent at a time, and the value of m is 1 to M.

[0038] Table 1

[0039]

[0040]

[0041] Step 4, the data exchange module sends the nth group of wave control codes to the data transceiver scheduling module of the FPGA module through the optical fiber. The data transceiver scheduling module taps the data and restores the nth group of wave control codes. According to the frame header and the cutoff code in the data, the valid data is extracted and the values ​​of n and m are parsed. According to the value of n, the group of wave control codes will be stored in the corresponding storage unit n, and according to the value of m, the wave control code will be stored in the corresponding mth RAM, and the corresponding data will be stored in the address of the RAM according to the data / address line. Each address of each RAM corresponds to a parameter of a wave control code, for example, address 1 stores the frequency code, address 2 stores the waveform code, and address 3 stores the transmission DBF coefficient, etc.

[0042] Step 5: The host computer sets the beam n working times a n , can be sent alone or packaged with the beam control code of beam n, the working number is sent to the data transceiver scheduling module, and the data is tapped to obtain the working number a n , the number of work times a n Sent to the storage control module.

[0043] The storage control module controls the storage unit n. The embodiment designs two control methods. The implementer can choose one of the S51 and S52 schemes according to their own needs:

[0044] S51, controlled by FIFO. FIFO continuously receives a n Each PRI executes a read FIFO, reads storage unit n, and generates beam n. During this period, a is written to the FIFO. n+1 Read the instruction of beam n+1 again. Execute a n After that, at the next PRI, FIFO will output the instruction to read beam n+1, and so on, thus completing the function of the storage control module.

[0045] S52, controlled by RAM. RAM receives beams 1-N for a1-a1 times. N , stored at address 1 to address N. Define a counter to count PRI. Read data a at RAM address n n , then next a n During a PRI period, the control reads storage unit n, generates beam n, and each PRI counter increases by 1. When the counter is equal to a n When the counter is reset, the next PRI reads the data a at RAM address n+1. n+1 , the counter recounts a n+1 times, and so on, to complete the functions of the storage control module.

[0046] The S51 control method is simple. You only need to write control instructions to the FIFO multiple times. The FIFO will automatically read the control command in each PRI according to the first-in first-out principle, but the amount of data sent is large. The S52 control method is more complicated. The number of reads must be stored in the RAM, and the PRI counter will switch the control command. However, the amount of data is small, and only a set of read times a1-a N The user can flexibly select a solution to control the system according to the requirements of radar-related operations.

[0047] Step 6. During a PRI period, the storage control module controls the storage unit n to read a group of wave control codes. When the FPGA module receives the wave control code transmission signal generated by the radar, it simultaneously sends the group (M) of wave control codes to the corresponding TR component through M optical fibers. The TR component parses the wave control code and restores it to information such as frequency code, waveform code, and transmission DBF coefficient. When receiving the corresponding trigger signal, the working unit in the TR component uses the group of information to generate the corresponding beam n.

[0048] Step 7: Read the number of times a in the storage control module according to the selected S51 or S52 solution. n , execute the control method of step 6, cycle work a n times, you can achieve a n After the formation of secondary beam n is completed, the storage control module automatically switches to the control of forming beam n+1.

[0049] Step 8, the echo data generated by the TR component is transmitted to the FPGA module through optical fiber multiplexing. After receiving the data, the FPGA module splits the optical fiber data into multiple channel data. By identifying the data frame header, the data in the multiple channels are beamformed in the azimuth and elevation planes to obtain DBF data. The data frame header is inserted into the DBF data (the data frame header contains information such as data length, pulse sequence number, beam number and wave position number, so as to quickly distinguish the data content) and transmitted to the data exchange module through optical fiber. The data exchange module transmits it to the wave control code calculation module through PCIE.

[0050] Step 9: Due to the PCIE storage and forwarding, the data exchange module and the wave control code calculation module cannot accurately interact with each PRI. At the same time, there is an uncontrollable delay in data transmission. In order to achieve continuous control, the returned data frame header information needs to be identified. When the wave control code calculation module identifies that the wave control code n has been sent through the TR control module based on the frame header information in the returned data, the subsequent wave control code is sent, as follows:

[0051] The wave control code calculation module detects the pulse sequence number and wave position code in the returned data frame header. When the pulse sequence number of the same wave position code is counted from 1 to a n , indicating that the nth beam is continuously receivedn PRI data. Since there is a time delay in transmitting the array echo data to the wave control code calculation module, the radar beam n has actually completed its work at this time, and the beam has pointed to the beam n+1 or higher. At this time, storage unit n is idle and the wave control code can be rewritten. Repeat steps 3 to 5 to store the N+n group of wave control codes in storage unit n, and beam N+n points to the number a. N+n When the Nth beam is finished working, the storage control module will re-read the storage unit 1 to generate the N+1th beam, and the whole control and normal operation of the L group of beams can be completed in a cycle.

[0052] The various communication methods introduced in this embodiment have been applied in radars, and their communication disadvantages are that the communication protocols are not unified and the data delay is uncertain. The present invention cleverly uses a unified data format to divide the frame header and the cutoff bit, and divides the data into address data and wave control data, so that the wave control code can be flexibly stored. When only part of the wave control code is modified, it is only necessary to send the address and corresponding data in the corresponding valid data, without sending the wave control code of all addresses, thereby reducing the amount of data transmission and improving flexibility.

[0053] The present invention fully adopts high-speed communication, which can meet the rapid scheduling of beams during electronic scanning of phased array radars and is compatible with beam scheduling of mechanical scanning. The optical fiber communication therein has a large data capacity and a fast communication speed, which reduces the multi-channel cables required for traditional SPI, RS232 and other communications. The present invention cleverly reuses RAM, and stores the wave control codes of different beams in the same group of RAM in a time-sharing manner, thereby reducing the consumption of storage resources and improving the flexibility of chip use. The wave control method of the present invention has strong versatility and can increase the number of TR components controlled by the FPGA module board expansion.

Claims

1. A method for realizing digital wave control of a phased array radar, characterized in that: Step 1, set the wave control code parameters and transmit them to the wave control code calculation module; Step 2: The wave control code calculation module analyzes the parameters and calculates the wave control codes of L groups of M TR components; and stores all the wave control codes; Step 3: The wave control code calculation module sends a group of wave control codes from the stored database to the data exchange module, and the data exchange module unpacks the received data to obtain the nth group of wave control codes; Step 4, the data exchange module sends the nth group of wave control codes to the data transceiver scheduling module of the FPGA module; the data transceiver scheduling module taps the data and restores the nth group of wave control codes; extracts valid data from the data according to the frame header and the cutoff code, and parses the values ​​of n and m; according to the value of n, the group of wave control codes will be stored in the corresponding storage unit n, and according to the value of m, the wave control codes will be stored in the corresponding mth RAM, and the corresponding data will be stored in the address of the RAM according to the data / address line; Step 5: The host computer sets the beam n working times a n , the working times are sent to the data transceiver scheduling module, and the data is tapped to obtain the working times a n , the number of work times a n Send to storage control module; The storage control module controls the storage unit n to select one of the S51 and S52 schemes: S51, controlled by FIFO: FIFO continuously receives a n Each PRI executes a read FIFO, reads storage unit n, and generates beam n; during this period, writes a to the FIFO. n+1 Read the instruction of beam n+1 again; execute a n After that, at the next PRI, FIFO will output the instruction to read beam n+1, and so on, completing the function of the storage control module; S52, controlled by RAM: RAM receives beams 1-N for a1-a1 times N , stored at address 1 to address N; define a counter to count PRI and read data a at RAM address n n , then next a n During a PRI period, the control reads storage unit n, generates beam n, and each PRI counter increases by 1; when the counter is equal to a n When the counter is reset, the next PRI reads the data a at RAM address n+1. n+1 , the counter recounts a n+1 The functions of the storage control module are completed. Step 6: During a PRI period, the storage control module controls the storage unit n to read a group of wave control codes; the FPGA module receives the wave control code transmission signal generated by the radar, and then sends the group of wave control codes to the corresponding TR components through M optical fibers at the same time; Step 7: Read the number of times a in the storage control module according to the selected S51 or S52 solution. n , execute the control method of step 6, cycle work a n After the execution is completed, the storage control module automatically switches to the control of forming beam n+1; Step 8, the echo data generated by the TR component is transmitted to the FPGA module through optical fiber multiplexing. After receiving the data, the FPGA module splits the optical fiber data into multi-channel data; by identifying the data frame header, the data in the multi-channel is beamformed in the azimuth and elevation planes to obtain DBF data, the data frame header is inserted into the DBF data and transmitted to the data exchange module, and the data exchange module transmits it to the wave control code calculation module; Step 9: When the wave control code calculation module identifies that the wave control code n has been sent through the TR control module based on the frame header information in the returned data, it sends subsequent wave control codes.

2. The method for realizing digital wave control of a phased array radar according to claim 1, characterized in that: A phased array radar digital wave control device is used, including: a host computer, a wave control code calculation module, a data exchange module, an FPGA module and a TR control module; the FPGA module includes a data transceiver scheduling module, a storage control module, and a storage unit; the FPGA module is also connected to the radar wave control signal for receiving the radar wave control signal.

3. The method for realizing digital wave control of a phased array radar according to claim 2, characterized in that: The data exchange module and the wave control code calculation module communicate via PCIE.

4. The method for realizing digital wave control of a phased array radar according to claim 2, characterized in that: The data conversion module completes the data conversion between optical fiber communication and PCIE or RapidIO.

5. A method for realizing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: The specific working process of step 1 is as follows: the host computer performs beam scheduling control, sets beam pointing, beam number L, beam width or working frequency parameters, and sends the parameters to the beam control code calculation module.

6. A method for realizing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: In step 1, set the working times a of each group of wave control codes n , the working times are sent synchronously with the wave control code parameters.

7. A method for implementing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: In step 1, set the working times a of each group of wave control codes n , when working, it is sent by the host computer and executed in step 5.

8. The method for realizing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: The wave control code parameters in step 2 include frequency code, waveform code, transmission DBF coefficient, delay compensation code, correction coefficient or reception DBF coefficient.

9. A method for implementing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: In step 4, each address of each RAM corresponds to a parameter of a wave control code.

10. The method for realizing digital wave control of a phased array radar according to claim 1 or 2, characterized in that: The working process in step 9 is as follows: the wave control code calculation module detects the pulse sequence number and wave position code in the returned data frame header, and when the pulse sequence number of the same wave position code is counted from 1 to a n , indicating that the nth beam is continuously received n Data of PRIs; Storage unit n is in idle state, rewrite the wave control code; repeat steps 3 to 5 to store the N+nth group of wave control codes in storage unit n, and the beam N+n points to the number of times a N+n When the Nth beam is finished, the storage control module will re-read the storage unit 1 to generate the N+1th beam, and then cycle through all the control and normal operation of the L groups of beams.

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