Task processing method and device, electronic equipment and storage medium

Abstract

The invention provides a task processing method, and relates to the technical field of artificial intelligence, in particular to the technical field of chips and parallel computing. According to the specific implementation scheme, a plurality of to-be-executed tasks are provided for a plurality of function units, the function units comprise a plurality of memory access units, the to-be-executed tasks correspond to at least one memory access instruction, and at least one synchronization mode of the memory access instruction comprises at least one of a first synchronization mode and a second synchronization mode; the first synchronization mode is used for indicating to generate a synchronization signal after the execution of the memory access instruction is completed, and the second synchronization mode is used for indicating to execute the memory access instruction after receiving the synchronization signal; and in response to determining that the at least one synchronization mode of the executed memory access instruction comprises a first synchronization mode, providing a synchronization signal to a target memory access unit in the plurality of memory access units, the target memory access unit being used for executing the to-be-executed memory access instruction corresponding to the synchronization signal. The invention further provides a task processing device, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, in particular to the technical fields of chips, parallel computing, multi-threaded processors, etc., and can be applied to the training and reasoning scenarios of deep learning models and graphics computing scenarios. More specifically, the present disclosure provides a task processing method, device, electronic device and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the instructions of multiple threads can be executed concurrently and interleaved, so that the memory access operations of multiple threads cover each other to make full use of the chip's computing resources and memory access resources. Summary of the invention

[0003] The present disclosure provides a task processing method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, a task processing method is provided, the method comprising: providing a plurality of tasks to be executed to a plurality of functional units, wherein the plurality of functional units include a plurality of memory access units, the tasks to be executed correspond to at least one memory access instruction, at least one synchronization mode of the memory access instruction includes at least one of a first synchronization mode and a second synchronization mode, the first synchronization mode is used to indicate that a synchronization signal is generated after the execution of the memory access instruction is completed, and the second synchronization mode is used to indicate that the execution of the memory access instruction starts after the synchronization signal is received; in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, providing a synchronization signal to a target memory access unit among the plurality of memory access units, wherein the target memory access unit is used to execute the memory access instruction to be executed corresponding to the synchronization signal.

[0005] According to another aspect of the present disclosure, a task processing device is provided, which includes: a task scheduling unit, configured to: provide a plurality of tasks to be executed to a plurality of functional units, wherein the plurality of functional units include a plurality of memory access units, the tasks to be executed correspond to at least one memory access instruction, and at least one synchronization mode of the memory access instruction includes at least one of a first synchronization mode and a second synchronization mode, the first synchronization mode is used to indicate that a synchronization signal is generated after the execution of the memory access instruction is completed, and the second synchronization mode is used to indicate that the execution of the memory access instruction starts after the synchronization signal is received; a memory access unit, configured to: in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, provide a synchronization signal to a target memory access unit among the plurality of memory access units, wherein the target memory access unit is used to execute the memory access instruction to be executed corresponding to the synchronization signal.

[0006] According to another aspect of the present disclosure, a task processing device is provided, and the device includes: The present disclosure provides a task processing apparatus.

[0007] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0009] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0010] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0012] Figure 1 is a flowchart of a task processing method according to an embodiment of the present disclosure;

[0013] Figure 2 is a schematic diagram of multiple functional units according to an embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram of a memory access instruction according to an embodiment of the present disclosure;

[0015] Figure 4A is a schematic diagram of a memory access unit according to an embodiment of the present disclosure;

[0016] Figure 4B is a schematic diagram of a memory access unit according to another embodiment of the present disclosure;

[0017] Figure 5 is a schematic diagram of executing a task to be executed according to an embodiment of the present disclosure;

[0018] Figure 6 is a schematic block diagram of a task processing device according to an embodiment of the present disclosure;

[0019] Figure 7 is a block diagram of a task processing device according to an embodiment of the present disclosure; and

[0020] Figure 8is a block diagram of an electronic device to which a task processing method can be applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] There may be no data dependency between multiple instructions of multiple concurrent threads. Data dependencies may include read-after-write, write-after-read, read-after-read, and write-after-write dependencies. For operation flow queues with data dependencies, it is difficult to implement concurrent instruction scheduling. An operation flow queue may include multiple tasks to be executed. The operation flow queue will be described below.

[0023] A deep learning model may include multiple model layers. During the training or reasoning process of a deep learning model, the calculation of each model layer may be abstracted into one or more operators. The one or more operators include operators such as convolution, full connection, pooling, and activation. Among the multiple operators executed in a preset order, some subsequent operators depend on the calculation results of the preceding operators. This series of operators may be organized into an operation stream queue, and each operator may correspond to a task to be executed in the operation stream. The operation stream queue may be sent serially to a deep learning acceleration unit for calculation. The deep learning acceleration unit may be a general purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a Kunlun core, and other hardware computing units.

[0024] In addition, taking a general-purpose graphics processing unit as an example, multiple consecutive tasks can be executed during the graphics calculation process. These tasks may include geometry processing, rasterization, pixel processing, rendering output, etc. Some of these tasks have data dependencies, and these tasks can be organized into operation stream queues to use the graphics processing unit to execute these tasks serially.

[0025] When scheduling an operation flow queue, it can be scheduled serially according to the order in the operation flow queue. In the case of a data dependency relationship between two tasks to be executed in the operation flow queue, in order to ensure the correctness of the calculation result, the task scheduling unit can take out the two tasks to be executed in sequence from the operation flow queue and send them to the corresponding functional units. For example, after the previous task to be executed is completed, the subsequent task to be executed can be taken out from the operation flow queue and continue to be sent to the functional unit. The previous task to be executed can be an addition task. In order to execute the addition task, a data read instruction, an addition instruction and a data write instruction can be executed in sequence. The data read instruction can be provided to a memory access unit so that the memory access unit reads one or more data. The arithmetic logic unit (ALU) can execute the addition instruction according to the one or more data to obtain the addition result. Next, another memory access unit can execute the data write instruction to write the addition result into the specified storage space. When executing the subsequent task to be executed, one or more instructions can be executed based on the addition result. Therefore, after the addition result is written back, the subsequent tasks to be executed can be sent to the functional unit. In the case of serial scheduling of tasks according to the order in the operation flow queue, the time consumption of each task in the operation flow queue cannot cover each other, and the hardware utilization is low.

[0026] In addition, among the multiple subtasks of the subsequent tasks to be executed, there may be subtasks that have no dependencies on the previous tasks to be executed. When scheduling an operation flow queue, the tasks to be executed in the operation flow queue can also be split into more fine-grained subtasks. Among the multiple subtasks of the subsequent tasks to be executed, one or more subtasks that have no dependencies on the previous tasks to be executed are issued in advance to improve hardware utilization efficiency. The one or more subtasks may include a cache release subtask, a constant handling subtask, and the like. However, in order to achieve the splitting of the tasks to be executed, the complexity of the task scheduling unit will increase, resulting in an increase in the cost of chip design.

[0027] Therefore, in order to efficiently process the tasks to be executed, the present disclosure provides a task processing method, which will be described below.

[0028] Figure 1 is a flowchart of a task processing method according to an embodiment of the present disclosure.

[0029] like Figure 1 As shown, the method 100 may include operations S110 to S120.

[0030] In operation S110 , a plurality of tasks to be performed are provided to a plurality of functional units.

[0031] In the embodiment of the present disclosure, the multiple tasks to be executed may be multiple tasks to be executed in one or more of the above-mentioned operation flow queues.

[0032] In the embodiment of the present disclosure, the multiple functional units may include multiple memory access units, and may also include multiple arithmetic logic units.

[0033] In the disclosed embodiment, the multiple tasks to be executed provided to the multiple functional units may or may not have data dependencies. For example, when sending tasks, regardless of whether there is a data dependency between the previous task to be executed and the subsequent task to be executed, the previous task to be executed and the subsequent task to be executed may be sent directly, rather than sending the subsequent task to be executed after the previous task to be executed is completed.

[0034] In an embodiment of the present disclosure, among multiple tasks to be executed, one or more tasks to be executed correspond to at least one memory access instruction. For example, multiple tasks to be executed may include an addition task, and the addition task corresponds to a first memory access instruction and a second memory access instruction. The first memory access instruction can read data, and the second memory access instruction can write back the addition result. It can be understood that among multiple tasks to be executed, there may be tasks to be executed that do not correspond to a memory access instruction. When executing the task to be executed that does not correspond to the memory access instruction, the memory access operation may not be performed.

[0035] In an embodiment of the present disclosure, a memory access instruction may have at least one synchronization mode. At least one synchronization mode of the memory access instruction includes a first synchronization mode and a second synchronization mode. The first synchronization mode may indicate that a synchronization signal is generated after the execution of the memory access instruction is completed. The second synchronization mode may indicate that the memory access instruction is started to be executed after the synchronization signal is received. For example, the synchronization mode of a memory access instruction may be the first synchronization mode, and the synchronization mode of another memory access instruction may be the second synchronization mode.

[0036] In operation S120 , in response to determining that at least one synchronization pattern of the executed memory access instruction includes a first synchronization pattern, a synchronization signal is provided to a target memory access unit among the plurality of memory access units.

[0037] In the embodiment of the present disclosure, if at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, a synchronization signal can be generated after the memory access instruction is executed, and the synchronization signal can be provided to the target memory access unit. The target memory access unit can be the memory access unit that needs to execute the to-be-executed memory access instruction corresponding to the synchronization signal.

[0038] In the embodiment of the present disclosure, the target memory access unit may execute the memory access instruction to be executed corresponding to the synchronization signal. For example, after receiving the synchronization signal, the target memory access unit may execute the memory access instruction to be executed corresponding to the synchronization signal.

[0039] Through the disclosed embodiments, multiple tasks to be executed are provided to multiple functional units, which can improve the efficiency of task issuance and thus improve the computing efficiency of the chip. A memory access mode is set for memory access instructions so that tasks to be executed with data dependencies can be correctly executed, which can effectively improve the accuracy of the chip. The setting of memory access instructions will hardly increase the design complexity of the task scheduling unit and the memory access unit, and can improve the efficiency of the chip at a lower cost.

[0040] It can be understood that the above describes the method of the present disclosure, and some ways of providing multiple tasks to be executed to multiple functional units will be described below.

[0041] Figure 2 is a schematic diagram of multiple functional units according to an embodiment of the present disclosure.

[0042] like Figure 2 As shown, the task scheduling unit 210 can provide tasks of each of the multiple operation flow queues to multiple functional units. The multiple operation flow queues can include an operation flow queue opfq20, an operation flow queue opfq21, and an operation flow queue opfq22. It can be understood that Figure 2 The multiple operation flow queues shown are only examples, and the number of operation flow queues can be any value.

[0043] like Figure 2 As shown, the multiple functional units may include multiple memory access units and multiple execution units. The multiple memory access units may include memory access unit 221 and memory access unit 222. The multiple execution units may include execution unit p20 and execution unit p21. It can be understood that Figure 2 The functional units shown are only examples, and multiple functions may also include other units, which is not limited by the present disclosure.

[0044] like Figure 2 As shown, the operation flow queue opfq20 may include a pending task m200, a pending task m201, a pending task m202, and a pending task m203. The operation flow queue opfq21 may include a pending task m210, a pending task m211, a pending task m212, and a pending task m213. The operation flow queue opfq22 may include a pending task m220, a pending task m221, a pending task m222, and a pending task m223. The following will be described in conjunction with the operation flow queue opfq20.

[0045] In some embodiments, in some implementations of the above operation S110, providing multiple tasks to be executed to multiple functional units may include: in response to providing a first task to be executed among the multiple tasks to be executed to at least one of the multiple functional units, providing a second task to be executed after the first task to be executed among the multiple tasks to be executed to at least one of the multiple functional units.

[0046] like Figure 2 As shown, the task scheduling unit can provide the pending task m200 to the memory access unit 221. Next, regardless of whether the pending task m200 is completed, the pending task 201 can be provided to the memory access unit 222. It can be understood that when the pending task m201 is provided to the memory access unit 221, the pending task m200 can be used as the first pending task, and the pending task m201 can be used as the second pending task.

[0047] If the plurality of memory access units include other memory access units in addition to the memory access unit 221 and the memory access unit 222. In this case, regardless of whether the pending task m201 is completed, in response to providing the pending task m201 to the memory access unit 222, the pending task m202 can be provided to the memory access unit. It can be understood that when providing the pending task m202 to the memory access unit, the pending task m201 can be used as the first pending task, and the pending task m202 can be used as the second pending task.

[0048] It can be understood that the above describes some ways of providing the tasks to be performed to multiple functional units, and the following describes some ways of performing the tasks to be performed.

[0049] In some embodiments, in some implementations of the above operation S120, providing a synchronization signal to a target memory access unit among multiple memory access units includes: broadcasting a synchronization signal to multiple memory access units. After providing the task to be executed to the memory access unit, the memory access unit can execute the memory access instruction corresponding to the task to be executed. If the memory access mode of the memory access instruction corresponding to the task to be executed m200 is the first memory access mode, after the memory access unit 221 executes the memory access instruction of the task to be executed m200, a synchronization signal can be generated. The synchronization signal can be provided to the memory access unit 222 through the synchronization signal broadcasting network syn20.

[0050] In an embodiment of the present disclosure, multiple memory access units are connected via wiring. The wiring between the multiple memory access units forms a synchronization signal broadcast network. For another example, if there are N memory access units, a synchronization signal can be copied into N synchronization signals. N synchronization signals are provided to N memory access units via the synchronization signal broadcast network. N can be an integer greater than 1. The N memory access units include the above-mentioned target memory access unit. Through the embodiment of the present disclosure, the synchronization signal is broadcast to multiple memory access units, which can reduce the complexity of the memory access instruction and can execute subsequent memory access instructions at a lower cost.

[0051] It can be understood that the above further describes the method of the present disclosure, and the memory access instruction of the present disclosure will be further described below.

[0052] In some embodiments, the memory access instruction includes at least one of a memory access operation description field, a synchronization type field, and a synchronization identification field. The memory access operation description field may indicate the address and data amount of the memory access operation, the synchronization type field may indicate the synchronization mode of the memory access instruction, and the value of the synchronization identification field is the synchronization identification of the synchronization signal. Figure 3 Provide explanation.

[0053] Figure 3 is a schematic diagram of a memory access instruction according to an embodiment of the present disclosure.

[0054] like Figure 3 As shown, the memory access instruction instr30 may include a memory access operation description field fi301, a synchronization type field fi302, and a synchronization identification field fi303. The memory access instruction instr30 may be a 32-bit instruction.

[0055] In an embodiment of the present disclosure, the memory access operation description field may indicate the address and data volume of the memory access operation. For example, the value of the memory access operation description field may include the type of memory access operation, the first address, and the offset value. Based on the first address and the offset value, an address space may be determined. If the type of the memory access operation is load, data may be read from the address space. If the type of the memory access operation is store, data may also be written to the address space. The offset value may be related to the data volume of the data.

[0056] In an embodiment of the present disclosure, the synchronization type field may indicate a synchronization mode of a memory access instruction. For example, the value of the synchronization type field may be 2 bits. The synchronization mode of the memory access instruction may be at least one. The at least one synchronization mode may include a first memory access mode, a second memory access mode, and a third memory access mode. The third memory access mode may indicate that the memory access instruction can be executed without waiting for a synchronization signal and that no synchronization signal is generated after the execution is completed. If the value of the synchronization type field is 00, it may indicate that the synchronization mode of the memory access instruction is the third memory access mode. If the value of the memory access synchronization type field is 01, it may indicate that the memory access mode of the memory access instruction is the first memory access mode. If the value of the memory access synchronization type field is 10, it may indicate that the memory access mode of the memory access instruction is the second memory access mode. If the value of the memory access synchronization type field is 11, it may indicate that the memory access mode of the memory access instruction is 2, namely, the first memory access mode and the second memory access mode. It can be understood that the correspondence between the value of the synchronization type field and the synchronization mode is only an example.

[0057] In an embodiment of the present disclosure, the value of the synchronization identification field is the synchronization identification of the memory access instruction. The memory access unit may correspond to the synchronization signal cache module. For example, taking the third memory access instruction and the fourth memory access instruction in multiple memory access instructions as examples, the synchronization mode of the third memory access instruction may be the first synchronization mode, and the memory access mode of the fourth memory access instruction may be the second synchronization mode. The value of the synchronization type field of the third memory access instruction and the value of the synchronization type field of the fourth memory access instruction may be different. The value of the synchronization identification field of the third memory access instruction and the value of the synchronization identification field of the fourth memory access instruction may be the same. After the third memory access instruction is executed, the memory access unit that executes the third memory access instruction may generate a synchronization signal and broadcast the synchronization signal of the third memory access instruction. The synchronization signal may include the synchronization identification of the third memory access instruction. N synchronization signal cache modules for N memory access units may receive the synchronization signal so that one of the N memory access units executes the fourth memory access instruction. For another example, the synchronization identification may be a number. The synchronization identification field may be 8 bits.

[0058] It can be understood that the memory access instruction of the present disclosure is described above, and the memory access unit of the present disclosure is described below.

[0059] In some embodiments, the memory access unit may also correspond to an instruction cache module. For example, the instruction cache module may be implemented based on a portion of the storage space of a static random access memory (SRAM). The instruction cache module may be configured to store multiple memory access instructions. The synchronization signal cache module may be implemented based on a register. The capacity of the register may be no less than 8 bits. The synchronization signal cache module may be configured to receive at least one synchronization signal. Figure 4A Provide explanation.

[0060] Figure 4A is a schematic diagram of a memory access unit according to an embodiment of the present disclosure.

[0061] like Figure 4A As shown, the memory access unit 420 may include a memory access interface lsui40, an instruction cache module ic40 and a synchronization signal cache module sync40.

[0062] In an embodiment of the present disclosure, the instruction cache module is configured to store a memory access instruction queue. The memory access instruction queue may include multiple memory access instructions. As shown in FIG. 4 , the instruction cache module ic40 may be configured to store a memory access instruction queue lsuq40. The memory access instruction queue lsuq40 may include memory access instructions instr400, memory access instructions instr401, memory access instructions instr402 . . . , memory access instructions instr404. The memory access instruction instr400 is located at the head of the memory access instruction queue lsuq40.

[0063] In some embodiments, in some implementations of the above operation S120, in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, providing a synchronization signal to a target memory access unit among multiple memory access units includes: in response to determining that at least one synchronization mode of the first head memory access instruction includes the first synchronization mode, executing the first head memory access instruction. The first head memory access instruction is a memory access instruction at the head of the memory access instruction queue for the first memory access unit. As shown in Figure 4, the above memory access instruction instr400 is located at the head of the memory access instruction queue lsuq40 and can be used as the first head memory access instruction. If the synchronization mode of the memory access instruction instr400 is the first synchronization mode, the memory access instruction instr400 can be executed.

[0064] In some embodiments, in some implementations of the above operation S120, in response to determining that at least one synchronization mode of the executed memory access instruction includes a first synchronization mode, providing a synchronization signal to a target memory access unit among multiple memory access units may also include: in response to determining that the first head memory access instruction is executed, providing a synchronization signal to a synchronization signal cache module for the target memory access unit. For example, after the execution of the memory access instruction instr400 is completed, a synchronization signal can be generated and broadcast to N memory access units. The fifth memory access instruction may have a dependency relationship with the memory access instruction instr400. The fifth memory access instruction may be stored in an instruction cache module of one of the N memory access units. The memory access unit storing the fifth memory access instruction may be used as a target memory access unit. The memory access mode of the fifth memory access instruction may be the second memory access mode.

[0065] In some embodiments, the target memory access unit is used to perform the following operations to execute the memory access instruction corresponding to the synchronization signal: in response to determining that at least one memory access mode of the second head memory access instruction includes the second synchronization mode and determining that there is at least one synchronization signal corresponding to the second head memory access instruction in the synchronization signal cache unit for the memory access unit, the second head memory access instruction is executed. The second head memory access instruction is a memory access instruction at the head of the memory access instruction queue for the target memory access unit. For example, after the execution of the above-mentioned memory access instruction instr400 is completed, the target memory access unit can receive the synchronization signal via the above-mentioned synchronization signal broadcast network. When the fifth memory access instruction is located at the head of the memory access instruction queue, the fifth memory access instruction can be used as the second head memory access instruction. It can be determined whether there is a synchronization signal corresponding to the synchronization identification field of the fifth memory access instruction in the synchronization signal cache space of the target memory access unit. If it is determined that there is a synchronization signal corresponding to the fifth memory access instruction in the synchronization signal cache unit, the fifth memory access instruction can be executed. Through the embodiment of the present disclosure, an instruction cache module is set up, which can enable the memory access unit to execute multiple memory access instructions corresponding to multiple tasks to be executed. The memory access instruction queue of the instruction cache module can enable multiple memory access instructions to be correctly executed, which can effectively improve the accuracy of task execution while improving the efficiency of task scheduling. The synchronization signal cache module can receive synchronization signals at a lower cost and further improve the accuracy of task execution.

[0066] It can be understood that the above text describes the method of the present disclosure in conjunction with the memory access instruction instr400 and the fifth memory access instruction. The method of the present disclosure will be further described below in conjunction with the memory access instruction instr401.

[0067] Figure 4B is a schematic diagram of a memory access unit according to another embodiment of the present disclosure.

[0068] like Figure 4B As shown, after the memory access instruction instr400 is provided to the memory access interface lsui40, the memory access instruction instr401 can be moved to the head of the memory access instruction queue lsuq40. The memory access mode of the memory access instruction instr401 can be the second memory access mode. It can be determined whether there is a synchronization signal whose synchronization identifier is consistent with the value of the synchronization identifier field of the memory access instruction instr401 among the multiple synchronization signals in the synchronization signal cache module sync40. If there is a synchronization signal singal401 whose synchronization identifier is consistent with the synchronization identifier field of the memory access instruction instr401, the memory access instruction instr401 can be executed.

[0069] In another embodiment of the present disclosure, in response to determining that at least one memory access mode of the second header memory access instruction includes a second synchronization mode and determining that at least one synchronization signal corresponding to the second header memory access instruction does not exist in the synchronization signal cache unit for the memory access unit, the second header memory access instruction is blocked. If there is no synchronization signal whose synchronization identifier is consistent with the synchronization identifier field of the memory access instruction, the memory access instruction queue lsuq40 is blocked until a synchronization signal consistent with the synchronization identifier field of the memory access instruction is received.

[0070] In addition, in another embodiment of the present disclosure, Figure 4B As shown, after the memory access instruction instr400 is provided to the memory access interface lsui40, the memory access instruction queue lsuq40 can receive a new memory access instruction. It can be understood that the above-mentioned multiple tasks to be executed are multiple tasks to be executed of a program kernel. The number of tasks to be executed included in the program kernel can be greater than or equal to the number of tasks to be executed provided to multiple functional units. In the case where there is a third task to be executed that is not provided to the memory access unit among the multiple tasks to be executed of the program kernel, if an idle queue position appears in the memory access instruction queue of the memory access unit, the third task to be executed can be provided to the memory access unit.

[0071] In one embodiment of the present disclosure, the synchronization signal may be broadcast to N memory access units. The synchronization signal cache module of the memory access unit may receive multiple synchronization signals. Among the multiple synchronization signals received by the synchronization signal cache module sync40, there may be irrelevant synchronization signals that do not correspond to any memory access instruction in the memory access instruction queue lsuq40. In the case where the memory access instruction has a synchronization identification field, these irrelevant synchronization signals will not affect the normal execution of the memory access instruction.

[0072] In another embodiment of the present disclosure, in response to determining that the second header memory access instruction is executed, the cache space corresponding to the second header memory access instruction in the synchronization signal cache module is released. For example, after the memory access instruction instr401 is executed, the synchronization signal in the synchronization signal cache module, whose synchronization flag is consistent with the value of the synchronization flag field of the memory access instruction instr401, can be deleted to release the corresponding storage space.

[0073] In some embodiments, in response to determining that multiple tasks to be executed are completed, the storage space of each of the multiple synchronization signal buffer modules is released. For example, after all the tasks to be executed are completed, all the storage space of the synchronization signal buffer module can be released.

[0074] It can be understood that the present disclosure is described above in conjunction with the first memory access mode and the second memory access mode, respectively, and the memory access instructions of the present disclosure will be further described below in conjunction with multiple memory access modes.

[0075] In the embodiment of the present disclosure, in response to determining that the memory access mode of the memory access instruction is the third memory access mode, the memory access instruction can be executed. After the execution is completed, there is no need to generate a synchronization signal.

[0076] In addition, in another embodiment of the present disclosure, at least one memory access mode of the memory access instruction may include a first memory access mode and a second memory access mode. When the memory access instruction is located at the head of the memory access instruction queue, it can be determined whether the synchronization signal cache module has a synchronization signal whose synchronization identifier is consistent with the value of the synchronization identifier field of the memory access instruction. After the execution of the memory access instruction is completed, a synchronization signal can be generated. It can be understood that in this case, the value of the synchronization signal identifier field may include a value indicating the execution order.

[0077] In addition, in the disclosed embodiment, if the synchronization mode of the memory access instruction is the second synchronization mode, the value of the synchronization identification field can be a concatenation of multiple synchronization identifications. For example, a memory access instruction can have a data dependency relationship with multiple previous memory access instructions. After receiving multiple synchronization signals of multiple previous memory access instructions, the subsequent memory access instruction that has a dependency relationship with the multiple previous memory access instructions can be executed.

[0078] It can be understood that the above describes the memory access unit of the present disclosure, and the execution process of the task to be executed will be described below.

[0079] Figure 5 It is a schematic diagram of executing a task to be executed according to an embodiment of the present disclosure.

[0080] like Figure 5 As shown, the task to be executed m500 may include a first cache release subtask, a first memory access subtask, a first calculation subtask, and a second memory access subtask. The first cache release subtask corresponds to the first cache release instruction instr_re500. The first memory access subtask corresponds to the sixth memory access instruction instr506. The first calculation subtask corresponds to the first calculation instruction instr_cal500. The second memory access subtask corresponds to the seventh memory access instruction instr507. The task to be executed m501 may include a second cache release subtask, a third memory access subtask, a second calculation subtask, and a fourth memory access subtask. The second cache release subtask corresponds to the second cache release instruction instr_re501. The third memory access subtask corresponds to the eighth memory access instruction instr508. The second calculation subtask corresponds to the second calculation instruction instr_cal501. The fourth memory access subtask corresponds to the ninth memory access instruction instr509. The seventh memory access instruction instr507 and the eighth memory access instruction instr508 may have a data dependency relationship. The memory access mode of the seventh memory access instruction instr507 may be the first memory access mode. The memory access mode of the eighth memory access instruction instr508 may be the second memory access mode.

[0081] As described above, the task to be executed m500 and the task to be executed m501 can be provided to two functional units respectively. The first cache release instruction instr_re500 can be an instruction without dependency. The second cache release instruction instr_re501 can also be an instruction without dependency. Thus, the first cache release instruction instr_re500 and the second cache release instruction instr_re501 can be executed respectively, which can effectively tap the hardware parallel capability and improve the task execution efficiency.

[0082] The eighth memory access instruction instr508 needs to wait for the synchronization signal of the seventh memory access instruction instr507. The execution of the task m501 to be executed is blocked. In addition, after the first cache release instruction instr_con500 is executed, the sixth memory access instruction instr506, the first calculation instruction instr_cal500 and the seventh memory access instruction instr507 can be executed in sequence. When executing the seventh memory access instruction instr507, a synchronization signal can be generated and broadcast. The memory access unit that receives the eighth memory access instruction can execute the eighth memory access instruction instr508, the second calculation instruction instr_cal501 and the ninth memory access instruction in sequence after receiving the synchronization signal. Therefore, after setting the synchronization type field and the synchronization signal identification field of the memory access instruction, it is not necessary to determine the dependency relationship between subtasks in the scheduling stage, and it is also possible to implement the execution of non-dependent subtasks first, thereby improving execution efficiency.

[0083] Figure 6 is a schematic block diagram of a task processing device according to an embodiment of the present disclosure.

[0084] like Figure 6 As shown, the apparatus 600 may include a task scheduling unit 610 and a memory access unit 620 .

[0085] The task scheduling unit 610 can be configured to provide multiple tasks to be executed to multiple functional units. The multiple functional units include multiple memory access units, and the tasks to be executed correspond to at least one memory access instruction. At least one synchronization mode of the memory access instruction includes at least one of a first synchronization mode and a second synchronization mode. The first synchronization mode is used to indicate that a synchronization signal is generated after the execution of the memory access instruction is completed, and the second synchronization mode is used to indicate that the memory access instruction is started to be executed after the synchronization signal is received. The task scheduling unit 610 can perform the above operation S110. The above description of the task scheduling unit 210 is also applicable to the task scheduling unit 610, and the present disclosure will not repeat it here.

[0086] The memory access unit 620 may be configured to: in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, provide a synchronization signal to a target memory access unit among the multiple memory access units. The target memory access unit is used to execute the memory access instruction to be executed corresponding to the synchronization signal. It can be understood that the memory access unit 620 can perform the above operation S120, and the above description of the memory access unit 221, the memory access unit 222 and the memory access unit 420 is also applicable to the memory access unit 620.

[0087] In some embodiments, the task scheduling unit is also configured to perform the following operations to provide multiple tasks to be executed to multiple functional units: in response to a first task to be executed among the multiple tasks to be executed having been provided to at least one of the multiple functional units, a second task to be executed after the first task to be executed among the multiple tasks to be executed is provided to at least one of the multiple functional units.

[0088] In some embodiments, the memory access unit includes at least one of an instruction cache module and a synchronization signal cache module, the instruction cache module is configured to store a plurality of memory access instructions, and the synchronization signal cache module is configured to receive at least one synchronization signal.

[0089] In some embodiments, the instruction cache module is further configured to store a memory access instruction queue, the memory access instruction queue stores a plurality of memory access instructions, and the memory access unit is further configured to perform the following operations in response to determining that at least one synchronization mode of the executed memory access instruction includes a first synchronization mode, providing a synchronization signal to a target memory access unit among the plurality of memory access units includes: in response to determining that at least one synchronization mode of the first head memory access instruction includes the first synchronization mode, executing the first head memory access instruction. The first head memory access instruction is a memory access instruction at the head of the memory access instruction queue for the first memory access unit. In response to determining that the first head memory access instruction is executed, providing a synchronization signal to a synchronization signal cache module for the target memory access unit.

[0090] In some embodiments, the target memory access unit is configured to perform the following operations to execute the memory access instruction corresponding to the synchronization signal: in response to determining that at least one memory access mode of the second head memory access instruction includes the second synchronization mode and determining that there is at least one synchronization signal corresponding to the second head memory access instruction in the synchronization signal cache unit for the memory access unit, execute the second head memory access instruction. The second head memory access instruction is the memory access instruction at the head of the memory access instruction queue for the target memory access unit.

[0091] In some embodiments, the memory access instruction includes at least one of a memory access operation description field, a synchronization type field, and a synchronization identification field. The memory access operation description field is used to indicate the address and data amount of the memory access operation, the synchronization type field is used to indicate the synchronization mode of the memory access instruction, and the value of the synchronization identification field is the synchronization identification of the memory access instruction.

[0092] In some embodiments, the above-mentioned device also includes a synchronization signal broadcasting network, and the memory access unit is further configured to perform the following operations to provide the synchronization signal to a target memory access unit among the multiple memory access units: broadcast the synchronization signal to the multiple memory access units.

[0093] In some embodiments, the plurality of synchronization signal buffer modules are further configured to: in response to determining that the plurality of tasks to be executed are completed, release the storage space of each of the plurality of synchronization signal buffer modules.

[0094] Figure 7 is a block diagram of a task execution device according to an embodiment of the present disclosure.

[0095] like Figure 7 As shown, the device 70 may include a task processing device 700. The task processing device 700 may be the device 600 described above.

[0096] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0097] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0098] Figure 8 A schematic block diagram of an example electronic device 800 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0099] like Figure 8As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0100] A number of components in the device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0101] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as the task processing method. For example, in some embodiments, the task processing method may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the task processing method described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute the task processing method in any other appropriate manner (eg, by means of firmware).

[0102] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0103] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0104] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0105] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0106] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0107] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0108] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0109] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A task processing method, comprising: Providing a plurality of tasks to be executed to a plurality of functional units, wherein the plurality of functional units include a plurality of memory access units, the tasks to be executed correspond to at least one memory access instruction, and at least one synchronization mode of the memory access instruction includes at least one of a first synchronization mode and a second synchronization mode, wherein the first synchronization mode is used to indicate that a synchronization signal is generated after the execution of the memory access instruction is completed, and the second synchronization mode is used to indicate that the execution of the memory access instruction starts after the synchronization signal is received; In response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, the synchronization signal is provided to a target memory access unit among the multiple memory access units, wherein the target memory access unit is used to execute the memory access instruction to be executed corresponding to the synchronization signal.

2. The method according to claim 1, wherein: Providing a plurality of tasks to be performed to a plurality of functional units comprises: In response to a first task to be performed among the plurality of tasks to be performed being provided to at least one of the plurality of functional units, a second task to be performed after the first task to be performed among the plurality of tasks to be performed is provided to at least one of the plurality of functional units.

3. The method according to claim 1, wherein: The memory access unit includes at least one of an instruction cache module and a synchronization signal cache module, the instruction cache module is configured to store a plurality of the memory access instructions, and the synchronization signal cache module is configured to receive at least one of the synchronization signals.

4. The method according to claim 3, wherein: The instruction cache module is further configured to store a memory access instruction queue, wherein the memory access instruction queue stores a plurality of the memory access instructions. In response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, providing the synchronization signal to a target memory access unit among the plurality of memory access units includes: In response to determining that at least one synchronization mode of a first head memory access instruction includes the first synchronization mode, executing the first head memory access instruction, wherein the first head memory access instruction is a memory access instruction at the head of a memory access instruction queue for the first memory access unit; In response to determining that the first header memory access instruction is executed completely, providing the synchronization signal to a synchronization signal buffer module for the target memory access unit.

5. The method according to claim 3, wherein: The target memory access unit is used to perform the following operations to execute the memory access instruction corresponding to the synchronization signal: In response to determining that at least one memory access mode of a second head memory access instruction includes a second synchronization mode and determining that there is at least one synchronization signal corresponding to the second head memory access instruction in a synchronization signal cache unit used for the memory access unit, the second head memory access instruction is executed, wherein the second head memory access instruction is a memory access instruction at the head of a memory access instruction queue for the target memory access unit.

6. The method according to claim 1, wherein: The memory access instruction includes at least one of a memory access operation description field, a synchronization type field and a synchronization identification field. The memory access operation description field is used to indicate the address and data amount of the memory access operation, the synchronization type field is used to indicate the synchronization mode of the memory access instruction, and the value of the synchronization identification field is the synchronization identification of the memory access instruction.

7. The method according to claim 1, wherein: Providing the synchronization signal to a target memory access unit among the plurality of memory access units comprises: The synchronization signal is broadcasted to a plurality of the memory access units.

8. The method according to claim 3, further comprising: In response to determining that the plurality of tasks to be executed are completed, the storage space of each of the plurality of synchronization signal buffer modules is released.

9. A task processing device, comprising: A task scheduling unit, configured to: provide a plurality of tasks to be executed to a plurality of functional units, wherein the plurality of functional units include a plurality of memory access units, the tasks to be executed correspond to at least one memory access instruction, at least one synchronization mode of the memory access instruction includes at least one of a first synchronization mode and a second synchronization mode, the first synchronization mode is used to indicate that a synchronization signal is generated after the execution of the memory access instruction is completed, and the second synchronization mode is used to indicate that the execution of the memory access instruction starts after the synchronization signal is received; A memory access unit is configured to: in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, provide the synchronization signal to a target memory access unit among the multiple memory access units, wherein the target memory access unit is used to execute the memory access instruction to be executed corresponding to the synchronization signal.

10. The device according to claim 9, wherein: The task scheduling unit is further configured to perform the following operations to provide a plurality of tasks to be executed to a plurality of functional units: In response to a first task to be performed among the plurality of tasks to be performed being provided to at least one of the plurality of functional units, a second task to be performed after the first task to be performed among the plurality of tasks to be performed is provided to at least one of the plurality of functional units.

11. The device according to claim 9, wherein: The memory access unit includes at least one of an instruction cache module and a synchronization signal cache module, the instruction cache module is configured to store a plurality of the memory access instructions, and the synchronization signal cache module is configured to receive at least one of the synchronization signals.

12. The device according to claim 11, wherein The instruction cache module is further configured to store a memory access instruction queue, wherein the memory access instruction queue stores a plurality of the memory access instructions. The memory access unit is further configured to perform the following operations in response to determining that at least one synchronization mode of the executed memory access instruction includes the first synchronization mode, providing the synchronization signal to a target memory access unit among the plurality of memory access units comprises: In response to determining that at least one synchronization mode of a first head memory access instruction includes the first synchronization mode, executing the first head memory access instruction, wherein the first head memory access instruction is a memory access instruction at the head of a memory access instruction queue for the first memory access unit; In response to determining that the first header memory access instruction is executed completely, providing the synchronization signal to a synchronization signal buffer module for the target memory access unit.

13. The device according to claim 11, wherein: The target memory access unit is configured to perform the following operations to execute the memory access instruction corresponding to the synchronization signal: In response to determining that at least one memory access mode of a second head memory access instruction includes a second synchronization mode and determining that there is at least one synchronization signal corresponding to the second head memory access instruction in a synchronization signal cache unit used for the memory access unit, the second head memory access instruction is executed, wherein the second head memory access instruction is a memory access instruction at the head of a memory access instruction queue for the target memory access unit.

14. The device according to claim 9, wherein: The memory access instruction includes at least one of a memory access operation description field, a synchronization type field and a synchronization identification field. The memory access operation description field is used to indicate the address and data amount of the memory access operation, the synchronization type field is used to indicate the synchronization mode of the memory access instruction, and the value of the synchronization identification field is the synchronization identification of the memory access instruction.

15. The apparatus according to claim 9, further comprising a synchronization signal broadcasting network, The memory access unit is further configured to perform the following operations to provide the synchronization signal to a target memory access unit among the plurality of memory access units: The synchronization signal is broadcasted to a plurality of the memory access units.

16. The device according to claim 11, wherein The plurality of synchronization signal buffer modules are further configured to: in response to determining that the plurality of tasks to be executed are completed, release the storage space of each of the plurality of synchronization signal buffer modules.

17. A task processing device, comprising the task processing apparatus as claimed in any one of claims 9 to 16.

18. An electronic device, comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 8.

19. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 8.

20. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 8.

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