Interrupt management method and device of computer processor

Abstract

The invention provides an interrupt management method and device for a computer processor, and the method comprises the steps: setting an interrupt latch management module, setting M groups of interrupt functions in the interrupt latch management module, enabling each group of interrupt functions to correspond to N interrupt sources, enabling each interrupt source to correspond to one register, when the interrupt function receives an interrupt pulse sent by an interrupt source, the interrupt state of the interrupt source is stored in a register corresponding to the interrupt source; and allocating an independent weight configuration to each group of interrupt functions, performing weighted polling arbitration on all registers of the M groups of interrupt functions according to corresponding weights, selecting polled effective registers, generating corresponding interrupt information, and outputting the interrupt information to a bus for reporting. Compared with the prior art, the interrupt management structure is simple and flexible, the resource consumption is low, and the interrupt state can be reported in time according to needs.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit chip design and relates to an interrupt management reporting device and method. Background Art

[0002] Interrupt technology, as a core component in modern computer architecture, is the foundation of computer system flexibility, efficiency and reliability, and improves the efficiency of hardware resource utilization. With the continuous increase in computer system functions, the complexity of the system is rapidly increasing, and the number of interrupts between the computer's processor and subsystems and peripherals is rapidly increasing.

[0003] In traditional interrupt design, interrupt lines are generally used to report interrupts between computer processors, subsystems, and peripheral devices. As the number of interrupts increases, the number of interrupt lines increases, and the number of wiring between the processor and the subsystem also increases. This makes the interrupt lines of the entire chip system more and more complex. Moreover, in the entire system, the interrupt controller often has a limit on the number of interrupt lines, and the number of interrupts allocated to a specific subsystem is often far less than the needs of the subsystem. The usual practice is to merge multiple interrupts into one interrupt line and send it to the interrupt controller, which brings a large backtracking cost when the software is used.

[0004] Therefore, there is an urgent need for an interrupt management method and a management device for a computer processor that can solve the above problems. Summary of the invention

[0005] The object of the present invention is to provide a method and device for interrupt management of a computer processor, wherein the interrupt management structure is simple and flexible, consumes less resources, and can report the interrupt status in time as needed.

[0006] In order to achieve the above-mentioned purpose, the present invention provides an interrupt management method for a computer processor, comprising: setting an interrupt latch management module, in which M groups of interrupt functions are set, each group of the interrupt functions corresponds to N independent interrupt sources, and M and N are both integers greater than or equal to 2; each interrupt source corresponds to a register, and the M groups of interrupt functions communicate with M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt sources; when an interrupt request occurs in the interrupt source, the corresponding interrupt pulse is transmitted to the corresponding interrupt function, and when the interrupt function receives the interrupt pulse sent by the interrupt source, the interrupt state of the interrupt source is stored in the register corresponding to the interrupt source, and the register storing the interrupt state is called a valid register; an independent weight configuration is assigned to each group of interrupt functions, and weighted polling arbitration is performed on the M×N registers corresponding to the M groups of the interrupt functions according to the corresponding weights, and when the register selected by the polling arbitration is a valid register, the corresponding interrupt information is generated and the interrupt information is output to the bus for reporting.

[0007] Preferably, the interrupt information includes an index of an interrupt function to which the interrupt corresponding to the valid register belongs and a location index of an interrupt source.

[0008] Preferably, outputting the interrupt information to the bus for reporting specifically includes: forming the interrupt information into an AXI packet and sending it to the bus. Of course, the protocol is not limited to AXI, and the interrupt information can also be reported using other bus protocols such as APB and AHB.

[0009] Preferably, the weight of the interrupt function matches the priority of the interrupt function, and the higher the priority of the interrupt function, the higher the weight of the interrupt function.

[0010] Preferably, the interrupt management method further comprises the step of: clearing the interrupt status stored in the corresponding valid register after reporting the interrupt information to the bus.

[0011] The present invention also provides an interrupt management device for a computer processor, comprising an interrupt latch management module, a polling management module and a bus message triggering module, wherein the interrupt latch management module comprises M groups of interrupt functions, each group of the interrupt functions corresponds to N independent interrupt sources, and M and N are both integers greater than or equal to 2; each interrupt source corresponds to a register, and the M groups of the interrupt functions communicate with M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt sources, and when the interrupt function receives an interrupt pulse sent by the interrupt source, the interrupt function stores the interrupt status of the interrupt source in the register corresponding to the interrupt source, and the register storing the interrupt status is called a valid register; the polling management module assigns an independent weight configuration to each group of interrupt functions, and performs weighted polling arbitration on the M×N registers corresponding to the M groups of the interrupt functions according to the corresponding weights, and when the register selected by the polling arbitration is a valid register, generates corresponding interrupt information and transmits the interrupt information to the bus message triggering module; the bus message triggering module reports the interrupt information to the bus.

[0012] Preferably, the interrupt information includes an index of an interrupt function to which the interrupt corresponding to the valid register belongs and a position index of an interrupt source, wherein the position index of the interrupt source can be a specific position of the interrupt source or a register number.

[0013] Preferably, the bus message trigger module forms the interrupt information into an AXI packet and sends it to the bus. Of course, the protocol is not limited to AXI, and the interrupt information can also be reported using other bus protocols such as APB and AHB.

[0014] Specifically, the bus message trigger module composes the interrupt information into an AXI packet and sends it to the bus. After the AXI protocol returns the corresponding handshake signal, the bus message trigger module returns a ready signal to the polling management module. The polling management module ends the current arbitration according to the ready signal to proceed to the next weighted polling arbitration, and transmits the completion signal as a reporting feedback signal to the interrupt latch management module, so that the interrupt latch management module clears the interrupt status stored in the currently reported valid register according to the reporting feedback signal.

[0015] Preferably, the bus message trigger module also returns a reporting feedback signal to a corresponding interrupt function through the polling management module, and the interrupt function clears the interrupt status of the currently reported valid register according to the reporting feedback signal.

[0016] Preferably, the weight of the interrupt function matches the priority of the interrupt function, and the higher the priority of the interrupt function, the higher the weight of the interrupt function.

[0017] Compared with the prior art, the present invention uses a bus to report interrupt information, which effectively reduces the number of interrupt lines between the processor and the subsystem or peripheral device, and saves a large number of interconnection lines. Furthermore, the present invention uses multiple interrupt functions to independently manage the information in the register corresponding to the interrupt source, and can independently store, clear, and report the interrupt status. Not only is the control flexible, but also when an interrupt function performs related clearing operations, it does not affect the normal operation of other interrupt functions. Moreover, the present invention also independently configures weights for each interrupt function, and can distinguish the levels of interrupt functions according to importance or interrupt frequency, so as to achieve different performance configurations for users of different interrupt functions, and realize the distinction between VIPs and ordinary users. Furthermore, the present invention uses a single register to store interrupts of a single interrupt source, rather than other methods such as FIFO, which reduces the overhead of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural diagram of the interrupt management device of the present invention. DETAILED DESCRIPTION

[0019] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0020] The present invention discloses an interrupt management device connected between a central processing unit and a sub-device, wherein the interrupt management device converts the interrupt state of the interrupt source in the sub-device into corresponding interrupt information and reports it to the central processing unit through a bus. The sub-device may be a subsystem or other equipment.

[0021] refer to Figure 1The interrupt management device includes an interrupt latch management module 10, a polling management module 20 and a bus message trigger module 30. The interrupt latch management module 10 includes M groups of interrupt functions 11, each group of the interrupt functions 11 corresponds to N independent interrupt sources, and M and N are both integers greater than or equal to 2; each interrupt source corresponds to a register 12, and the M groups of interrupt functions 11 communicate with M×N interrupt sources respectively, and manage the corresponding registers 12 according to the interrupt status of the interrupt source. When the interrupt function 11 receives an interrupt pulse sent by the interrupt source, the interrupt status of the interrupt source is stored in the register 12 corresponding to the interrupt source, and the register 12 storing the interrupt status is called a valid register 12. The polling management module 20 assigns an independent weight configuration to each group of interrupt functions 11, and performs weighted polling arbitration on the M×N registers 12 corresponding to the M groups of interrupt functions 11 according to the corresponding weights. When the register 12 selected by the polling arbitration is a valid register 12, the corresponding interrupt information is generated and transmitted to the bus message trigger module 30; the bus message trigger module 30 reports the interrupt information to the bus, and clears the interrupt status corresponding to the valid register 12 after the effective reporting.

[0022] After reporting the interrupt information to the bus, a reporting feedback signal is returned to the interrupt latch management module 10, so that the interrupt function 11 clears the currently reported interrupt status of the valid register 12 according to the reporting feedback signal.

[0023] The interrupt management device is used to execute an interrupt management method, which includes: when an interrupt request occurs at the interrupt source, the corresponding interrupt pulse is transmitted to the corresponding interrupt function 11, and when the interrupt function 11 receives the interrupt pulse sent by the interrupt source, the interrupt state of the interrupt source is stored in the register 12 corresponding to the interrupt source, and the register 12 storing the interrupt state is called a valid register 12; an independent weight configuration is assigned to each group of interrupt functions 11, and weighted polling arbitration is performed on M groups of M×N registers 12 corresponding to the interrupt functions 11 according to the corresponding weights. When the register 12 selected by the polling arbitration is a valid register 12, the corresponding interrupt information is generated and the interrupt information is output to the bus for reporting, and a reporting feedback signal is returned to the corresponding interrupt function 11, and the interrupt function 11 clears the interrupt state stored in the currently reported valid register 12 according to the reporting feedback signal.

[0024] Wherein, the interrupt information includes the index of the interrupt function 11 where the interrupt corresponding to the valid register 12 is located and the location index of the interrupt source. Outputting the interrupt information to the bus for reporting is specifically: composing the interrupt information into an AXI packet and sending it to the bus. Specifically, the bus message trigger module 30 composes the interrupt information into an AXI packet and sends it to the bus. After the AXI protocol returns the corresponding handshake signal, the bus message trigger module 30 will return a ready signal to the polling management module 20. The polling management module 20 ends this arbitration according to the ready signal to proceed to the next weighted polling arbitration, and transmits the completion signal as a reporting feedback signal to the interrupt latch management module 10, so that the interrupt latch management module 10 clears the interrupt status stored in the currently reported valid register 12 according to the reporting feedback signal. The AXI protocol completes the reporting of the interrupt after each bus access successfully shakes hands with the destination.

[0025] In this embodiment, the weight of the interrupt function 11 matches the priority of the interrupt function 11. The higher the priority of the interrupt function 11, the higher the weight of the interrupt function 11. The interrupt function 11 can manage one or more registers at the same time.

[0026] In actual applications, taking the case where the number of interrupt functions 11 (Function) is 101 as an example, each interrupt function 11 corresponds to 16 interrupt sources to support 16 interrupts, for a total of 11×16=1616 interrupts.

[0027] When an interrupt occurs at each interrupt source, the interrupt status is transmitted to the interrupt function 11 in the form of a pulse. The interrupt function 11 uses a register to identify the interrupt status for each interrupt source. A 0 in the register indicates that the interrupt source has no interrupt request, and a 1 indicates that the interrupt source has an interrupt to be issued. When any number of interrupt pulses from the 1616 interrupt sources arrive, the interrupt function 11 sets the corresponding register to 1. After receiving the feedback signal from the polling management module 20, the corresponding register will be cleared to 0. Of course, in addition to this, when one or several of the interrupt functions 11 initiate a clear command, the registers corresponding to the interrupt function 11 will be uniformly cleared. When the interrupt latch management module 10 receives a valid clear signal controlled by the software, all registers 12 (1616 registers) corresponding to the interrupt functions 11 will be cleared.

[0028] The polling management module 20 has a weighted polling arbitration algorithm. In the first step of the loop monitoring, the interrupt status of 1616 registers is selected when a certain register 12 is polled to be 1, and the number of the interrupt function 11 and the number of the register 12 or the interrupt source are recorded. These numbers are passed as interrupt information to the downstream module-bus message trigger module 30, and a valid signal is set at the same time to tell the downstream that valid interrupt information needs to be output. After the polling management module 20 sets the valid signal valid, the bus message trigger module 30 starts to act, and uses the interrupt information transmitted by the polling management module 20 as data to form an AXI packet and send it to the bus. Then, the AXI corresponding handshake signal is sent to the polling management module 20, indicating that the interrupt has been reported: the ready signal-Ready signal is returned to the polling management module 20, and the arbitration ends. The polling management module 20 returns the reporting feedback signal-complete signal to the interrupt latch management module 10, and the interrupt latch management module 10 clears the corresponding register to 0. At the same time, the polling management module 20 continues to poll, looking for the next valid register, and starts the next round of interrupt reporting.

[0029] Among them, AXI: Advanced eXtensible Interface, is a high-performance, low-latency on-chip bus protocol; FIFO: First Input First Output, refers to first-in, first-out; APB: Advanced Peripheral Bus, means peripheral bus; AHB: Advanced High Performance Bus, advanced high-performance bus.

[0030] Among them, different weights can be configured for each interrupt function 11, and the size of the weight determines the number of times each interrupt function 11 is arbitrated in each arbitration cycle. Of course, the same weight can also be configured for each interrupt function 11, in which case all interrupt functions 11 have the same priority.

[0031] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A method for managing interrupts of a computer processor, characterized in that: include: An interrupt latch management module is set, in which M groups of interrupt functions are set, each group of interrupt functions corresponds to N independent interrupt sources, and M and N are both integers greater than or equal to 2; Each interrupt source corresponds to a register, the M groups of interrupt functions communicate with M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt source; When an interrupt request is generated by the interrupt source, a corresponding interrupt pulse is transmitted to the corresponding interrupt function. When the interrupt function receives the interrupt pulse sent by the interrupt source, the interrupt state of the interrupt source is stored in the register corresponding to the interrupt source. The register storing the interrupt state is called a valid register. An independent weight configuration is assigned to each group of interrupt functions, and weighted polling arbitration is performed on the M×N registers corresponding to the M groups of interrupt functions according to the corresponding weights. When the register selected by the polling arbitration is a valid register, the corresponding interrupt information is generated and output to the bus for reporting.

2. The interrupt management method according to claim 1, characterized in that: The interrupt information includes an index of an interrupt function to which the interrupt corresponding to the valid register belongs and a location index of an interrupt source.

3. The interrupt management method according to claim 1, wherein: Outputting the interrupt information to the bus for reporting specifically includes: forming the interrupt information into an AXI packet and sending it to the bus.

4. The interrupt management method according to claim 1, wherein: The weight of the interrupt function matches the priority of the interrupt function. The higher the priority of the interrupt function, the higher the weight of the interrupt function.

5. The interrupt management method according to claim 1, wherein: The method further comprises the steps of: clearing the interrupt status stored in the corresponding valid register after reporting the interrupt information to the bus.

6. An interrupt management device for a computer processor, characterized in that: It includes an interrupt latch management module, a polling management module and a bus message trigger module. The interrupt latch management module includes M groups of interrupt functions, each group of the interrupt functions corresponds to N independent interrupt sources, and M and N are both integers greater than or equal to 2; each interrupt source corresponds to a register, and the M groups of interrupt functions communicate with M×N interrupt sources respectively, and manage the corresponding registers according to the interrupt status of the interrupt source. When the interrupt function receives an interrupt pulse sent by the interrupt source, the interrupt status of the interrupt source is stored in the register corresponding to the interrupt source, and the register storing the interrupt status is called a valid register; The polling management module assigns an independent weight configuration to each group of interrupt functions, performs weighted polling arbitration on the M×N registers corresponding to the M groups of interrupt functions according to the corresponding weights, and generates corresponding interrupt information when the register selected by the polling arbitration is a valid register and transmits the interrupt information to the bus message trigger module; The bus message triggering module reports the interrupt information to the bus.

7. The interrupt management device according to claim 6, characterized in that: The interrupt information includes an index of an interrupt function to which the interrupt corresponding to the valid register belongs and a location index of an interrupt source.

8. The interrupt management device according to claim 6, characterized in that: The bus message triggering module composes the interrupt information into an AXI packet and sends it to the bus.

9. The interrupt management device according to claim 6, characterized in that: The bus message trigger module also returns a reporting feedback signal to a corresponding interrupt function through the polling management module, and the interrupt function clears the interrupt status of the currently reported valid register according to the reporting feedback signal.

10. The interrupt management device according to claim 6, characterized in that: The weight of the interrupt function matches the priority of the interrupt function. The higher the priority of the interrupt function, the higher the weight of the interrupt function.

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