Communication method and device based on hardware blocking and electronic equipment

Abstract

The invention relates to the technical field of chip communication, and discloses a communication method based on hardware blocking, which comprises the following steps: under the condition of entering a data receiving state, transmitting received to-be-processed data to a specified address; under the condition of entering the blocking state, processing the to-be-processed data of the specified address; and when the processing of the to-be-processed data of the specified address is completed, exiting from the blocking state so as to enter the data receiving state again. The problems of delay uncertainty and time sequence void caused by software switch blocking are avoided, so that the problems of system delay increase and interrupt response uncertainty caused by increase of software processing transactions in related technologies are solved. Moreover, the performance of the system is not affected, the problems of other devices on the I2C bus are not caused, the situation that the whole I2C bus is locked due to abnormity is avoided, and the communication efficiency and stability of the NFC chip in a multi-task environment are improved. The invention further discloses a communication device based on hardware blocking and electronic equipment.

Description

Technical Field

[0001] The present application relates to the field of chip communication technology, for example, to a communication method and device based on hardware blocking, and an electronic device. Background Art

[0002] In I2C (Inter-Integrated Circuit) communications, as application complexity increases, the software needs to handle more and more transactions, and the system delay at the application layer and even the interrupt response delay are becoming more and more uncertain.

[0003] In order to handle interrupt delay, the related art discloses a solution using stretch-clock, where the slave device pulls the SCL (Serial Clock Line) line low to suspend a transmission, and the transmission continues only when the SCL line is released to a high level. This process is called clock stretching.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] If the stretch-clock solution is used, the clock stretching mechanism may cause data transmission delays in the system, affecting the overall performance of the system. In addition, since the communication on the I2C bus is synchronous, the clock stretching behavior of a slave device may affect the communication of other devices on the bus, resulting in data transmission errors or communication failures, which may affect other devices on the I2C bus.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a communication method and device based on hardware blocking, and an electronic device, which implement the blocking function of I2C communication data without affecting system performance and other devices on the I2C bus.

[0009] In some embodiments, the communication method based on hardware blocking is applied to an NFC (Near Field Communication) chip, including: when entering a data receiving state, transmitting the received data to be processed to a designated address; when entering a blocking state, processing the data to be processed at the designated address; when the processing of the data to be processed at the designated address is completed, exiting the blocking state to re-enter the data receiving state.

[0010] Optionally, when a STOP signal sent by the master device is received, a STOP interrupt is executed to enter a blocking state to perform data processing.

[0011] Optionally, the data receiving state is entered in the following manner: receiving a write address sent by a master device; and entering the data receiving state after matching the write address.

[0012] Optionally, when the processing of the pending data at the specified address is completed, exiting the blocking state includes: when the processing of the pending data at the specified address is completed, sending response data to the master device and clearing the STOP interrupt.

[0013] In some embodiments, the communication method based on hardware blocking is applied to a master device, including: controlling the NFC chip to enter a data receiving state; sending the data to be processed to the NFC chip; controlling the chip to enter a blocking state to perform data processing; and when the NFC chip exits the blocking state, controlling the NFC chip to re-enter a data receiving state.

[0014] Optionally, controlling the NFC chip to enter a data receiving state includes: sending a write address to the NFC chip.

[0015] Optionally, controlling the chip to enter a blocking state includes: sending a STOP signal to the NFC chip.

[0016] Optionally, when the NFC chip exits the blocking state, controlling the NFC chip to re-enter the data receiving state includes: after receiving the response data from the NFC chip, resending the write address to the NFC chip.

[0017] In some embodiments, the hardware blocking-based communication device includes: a processor and a memory storing program instructions, and the processor is configured to execute the hardware blocking-based communication method as described above when running the program instructions.

[0018] In some embodiments, the electronic device includes: an electronic device body; and a communication device based on hardware blocking as described above, installed in the electronic device body.

[0019] The communication method and device based on hardware blocking, and the electronic device provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, first, when the NFC chip enters the data receiving state, the received data to be processed is transmitted to a preset designated address, ensuring that the data can be temporarily stored and providing a buffer for subsequent processing. When the system detects a signal that needs to be blocked, it enters the blocking state, at which time the hardware will take over and process the data to be processed in the designated address, effectively avoiding the problems of software processing timeliness and timing holes, and enhancing the efficiency and reliability of data processing. Finally, once the data to be processed at the designated address is completely processed, it exits the blocking state and re-enters the data receiving state to prepare to receive and process new data streams. The disclosed embodiment blocks I2C data reception by hardware, and then reopens I2C data reception according to the software process, thereby solving the problems of increased system delay and uncertainty of interrupt response caused by increased software processing transactions in the related art. In addition, the disclosed embodiment will not affect the performance of its own system, nor will it cause problems with other devices on the I2C bus, avoiding the situation where the entire I2C bus is locked due to anomalies, improving the communication efficiency and stability of the NFC chip in a multi-tasking environment, and ensuring the continuity and reliability of data transmission.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of a host continuously sending multiple requests according to an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of an implementation environment of a communication method based on hardware blocking according to an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of a communication method based on hardware blocking provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another communication method based on hardware blocking provided by an embodiment of the present disclosure;

[0027] Figure 5 is an application schematic diagram of a communication method based on hardware blocking provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a schematic diagram of a communication device based on hardware blocking provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] The communication protocol between the NFC chip and the host is called the NCI (Near Field Communication Interface) specification. Figure 1As shown in the figure, the NFC chip acts as a slave of I2C. The host will concurrently request NFC chip services in a multi-tasking (multi-APP) state. When two requests are ready, the underlying hardware will send the next request at a very short time interval after sending one request. Usually, the interval between two adjacent requests is only 500us, and it will be shorter in extreme cases. The NFC chip firmware does not have time to process the two requests. The NFC chip firmware takes a certain amount of time to process instructions, and the processing time is related to the system scheduling. As long as the host sends the request correctly, the NFC chip replies with an ACK (Acknowledgement) signal for each byte of data to confirm the host, then it is considered that the NFC chip has correctly received the request. After that, as long as the NFC chip cannot give the response data within the specified time, the host will think that the NFC chip is abnormal and will use hardware to reset the NFC chip, which will cause a fatal error.

[0036] Therefore, it is necessary to control communication congestion so that the NFC chip has enough time to process data. Figure 2 FIG. 1 is a schematic diagram of an implementation environment of a communication method based on hardware blocking according to an embodiment of the present disclosure. Figure 2 As shown, the implementation environment may include a main device 100 and an NFC chip 200 .

[0037] The host device 100 controls the operating state of the NFC chip 200 through data and command signals, thereby utilizing the hardware logic of the chip for blocking and unblocking in cooperation with the software process to solve the timeliness and timing holes of software processing.

[0038] Combination Figure 3 As shown, the embodiment of the present disclosure provides a communication method based on hardware blocking, which is applied to an NFC chip, including:

[0039] S301, when the NFC chip enters a data receiving state, the NFC chip transmits the received data to be processed to a designated address.

[0040] S302: When the NFC chip enters a blocking state, the NFC chip processes the data to be processed at the designated address.

[0041] S303, when the processing of the pending data at the designated address is completed, the NFC chip exits the blocking state to re-enter the data receiving state.

[0042] Using the communication method based on hardware blocking provided by the embodiment of the present disclosure, first, when the NFC chip enters the data receiving state, the received data to be processed is transmitted to a preset designated address, ensuring that the data can be temporarily stored and providing a buffer for subsequent processing. When the system detects a signal that needs to be blocked, it automatically enters the blocking state. At this time, the hardware will take over and process the data to be processed in the designated address, effectively avoiding the problems of software processing timeliness and timing holes, and enhancing the efficiency and reliability of data processing. Finally, once the data to be processed at the designated address is completely processed, the NFC chip exits the blocking state and re-enters the data receiving state, ready to receive and process new data streams. By blocking I2C data reception by hardware and then reopening I2C data reception according to the software process, the problems of increased system delay and uncertainty in interrupt response caused by an increase in software processing transactions in the prior art are solved.

[0043] In addition, the embodiments of the present disclosure will not affect the performance of the NFC system itself, nor will it cause problems with other devices on the I2C bus, thus avoiding the serious consequence of the entire I2C bus being locked due to anomalies, improving the communication efficiency and stability of the NFC chip in a multi-tasking environment, and ensuring the continuity and reliability of data transmission, which is of great significance for improving the I2C communication performance of the NFC chip.

[0044] Optionally, when a STOP signal sent by the master device is received, a STOP interrupt is executed to enter a blocking state to perform data processing.

[0045] In an embodiment of the present disclosure, when the NFC chip receives a STOP signal sent by a host device (such as a smart phone), the NFC chip triggers a STOP interrupt and then enters a blocking state to process data. Specifically, first, the NFC chip listens for communication signals from the host device on the I2C bus. When the STOP signal is detected, the hardware logic of the NFC chip responds immediately and triggers a STOP interrupt. At this time, the NFC chip stops receiving data and enters a predefined blocking state. In the blocking state, the NFC chip starts processing previously received data, including temporary storage, verification, decoding, and execution of corresponding operations. After the data processing is completed, the NFC chip exits the blocking state and prepares to receive new data or commands again.

[0046] This ensures that the data will not be interrupted by new data streams while being processed, thus avoiding data loss or processing errors and enhancing the reliability of data transmission. At the same time, by entering the blocking state immediately after the STOP signal, the NFC chip can quickly respond to the host device's commands, improving the efficiency of communication. In addition, this mechanism also helps to reduce the waiting time of the host device waiting for the NFC chip to respond, optimizing the overall system performance.

[0047] Optionally, the data receiving state is entered in the following manner: receiving a write address sent by a master device; and entering the data receiving state after matching the write address.

[0048] In the disclosed embodiment, first, the NFC chip waits for a signal from the master device on the I2C bus. When the master device sends a write address, the NFC chip receives the address. The logic circuit inside the NFC chip performs address matching and compares the received address with the address preset inside the chip to confirm whether it is the target device. Once the address is matched successfully, the NFC chip confirms the communication target of the master device, enters the data receiving state, and prepares to receive the data sent subsequently.

[0049] The NFC chip will receive data only when the address is matched successfully, which prevents data from being mistakenly sent to non-target devices and enhances the accuracy and security of communication. At the same time, the address matching mechanism also improves communication efficiency, allowing the NFC chip to be ready to receive data immediately after receiving the correct address, reducing unnecessary data processing and energy consumption.

[0050] Optionally, when the processing of the pending data at the specified address is completed, exiting the blocking state includes: when the processing of the pending data at the specified address is completed, sending response data to the master device and clearing the STOP interrupt.

[0051] In the disclosed embodiment, when the data to be processed at the specified address is completely processed, the chip will exit the blocking state. Specifically, first, after the NFC chip completes a series of processing operations on the data in the specified address, such as data verification, decoding, or executing corresponding functions, it sends response data to the master device through the I2C bus. This response data may be a confirmation of the master device's instructions, the result of data transmission, or a further request. After sending the response data, the NFC chip clears the STOP interrupt set by receiving the STOP signal, and returns the hardware logic of the NFC chip to the normal state, ready to receive new communication instructions or data.

[0052] In this way, the bidirectionality and synchronization of communication are ensured, so that the host device can obtain feedback from the NFC chip in time, so that it can make the next operation or decision based on the response data. At the same time, by clearing the STOP interrupt, the NFC chip can quickly respond to new communication requests, improving the efficiency of communication and the response speed of the system. In addition, communication errors or data loss caused by unclear interrupts are avoided, which enhances the stability and reliability of the system.

[0053] Combination Figure 4 As shown, the embodiment of the present disclosure provides another communication method based on hardware blocking, which is applied to a master device, including:

[0054] S401, the host device controls the NFC chip to enter a data receiving state.

[0055] S402, the host device sends the data to be processed to the NFC chip.

[0056] S403, the master device controls the chip to enter a blocking state to perform data processing.

[0057] S404: When the NFC chip exits the blocking state, the master device controls the NFC chip to re-enter the data receiving state.

[0058] In the disclosed embodiment, the master device controls the NFC chip to enter the data receiving state by sending specific control commands or address information to ensure that the chip is ready to receive data. Secondly, the master device sends the data to be processed to the NFC chip through the I2C bus. The data may contain instructions, configuration parameters, or information that needs to be processed by the NFC chip. In order to ensure the integrity and accuracy of data processing, the master device controls the NFC chip to enter a blocking state. In the blocking state, the NFC chip processes the received data without responding to new data requests, thereby avoiding interruptions and interference in the data processing process. Finally, once the NFC chip has completed data processing, the master device will control the NFC chip to exit the blocking state and re-enter the data receiving state to prepare to receive the next batch of data or new instructions.

[0059] Optionally, controlling the NFC chip to enter a data receiving state includes: sending a write address to the NFC chip.

[0060] In the disclosed embodiment, the master device sends a write address to the NFC chip through the I2C bus to identify a specific register or memory area so that the NFC chip knows the target location of the data to be received. Then, after the NFC chip receives the write address, the internal logic circuit will identify the write address and configure the internal path to direct the subsequent received data to the specified address. Once the configuration is completed, the NFC chip enters the data receiving state and receives data from the master device.

[0061] Only when the NFC chip recognizes and confirms the write address will it start receiving data, which prevents data from being mistakenly written to an unexpected area of ​​the NFC chip. At the same time, this address-based control mechanism also improves the efficiency of data transmission, allowing the host device to accurately control the flow of data and ensure that data can be written to the NFC chip quickly and correctly. In addition, this approach also enhances the flexibility and scalability of the system, because by changing the write address, the host device can easily communicate with different functional areas on the NFC chip without changing the hardware connection.

[0062] Optionally, controlling the chip to enter a blocking state includes: sending a STOP signal to the NFC chip.

[0063] In the disclosed embodiment, the process of controlling the NFC chip to enter the blocking state is achieved by sending a STOP signal. Specifically, first, after the master device completes sending data to the NFC chip, it sends a STOP signal to the NFC chip through the I2C bus. The STOP signal is a control signal used in the I2C protocol to mark the end of a data transmission. After the NFC chip detects the STOP signal, it recognizes that the signal indicates the end of the current data transmission cycle according to the I2C protocol, and triggers the internal STOP interrupt, and then enters the blocking state.

[0064] The introduction of the STOP signal enables the master device to clearly identify the end of data transmission, avoiding data overflow or loss. The method of controlling the NFC chip to enter a blocking state by sending a STOP signal provides an effective data end identification and processing mechanism for I2C communication, ensuring the stability of data transmission and the efficiency of NFC chip data processing, and plays a key role in improving the performance and reliability of the entire NFC system.

[0065] Optionally, when the NFC chip exits the blocking state, controlling the NFC chip to re-enter the data receiving state includes: after receiving the response data from the NFC chip, resending the write address to the NFC chip.

[0066] In the disclosed embodiment, after the NFC chip exits the blocking state, the master device controls the NFC chip to enter the data receiving state by resending the write address. Specifically, first, after the NFC chip completes data processing and exits the blocking state, the master device waits for the NFC chip to send response data to confirm that the data in the previous stage has been successfully processed. Once the master device successfully receives the response data from the NFC chip, it indicates that the NFC chip is ready to receive new data. At this time, the master device again sends a new write address to the NFC chip through the I2C bus. After receiving the new write address, the NFC chip identifies the address and configures the internal path, prepares to store the received data to the specified location, and then enters the data receiving state. In this way, the NFC chip can start receiving new data transmission, and the master device can continue to send subsequent data.

[0067] In this way, through clear STOP signals and response data, the data exchange between the host device and the NFC chip is more orderly and controllable. At the same time, the NFC chip can quickly switch from one processing cycle to the next receiving cycle, reducing waiting and idle time and improving the system's response speed.

[0068] In practical applications, the embodiment of the present disclosure uses the main device as the host and the NFC chip as the slave, and realizes controllable communication blocking through the transmission of signals and data between the host and the slave, such as Figure 5 shown.

[0069] S501, sending a write address.

[0070] S502, entering the data receiving state after performing write address matching.

[0071] S503, sending data to be processed.

[0072] S504: The received data to be processed is transmitted to a designated address.

[0073] S505, send a STOP signal.

[0074] S506, processing the data to be processed at the designated address.

[0075] S507, when the processing of the data to be processed at the designated address is completed, sending response data.

[0076] S508, clear the STOP interrupt and exit the blocking state.

[0077] The disclosed embodiment uses a hardware unblocking method to achieve the blocking function of I2C communication data without loss of performance and without causing I2C bus derivative problems.

[0078] Combination Figure 6 As shown, the embodiment of the present disclosure provides a communication device 70 based on hardware blocking, including a processor (processor) 600 and a memory (memory) 601. Optionally, the device 60 may also include a communication interface (Communication Interface) 602 and a bus 603. Among them, the processor 600, the communication interface 602, and the memory 601 can communicate with each other through the bus 603. The communication interface 602 can be used for information transmission. The processor 600 can call the logic instructions in the memory 601 to execute the communication method based on hardware blocking of the above embodiment.

[0079] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0080] The memory 601 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 600 executes the functional application and data processing by running the program instructions / modules stored in the memory 601, that is, implementing the communication method based on hardware blocking in the above embodiment.

[0081] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0082] The embodiments of the present disclosure provide an electronic device, including: an electronic device body, and the above-mentioned communication device based on hardware blocking. The communication device based on hardware blocking is installed on the electronic device body. The installation relationship described here is not limited to placement inside the electronic device body, but also includes installation connections with other components of the electronic device, including but not limited to physical connections, electrical connections or signal transmission connections, etc. Those skilled in the art can understand that the communication device based on hardware blocking can be adapted to a feasible electronic device body, thereby realizing other feasible embodiments.

[0083] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0084] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0085] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0086] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0087] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A communication method based on hardware blocking, characterized in that: Applied to NFC chips, including: When entering the data receiving state, the received data to be processed is transmitted to the specified address; In the case of entering the blocking state, the pending data at the specified address is processed; When the pending data at the specified address is processed, the blocking state is exited to re-enter the data receiving state.

2. The communication method according to claim 1, characterized in that: When receiving the STOP signal sent by the master device, the STOP interrupt is executed to enter the blocking state for data processing.

3. The communication method according to claim 1, characterized in that: Enter the data receiving state as follows: Receive the write address sent by the master device; After the write address is matched, it enters the data receiving state.

4. The communication method according to any one of claims 1 to 3, characterized in that: When the pending data at the specified address is processed, exit the blocking state, including: When the pending data at the specified address is processed, the response data is sent to the master device and the STOP interrupt is cleared.

5. A communication method based on hardware blocking, characterized in that: Applicable to main equipment, including: Control the NFC chip to enter the data receiving state; Send the data to be processed to the NFC chip; The control chip enters a blocking state to process data; When the NFC chip exits the blocking state, the NFC chip is controlled to re-enter the data receiving state.

6. The communication method according to claim 5, characterized in that: Control the NFC chip to enter the data receiving state, including: Send write address to NFC chip.

7. The communication method according to claim 5, characterized in that: The control chip enters the blocking state, including: Send a STOP signal to the NFC chip.

8. The communication method according to any one of claims 5 to 7, characterized in that: When the NFC chip exits the blocking state, the NFC chip is controlled to re-enter the data receiving state, including: After receiving the response data from the NFC chip, resend the write address to the NFC chip.

9. A communication device based on hardware blocking, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the hardware blocking-based communication method according to any one of claims 1 to 8 when running the program instructions.

10. An electronic device, characterized in that: include: Electronic device body; The hardware blocking-based communication device as described in claim 9 is installed in the electronic device body.

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