Data processing method and device, medium and chip

Abstract

The invention discloses a data processing method and device, a medium and a chip. The method comprises the following steps: determining the degree of parallelism of a to-be-executed calculation task; in a preset operation stage, reading two operands from each memory according to a parallel sequence based on the degree of parallelism; forming a first array by the operand with the front address in the two operands read from each memory in each parallel sequence, and forming a second array by the operand with the rear address in the two operands read from each memory in each parallel sequence; respectively rearranging the first array and the second array according to a first preset rule to obtain a third array and a fourth array; and obtaining operands with the same sequence in the third array and the fourth array as two operands for the same butterfly computation. According to the method, no matter how much the parallelism is, the rearrangement stage can be determined based on the parallelism, butterfly computation can be performed by rearranging the read operands according to the first preset rule in the rearrangement stage, the parallelism is conveniently switched, and a logic circuit on an FPGA board does not need to be rewritten.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a data processing method, device, medium and chip. Background Art

[0002] With the continuous development of artificial intelligence and big data algorithms, protecting data security and privacy is becoming increasingly important. Using encryption algorithms to encrypt data is an important way to protect data security. At present, mainstream privacy computing technologies such as Fully Homomorphic Encryption (FHE) and Zero Knowledge Proof (ZKP) involve a large number of polynomial multiplication calculations. If calculated directly, the complexity is relatively high. For example, the time complexity of multiplying two polynomials of length N is O(N²). Number Theoretic Transform (NTT) can optimize the calculation of polynomial multiplication and reduce its time complexity to O(Nlog2N). Among them, NTT is an equivalent form of Fast Fourier Transform (FFT) in the field of number theory, which performs transformations under finite fields.

[0003] Whether it is the forward number theory transform (NTT) or the inverse number theory transform (INTT), the calculation speed is an important factor affecting the efficiency of privacy computing. At present, field programmable gate array (FPGA) is usually used to accelerate NTT / INTT in parallel through parallel circuit design. In different operation stages of parallel number theory transform, the positions of operands involved in butterfly calculation in the storage space are not corresponding. Therefore, for different operation stages, it is necessary to rearrange the operands read from the storage space, and then send the rearranged data to the computing unit for calculation. However, in the prior art, the mapping relationship of rearranging operands under different degrees of parallelism is different, and different mapping relationships correspond to different logic circuits on the FPGA board. Therefore, when the degree of parallelism is changed, the logic circuit on the FPGA board needs to be rewritten. Summary of the invention

[0004] The main purpose of this application is to propose a data processing method, device, medium and chip, which aims to solve the problem in the prior art that when the parallelism of number theory transformation is changed, the logic circuit on the FPGA board needs to be rewritten.

[0005] To achieve the above purpose, this application proposes a data processing method, comprising: Determine the degree of parallelism of a computing task to be executed; the computing task to be executed is to perform a number-theoretic transformation or an inverse number-theoretic transformation on the data to be processed, the computing task to be executed includes a plurality of parallel butterfly calculations, and the degree of parallelism represents the number of butterfly calculations included in one parallel butterfly calculation; the data to be processed includes a plurality of operands; In a preset operation stage of the computing task to be executed, two operands are read from a preset address in each memory at a time in an order of parallel butterfly calculations based on the degree of parallelism; the preset operation stage is determined based on the degree of parallelism; the number of operands obtained by each parallel butterfly calculation is twice the degree of parallelism; The operands read from each memory in each parallel butterfly calculation order are composed of the operand with the earlier address into a first array and the operand with the later address into a second array; Rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array; The operands in the same order in the third array and the fourth array are obtained as two operands participating in the same butterfly calculation.

[0006] In the embodiment of the present application, the data to be processed is pre-stored in respective memories whose number is the same as the degree of parallelism according to the degree of parallelism, and the number of operands stored in each memory is the same.

[0007] In the embodiment of the present application, the depth of each memory is preconfigured as , the storage addresses in each memory are y∈[0, ); The storage addresses of the memories are sequentially stored with the first To ( -1) operands; Where N= , K , N represents the sequence length of the data to be processed, K represents the degree of parallelism, y represents the storage address of the memory, t represents the number of the memory, t∈[0,K).

[0008] In the embodiment of the present application, the range of the preset operation stage is: r∈[0, b-1]; Among them, r represents the operation stage of the computing task to be executed, K , K represents the degree of parallelism.

[0009] In the embodiment of the present application, the first preset rule includes: When K=2, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; When K>2, When r∈[0,b-2], g'[2*m+grp* ]=g[m+grp* ], g'[2*m+1+grp* ]=h[m+grp* ], h'[2*m+grp* ]=g[m+ +grp* ], h'[2*m+1+grp* ]=h[m+ +grp* ]; When r=b-1, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array.

[0010] In the embodiment of the present application, after taking the operands of the same order in the third array and the fourth array as two operands of the same butterfly calculation and performing the butterfly calculation, the data processing method further includes: The calculation result with the earlier order among the two calculation results obtained by each butterfly calculation is formed into a fifth array, and the calculation result with the later order is formed into a sixth array; The fifth array and the sixth array are rearranged according to a second preset rule to obtain a seventh array and an eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

[0011] In the embodiment of the present application, the second preset rule includes: When K=2, s'[2*u]=s[2*u], s'[2*u+1]=p[2*u], p'[2*u]=s[2*u+1], p'[2*u+1]=p[2*u+1]; When K>2, When r∈[0,b-2], s'[2*m+grp* ]=s[m+grp* ]; s'[2*m+1+grp* ]=p[m+grp* ]; p'[2*m+grp* ]=s[m+ +grp* ]; p'[2*m+1+grp* ]=p[m+ +grp* ]; When r=b-1, s'[2*u]=s[2*u]; s'[2*u+1]=p[2*u]; s'[2*u]=s[2*u+1]; p'[2*u+1]=p[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

[0012] The present application also proposes a data processing device, comprising: an acquisition module, configured to determine the degree of parallelism of a computing task to be executed; the computing task to be executed is to perform a number-theoretic transformation or an inverse number-theoretic transformation on the data to be processed, the computing task to be executed includes a plurality of parallel butterfly calculations, the degree of parallelism indicates the number of butterfly calculations included in one parallel butterfly calculation; the data to be processed includes a plurality of operands; In a preset operation stage of the computing task to be executed, two operands are read from a preset address in each memory at a time in an order of parallel butterfly calculations based on the degree of parallelism; the preset operation stage is determined based on the degree of parallelism; the number of operands obtained by each parallel butterfly calculation is twice the degree of parallelism; A processing module, used for forming a first array with an operand with a front address and a second array with an operand with a back address among two operands read from each memory in each parallel butterfly calculation order; Rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array; The operands in the same order in the third array and the fourth array are obtained as two operands participating in the same butterfly calculation.

[0013] In the embodiment of the present application, the data to be processed is pre-stored in respective memories whose number is the same as the degree of parallelism according to the degree of parallelism, and the number of operands stored in each memory is the same.

[0014] In the embodiment of the present application, the depth of each memory is preconfigured as , the storage addresses in each memory are y∈[0, ); The storage addresses of the memories are sequentially stored with the first To ( -1) operands; Where N= , K , N represents the sequence length of the data to be processed, K represents the degree of parallelism, y represents the storage address of the memory, t represents the number of the memory, t∈[0,K).

[0015] In the embodiment of the present application, the processing module determines the range of the preset operation stage based on the following method: r∈[0, b-1]; Among them, r represents the operation stage of the computing task to be executed, K , K represents the degree of parallelism.

[0016] In the embodiment of the present application, the first preset rule includes: When K=2, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; When K>2, When r∈[0,b-2], g'[2*m+grp* ]=g[m+grp* ], g'[2*m+1+grp* ]=h[m+grp* ], h'[2*m+grp* ]=g[m+ +grp* ], h'[2*m+1+grp* ]=h[m+ +grp* ]; When r=b-1, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array.

[0017] In the embodiment of the present application, the processing module is also used for: After taking the operands of the same order in the third array and the fourth array as two operands of the same butterfly calculation, performing the butterfly calculation; The calculation result with the earlier order among the two calculation results obtained by each butterfly calculation is formed into a fifth array, and the calculation result with the later order is formed into a sixth array; The fifth array and the sixth array are rearranged according to a second preset rule to obtain a seventh array and an eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

[0018] In the embodiment of the present application, the second preset rule includes: When K=2, s'[2*u]=s[2*u], s'[2*u+1]=p[2*u], p'[2*u]=s[2*u+1], p'[2*u+1]=p[2*u+1]; When K>2, When r∈[0,b-2], s'[2*m+grp* ]=s[m+grp* ]; s'[2*m+1+grp* ]=p[m+grp* ]; p'[2*m+grp* ]=s[m+ +grp* ]; p'[2*m+1+grp* ]=p[m+ +grp* ]; When r=b-1, s'[2*u]=s[2*u]; s'[2*u+1]=p[2*u]; s'[2*u]=s[2*u+1]; p'[2*u+1]=p[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

[0019] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0020] An embodiment of the present application further provides a chip, which includes a programmable logic circuit and / or program instructions. When the chip works on a computer device, it is used to implement the method described in any of the above embodiments.

[0021] The data processing method in the embodiment of the present application can determine the preset operation stage that needs to be rearranged based on the degree of parallelism when facing pending computing tasks with different degrees of parallelism. After determining the preset operation stage, the butterfly calculation can be performed after the operands read each time in the preset operation stage are rearranged according to the first preset rule. Therefore, the degree of parallelism can be easily switched without rewriting the logic circuit on the FPGA board. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0023] Figure 1 A step diagram of a data processing method in an embodiment of the present application; Figure 2 A module diagram of a data processing device in an embodiment of the present application; Figure 3 A module diagram of a computer-readable storage medium in an embodiment of the present application; The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0024] The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present application, and are not intended to limit the scope of the present application in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0025] Those skilled in the art know that the embodiments of the present application can be implemented as a system, device, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0026] According to the implementation manner of the present application, a data processing method, device, medium and chip are proposed.

[0027] It should be understood herein that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction rather than having any limiting meaning.

[0028] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0029] Exemplary Methods In the embodiment of the present application, for a sequence length of N (N= ), it has N operands. When performing forward or reverse number theory transformation, there are n operation stages, and the operation stage r∈[0, n-1]. In each operation stage of number theory transformation, all operands need to be butterfly-calculated. Therefore, each operation stage has N operands, each butterfly calculation requires two operands, and each operation stage needs to be performed. butterfly calculations; K is the parallelism of the data to be processed, that is, K butterfly calculations are performed simultaneously in each parallel butterfly calculation order, K= Therefore, in each operation stage, a Parallel butterfly calculations are performed, wherein each parallel butterfly calculation includes K butterfly calculations.

[0030] In addition, in an embodiment of the present application, the degree of parallelism of the data to be processed during number theory transformation is K, that is, there are K memories to provide storage space for each original operand in the data to be processed, and to provide storage space for the operation results of each operation stage in the operation process.

[0031] In the embodiment of the present application, the sequence length of the data to be processed is N, N operands are stored in K memories on average, and N= , K = , so each memory stores operands, so the depth of each memory is , then the storage address range of each memory is y∈[0, ), one operand is stored at each storage address.

[0032] In the embodiment of the present application, the storage addresses of the respective memories are sequentially stored with the first To ( -1) operands, where t represents the memory number, t∈[0,K).

[0033] For example, the sequence length of the data to be processed is 256, and the degree of parallelism is 8, that is, N=256, n=8, K=8, b=3. The degree of parallelism is 8, and there are 8 memories, t∈[0,8), and the depth of each memory is 32, y∈[0,32). Refer to Table 1 below, which is a schematic table of the storage of operands A0-A256 in the data to be processed in each memory numbered RAM0-RAM7.

[0034] Table 1

[0035] Among them, for RAM0, it stores the 0th to 31st operands, namely A0-A31; For RAM1, it stores the 32nd to 63rd operands, i.e. A32-A63; For RAM2, it stores the 64th to 95th operands, i.e. A64-A95; For RAM3, it stores the 96th to 127th operands, i.e. A96-A127; For RAM4, it stores the 128th to 159th operands, i.e. A128-A159; For RAM5, it stores the 160th to 191th operands, i.e. A160-A191; For RAM6, it stores the 192th to 223rd operands, i.e. A192-A223; As for RAM6, it stores the 224th to 255th operands, namely A224-A256.

[0036] In the operation stage r of the number theory transformation, it is necessary to The butterfly calculation is divided into groups, each with Butterfly calculations, that is, each group has For each group, the two operands required for each butterfly calculation have addresses j and j+ , where j represents the order of parallel butterfly calculations.

[0037] For example, taking N=256, n=8 as an example, if the degree of parallelism is 1, the operands A0-A255 are located in the same memory. When r=0 in the operation stage, all operands are located in the same group, and the addresses of the operands A0-A255 in the group are 0-255 respectively.

[0038] When the degree of parallelism is 1, K=1, b=0, that is, only one butterfly operation is performed each time the butterfly is calculated. =128, that is, 128 butterfly calculations are required, and at this time j∈[0, 127).

[0039] When j=0, j and j+ They are 0 and 128 respectively, that is, the addresses of the two operands required in the first butterfly calculation are 0 and 128 respectively in the group, that is, the two operands required are A0 and A128; When j=1, j and j+ They are 1 and 129 respectively, that is, the addresses of the two operands required in the second butterfly calculation are 1 and 129 respectively in the group, that is, the two operands required are A1 and A129; By analogy, when j=127, j and j+ They are 127 and 255 respectively, that is, the addresses of the two operands required in the 128th butterfly calculation are 127 and 255 respectively in the group, that is, the two required operands are A127 and A255.

[0040] However, in parallel operation, K can be 2, 4, 6, etc., and each operand is stored in multiple memories. In this case, two operands need to be read from each memory respectively. In each parallel butterfly calculation, the address of the operand read from each memory is as follows: j and j+ , j represents the order of parallel butterfly calculations. When the degree of parallelism is K, each butterfly calculation requires K butterfly operations.

[0041] For example, referring to Table 1 above, N=256, each stage includes 128 butterfly operations, K=8, and 8 butterfly calculations can be performed each time a parallel butterfly calculation is performed, so 16 parallel butterfly calculations are required, j∈[0,15).

[0042] When j = 0, the addresses of the operands read from RAM0-7 are 0 and 16; When j = 1, the addresses of the operands read from RAM0-7 are 1 and 17; Similarly, when j=15, the addresses of the operands read from RAM0-7 are 15 and 31.

[0043] Then refer to Table 1, when j=0, Read A0 and A16 from RAM0; Read A32 and A48 from RAM1; Read A64 and A80 from RAM2; Read A96 and A112 from RAM3; Read A128 and A144 from RAM4; Read A160 and A176 from RAM5; Read A192 and A208 from RAM6; Read A224 and A240 from RAM7.

[0044] It can be seen that when butterfly calculations are performed in parallel, at the operation stage r=0, the two operands read from each memory are not the actual pair of operands corresponding to each butterfly calculation. For example, A0 and A16 are read from RAM0, but actually A0 and A128 are a pair of operands required for a butterfly calculation, and A16 and A144 are a pair of operands required for a butterfly calculation. Therefore, it is necessary to reorder the operands read from each memory so that each butterfly calculation has the correct two operands to ensure correct calculation.

[0045] Each operation stage has groups, the degree of parallelism is K, K= , that is, a total of memory, r<b, that is, In the operation stage r, the number of butterfly calculation groups of the data to be processed is less than the number of memories. The butterfly calculations in the same group need to be stored across memories. Then the two operands read from the same memory are not the two operands actually required in a butterfly calculation. Therefore, when r<b, the operands read need to be rearranged; when r≥b, that is, ≥ , in the operation stage r, if the number of groups of butterfly calculations of the data to be processed is greater than or equal to the number of memories, then the butterfly calculations in the same group of the data to be processed are stored in the same memory. Therefore, the two operands actually required for the same butterfly calculation can be read from the same memory. Therefore, in each stage when r≥b, the operands read from each memory do not need to be reordered.

[0046] like Figure 1 As shown, in the embodiment of the present application, the data processing method includes the following steps S100-S500: Step S100: Determine the parallelism of the computing task to be executed.

[0047] In step S100, the computing task to be executed is a computing task of performing a forward number theory transformation or an inverse number theory transformation on the processed data, wherein the computing task of the forward number theory transformation or the inverse number theory transformation includes multiple parallel butterfly calculations, and the parallelism of the computing task to be executed represents the number of butterfly calculations included in a parallel butterfly calculation sequence. In addition, the parallelism can be determined according to the number of memories involved, for example, if the number of memories involved in the calculation is 8, then the parallelism is 8, and for another example, if the number of memories involved in the calculation is 4, then the parallelism is 4.

[0048] Step S200: in a preset operation phase of the computing task to be executed, two operands are read from preset addresses in each memory at a time in an order of parallel butterfly calculation based on the degree of parallelism.

[0049] Based on the above description, it can be known that when r<b, the operands read from each memory need to be rearranged. Therefore, in the embodiment of the present application, the preset operation stage is r∈[0, b-1]; r represents the operation stage for executing the computing task, K , K represents the degree of parallelism, that is, in the embodiment of the present application, the preset operation stage that needs to be rearranged can be determined based on the degree of parallelism, for example, the operation stage where r<b is the preset operation stage.

[0050] For example, when K=8 and b=3, it is necessary to reorder the operands read from each memory when the operation stages r=0, 1, and 2; for another example, when K=16 and b=4, it is necessary to reorder the operands read from each memory when the operation stages r=0, 1, 2, and 3.

[0051] In the embodiment of the present application, in each operation stage of the computing task to be executed, when two operands are read from the preset address in each memory, the preset address can be in the order of j and j+ Determine, where j represents the order of parallel butterfly calculations.

[0052] In addition, in the embodiment of the present application, the number of operands obtained in each parallel butterfly calculation sequence is twice the degree of parallelism. For example, assuming the degree of parallelism is 8, then in each parallel butterfly calculation sequence, two operands need to be obtained from 8 memories respectively, and the degree of parallelism is 8, so a total of 16 operands are obtained, and the 16 operands are combined in pairs to form 8 parallel butterfly calculations.

[0053] Step S300: Of the two operands read from each memory in each parallel butterfly calculation order, the operand with the earlier address is formed into a first array, and the operand with the later address is formed into a second array.

[0054] In the embodiment of the present application, taking the above Table 1 as an example, when r = 0, j = 0, A0 and A16 are read from RAM0; Read A32 and A48 from RAM1; Read A64 and A80 from RAM2; Read A96 and A112 from RAM3; Read A128 and A144 from RAM4; Read A160 and A176 from RAM5; Read A192 and A208 from RAM6; Read A224 and A240 from RAM7.

[0055] Among them, A0, A32, A64, A96, A128, A160, A192, and A224 are operands with earlier addresses read from RAM0-7 respectively in the parallel butterfly calculation order of j=0, and thus constitute the first array; A16, A48, A80, A112, A144, A176, A208, and A240 are operands with later addresses read from RAM0-7 respectively in the parallel butterfly calculation order of j=0, and thus constitute the second array.

[0056] Step S400: rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array.

[0057] In the embodiment of the present application, the first preset rule includes case 1 and case 2: Case 1: The degree of parallelism is greater than 2, that is, K>2.

[0058] In case 1, the two stages r∈[0, b-2] and r=b-1 perform different operations on the operand reordering, as follows: When r ∈ [0, b-2], calculate according to the following formulas (1)-(4): g'[2*m+grp* ]=g[m+grp* ] (1) g'[2*m+1+grp* ]=h[m+grp* ] (2) h'[2*m+grp* ]=g[m+ +grp* ] (3) h'[2*m+1+grp* ]=h[m+ +grp* ] (4) When r=b-1, calculate according to the following formulas (5)-(8): g'[2*u]=g[2*u](5) g'[2*u+1]=h[2*u](6) h'[2*u]=g[2*u+1](7) h'[2*u+1]=h[2*u+1](8) Case 2: The degree of parallelism is 2, that is, K=2.

[0059] In case 2, it is only necessary to calculate according to the above formulas (5)-(8).

[0060] In the above formulas (1)-(8), r represents the operation stage of the computing task to be executed, grp represents the group order of the computing task to be executed in the operation stage r, grp∈[0, ), m∈[0, ), u∈[0, ), m and u are both natural numbers.

[0061] g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array. For example, g[m+grp* ] represents the order in the first array (m+grp* ) of the operand; g'[2*m+grp* ] represents the order in the third array (2*m+grp* ) operand; h[m+grp* ] represents the order in the second array (m+grp* ) of the operand; g'[2*m+1+grp* ] represents the order in the third array (2*m+1+grp* ) of the operand; g[m+ +grp* ] represents the order in the first array (m+ +grp* ) of the operand; h'[2*m+grp* ] represents the order in the fourth array is (2*m+grp* ) operand; h[m+ +grp* ] represents the order in the second array (m+ +grp* ) of the operand; h'[2*m+1+grp* ] represents the order in the fourth array is (2*m+1+grp* ) operands.

[0062] Next, examples are given to illustrate situation one and situation two respectively.

[0063] Case 1 Taking the above Table 1 as an example, in Table 1, K=8, b=3, r∈[0, b-2] and r=b-1 in case 1 are r∈[0, 1] and r=2, and each operation stage has 16 parallel butterfly calculations, that is, j∈[0, 16). Next, examples are given for r∈[0, 1] and r=2 respectively.

[0064] When r∈[0,1], r=0,1.

[0065] When r=0, grp∈[0, ), m∈[0,4), that is, grp=0,m=0,1,2,3. Taking j=0 as an example, when j=0, among the operands read from RAM0-7, A0, A32, A64, A96, A128, A160, A192, and A224 form the first array; A16, A48, A80, A112, A144, A176, A208, and A240 form the second array, as shown in Table 2 below: Table 2

[0066] As shown in Table 2 above, the order of A0, A32, A64, A96, A128, A160, A192, and A224 in the first array g[] is 0-7, respectively, and the order of A16, A48, A80, A112, A144, A176, A208, and A240 in the second array h[] is 0-7, respectively.

[0067] When grp=0, m=0 g'[2*m+grp* ]=g[m+grp* ], that is, g'[0]=g[0]; g'[2*m+1+grp* ]=h[m+grp* ], that is, g'[1]=h[0]; h'[2*m+grp* ]=g[m+ +grp* ], that is, h'[0]=g[4]; h'[2*m+1+grp* ]=h[m+ +grp* ], that is, h'[1]=h[4].

[0068] Among them, g'[0] represents the operand with order 0 in the third array, g[0] represents the operand with order 0 in the first array, g'[0]=g[0] represents that the operand with order 0 in the first array is reordered to the position with order 0 in the third array, that is, the operand with order 0 in the third array g'[] is A0; and so on, g'[1]=h[0] represents that the operand with order 0 in the second array is reordered to the position with order 1 in the third array, that is, the operand with order 1 in the third array g'[] is A16; h'[0]=g[4] means that the operand with the order of 4 in the first array is reordered to the position with the order of 0 in the fourth array, that is, the operand with the order of 0 in the fourth array is A128; h'[1]=h[4] means that the operand with the order 4 in the second array is reordered to the position with the order 1 in the fourth array, that is, the operand with the order 1 in the fourth array h'[] is A144.

[0069] When grp=0, m=1 g'[2*m+grp* ]=g[m+grp* ], that is, g'[2]=g[1]; g'[2*m+1+grp* ]=h[m+grp* ], that is, g'[3]=h[1]; h'[2*m+grp* ]=g[m+ +grp* ], that is, h'[2]=g[5]; h'[2*m+1+grp* ]=h[m+ +grp* ], that is, h'[3]=h[5].

[0070] Where g'[2]=g[1] means that the operand with the order 1 in the first array is reordered to the position with the order 2 in the third array, that is, the operand with the order 2 in the third array g'[] is A32; g'[3]=h[1] means reordering the operand with the order 1 in the second array to the position with the order 3 in the third array, that is, the operand with the order 3 in the third array g'[] is A48; h'[2]=g[5] means that the operand with the order of 5 in the first array is reordered to the position with the order of 2 in the fourth array, that is, the operand with the order of 2 in the fourth array is A160; h'[3]=h[5] means that the operand with the order of 5 in the second array is reordered to the position with the order of 3 in the fourth array, that is, the operand with the order of 3 in the fourth array h'[] is A176.

[0071] grp=0,m=2 g'[2*m+grp* ]=g[m+grp* ], that is, g'[4]=g[2]; g'[2*m+1+grp* ]=h[m+grp* ], that is, g'[5]=h[2]; h'[2*m+grp* ]=g[m+ +grp* ], that is, h'[4]=g[6]; h'[2*m+1+grp* ]=h[m+ +grp* ], that is, h'[5]=h[6].

[0072] Where g'[4]=g[2] means that the operand with the order 2 in the first array is reordered to the position with the order 4 in the third array, that is, the operand with the order 4 in the third array g'[] is A64; g'[5]=h[2] means, reorder the operand with the order 2 in the second array to the position with the order 5 in the third array, that is, the operand with the order 5 in the third array g'[] is A80; h'[4]=g[6] means that the operand with the order of 6 in the first array is reordered to the position with the order of 4 in the fourth array, that is, the operand with the order of 4 in the fourth array is A192; h'[5]=h[6] means that the operand with the order of 6 in the second array is reordered to the position with the order of 5 in the fourth array, that is, the operand with the order of 5 in the fourth array h'[] is A208.

[0073] grp=0,m=3 g'[2*m+grp* ]=g[m+grp* ], that is, g'[6]=g[3]; g'[2*m+1+grp* ]=h[m+grp* ], that is, g'[7]=h[3]; h'[2*m+grp* ]=g[m+ +grp* ], that is, h'[6]=g[7]; h'[2*m+1+grp* ]=h[m+ +grp* ], that is, h'[7]=h[7].

[0074] Where g'[6]=g[3] means that the operand with the order 3 in the first array is reordered to the position with the order 6 in the third array, that is, the operand with the order 6 in the third array g'[] is A96; g'[7]=h[3] means, reorder the operand with the order 3 in the second array to the position with the order 7 in the third array, that is, the operand with the order 7 in the third array g'[] is A112; h'[6]=g[7] means that the operand with the order of 7 in the first array is reordered to the position with the order of 6 in the fourth array, that is, the operand with the order of 6 in the fourth array is A224; h'[7]=h[7] means that the operand with the order of 7 in the second array is reordered to the position with the order of 7 in the fourth array, that is, the operand with the order of 7 in the fourth array h'[] is A240.

[0075] At this point, the reordering operation of the 8 pairs of operands taken when r=0, j=0 is completed, as shown in Table 2 above.

[0076] As shown in Table 2 above, after completing the rearrangement of the operands read from each memory when the operation stage r=0, j=0, by analogy, the operands read from each memory when r=0, j=1 to 15 can also be rearranged respectively, which are not listed here one by one.

[0077] Next, an example is given for r=1 as follows: r=1,grp∈[0, ), m∈[0,2), that is, grp=0,1,m=0,1.

[0078] Assume that Table 3 shows the operands obtained after the operation stage r=0 of Table 1 above is completed, wherein B0-B255 are the butterfly calculation results obtained after the operation stage r=0 of the reoperands A0-A255 of the computing task to be executed.

[0079] Table 3

[0080] Taking j=0 as an example, when j=0, B0 and B16 are read from RAM0; B32 and B48 are read from RAM1; B64 and B80 are read from RAM2; B96 and B112 are read from RAM3; B128 and B144 are read from RAM4; B160 and B176 are read from RAM5; B192 and B208 are read from RAM6; B224 and B240 are read from RAM7. Among them, B0, B32, B64, B96, B128, B160, B192, and B224 are operands with the front addresses read from RAM0-7 in the parallel butterfly calculation order of r=1 and j=0, and thus constitute the first array; B16, B48, B80, B112, B144, B176, B208, and B240 are operands with the back addresses read from RAM0-7 in the parallel butterfly calculation order of j=0, and constitute the second array, as shown in Table 4 below: Table 4

[0081] Among them, the order of B0, B32, B64, B96, B128, B160, B192, and B224 in the first array g[] is 0-7 respectively, and the order of B16, B48, B80, B112, B144, B176, B208, and B240 in the second array h[] is 0-7 respectively.

[0082] When grp=0, m=0, g'[2*m+grp* ]=g[m+grp* ], that is, g'[0]=g[0]; g'[2*m+1+grp* ]=h[m+grp* ], that is, g'[1]=h[0]; h'[2*m+grp* ]=g[m+ +grp* ], that is, h'[0]=g[2]; h'[2*m+1+grp* ]=h[m+ +grp* ], that is, h'[1]=h[2].

[0083] When grp=0 and m=1, g'[2*m+grp* ]=g[m+grp* ], that is, g'[2]=g[1]; g’[2*m + 1 + grp* = h[m + grp* , that is, g’[3] = h[1]; h’[2*m + grp* = g[m + + grp* , that is, h’[2] = g[3]; h’[2*m + 1 + grp* = h[m + + grp* , that is, h’[3] = h[3].

[0084] When grp = 1 and m = 0, g’[2*m + grp* = g[m + grp* , that is, g’[4] = g[4]; g’[2*m + 1 + grp* = h[m + grp* , that is, g’[5] = h[4]; h’[2*m + grp* = g[m + + grp* , that is, h’[4] = g[6]; h’[2*m + 1 + grp* = h[m + + grp* , that is, h’[5] = h[6].

[0085] When grp = 1 and m = 1, g’[2*m + grp* = g[m + grp* , that is, g’[6] = g[5]; g’[2*m + 1 + grp* = h[m + grp* , that is, g’[7] = h[5]; h’[2*m + grp* = g[m + + grp* , that is, h’[6] = g[7]; h’[2*m + 1 + grp* = h[m + + grp* , that is, h’[7] = h[7].

[0086] At this point, the reordering operation of the 8 pairs of operands read by r=1, j=0 is completed, as shown in Table 4. In addition, the specific meanings of the above formulas refer to the specific explanation of the examples of r=0, j=0, which will not be repeated here.

[0087] As shown in Table 4 above, after completing the rearrangement of the operands read from each memory when the operation stage r=1, j=0, by analogy, the operands read from each memory when r=1, j=1 to 15 can also be rearranged respectively, which are not listed here one by one.

[0088] The above is a detailed explanation of r∈[0,1], and the following is an example of r=2.

[0089] When r=2, u∈[0, 4), that is, u=0, 1, 2, 3.

[0090] Assume that Table 5 is the operands obtained after the above Table 3 completes the operation stage r=1, wherein C0-C255 are the butterfly calculation results obtained after the operation stage r=1 of the reoperands A0-A255 of the calculation task to be executed.

[0091] Table 5

[0092] Taking j=0 as an example, when j=0, among the operands read from RAM0-7, C0, C32, C64, C96, C128, C160, C192, and C224 form the first array; C16, C48, C80, C112, C144, C176, C208, and C240 ​​form the second array, as shown in Table 6 below: Table 6

[0093] Among them, the order of C0, C32, C64, C96, C128, C160, C192, and C224 in the first array g[] is 0-7 respectively, and the order of C16, C48, C80, C112, C144, C176, C208, and C240 ​​in the second array h[] is 0-7 respectively.

[0094] When u=0 g'[2*u]=g[2*u], that is, g'[0]=g[0]; g'[2*u+1]=h[2*u], that is, g'[1]=h[0]; h'[2*u]=g[2*u+1], that is, h'[0]=g[1]; h'[2*u+1]=h[2*u+1], that is, h'[1]=h[1].

[0095] When u=1 g'[2*u]=g[2*u], that is, g'[2]=g[2]; g'[2*u+1]=h[2*u], that is, g'[3]=h[2]; h'[2*u]=g[2*u+1], that is, h'[2]=g[3]; h'[2*u+1]=h[2*u+1], that is, h'[3]=h[3].

[0096] When u=2 g'[2*u]=g[2*u], that is, g'[4]=g[4]; g'[2*u+1]=h[2*u], that is, g'[5]=h[4]; h'[2*u]=g[2*u+1], that is, h'[4]=g[5]; h'[2*u+1]=h[2*u+1], that is, h'[5]=h[5].

[0097] When u=3 g'[2*u]=g[2*u], that is, g'[6]=g[6]; g'[2*u+1]=h[2*u], that is, g'[7]=h[6]; h'[2*u]=g[2*u+1], that is, h'[6]=g[7]; h'[2*u+1]=h[2*u+1], that is, h'[7]=h[7].

[0098] At this time, the reordering of the 8 pairs of operands read by r=2, j=0 is completed, as shown in Table 6. In addition, the specific meanings of the above formulas refer to the specific explanation of the examples of r=0, j=0, and are not repeated here.

[0099] As shown in Table 6 above, after completing the rearrangement of the operands read from each memory when the operation stage r=2, j=0, by analogy, the operands read from each memory when r=2, j=1 to 15 can also be rearranged respectively, which are not listed here one by one.

[0100] The above is an example of situation one, and the following is an example of situation two.

[0101] Case 2 When K=2, b=1. At this time, the range of the preset operation stage is r∈[0, b-1], that is, r=0. That is, it is only necessary to reorder the read operands according to the above formulas (5)-(8) when the operation stage r=0.

[0102] For example, the sequence length of the computing tasks to be executed is 64 and the parallelism is 2, that is, N=64, n=6, K=2, b=1. The parallelism is 2, and there are 2 memories, t∈[0,2), and the depth of each memory is 32, y∈[0,32). Refer to Table 7 below, which is a schematic table of the storage of the computing tasks to be executed D0-D63 in the memories numbered RAM0-RAM1.

[0103] Table 7

[0104] Among them, for RAM0, it stores the 0th to 31st operands, namely D0-D31, and for RAM1, it stores the 32nd to 63rd operands, namely D32-D63.

[0105] In the operation stage, when r=0, all operands are in the same group, and the addresses of operands D0-D63 in the group are 0-63 respectively. Then the two operands required for each butterfly calculation are: D0 and D32, D1 and D33, and so on to D31 and D63.

[0106] However, in parallel operation, two operands need to be read from each memory separately, and the addresses of the operands read from each memory in each parallel butterfly calculation order need to be j and j+ .

[0107] For example, referring to Table 7 above, N=64, each stage includes 32 butterfly operations, K=2, and 2 butterfly calculations can be performed each time a parallel butterfly calculation is performed, so 16 parallel butterfly calculations are required, j∈[0,15).

[0108] When j = 0, the addresses of the operands read from RAM0-1 are 0 and 16; When j=1, the addresses of the operands read from RAM0-1 are 1 and 17; Similarly, when j=15, the addresses of the operands read from RAM0-1 are 15 and 31.

[0109] Then, referring to Table 7, when j=0, D0 and D16 are read from RAM0, and D32 and D48 are read from RAM1, that is, when r=0 in the operation stage, the two operands read from each memory are not a pair of operands corresponding to each butterfly calculation. For example, D0 and D16 are read from RAM0, but actually D0 and D32 are a pair of operands required for a butterfly calculation, and D16 and D48 are a pair of operands required for a butterfly calculation. Therefore, the operands read from each memory need to be reordered to ensure correct operation.

[0110] Taking j=0 as an example, when j=0, among the operands read from RAM0-1, D0, D32, form the first array; D16, D48 form the second array, as shown in Table 8 below: Table 8

[0111] Among them, the order of D0 and D32 in the first array g[] is 0 and 1 respectively, and the order of D16 and D48 in the second array h[] is 0 and 1 respectively.

[0112] When r=0, u∈[0,1), that is, u=0.

[0113] When u=0 g'[2*u]=g[2*u], that is, g'[0]=g[0]; g'[2*u+1]=h[2*u], that is, g'[1]=h[0]; h'[2*u]=g[2*u+1], that is, h'[0]=g[1]; h'[2*u+1]=h[2*u+1], that is, h'[1]=h[1].

[0114] At this point, the reordering of the two pairs of operands read at r=0, j=0 is completed, as shown in Table 8 above.

[0115] As shown in Table 8 above, after completing the rearrangement of the operands read from each memory when the operation stage r=0, j=0, by analogy, the operands read from each memory when r=0, j=1 to 15 can also be rearranged respectively, which are not listed here one by one.

[0116] In step S400, after the operands read in each parallel butterfly calculation order in the preset operation stage are rearranged, two operand arrays (i.e., the third array and the fourth array) that can be read in the same order and can perform the same butterfly calculation can be formed.

[0117] Step S500: Combining operands of the same order in the third array and the fourth array into two operands required for a butterfly calculation.

[0118] As shown in Table 2 above, operands of the same order in the third array g'[] and the fourth array h'[] can perform the same butterfly calculation, for example, A0 and A128, A16 and A144, A32 and A160, A48 and A176, A64 and A192, A80 and A208, A96 and A224, A112 and A240.

[0119] For example, as shown in Table 4, B0 and B64, B16 and B80, B32 and B96, B48 and B112, B128 and B192, B144 and B208, B160 and B224, B176 and B240.

[0120] For example, as shown in Table 6, C0 and C32, C16 and C48, C64 and C96, C80 and C112, C128 and C160, C144 and C176, C192 and C224, C208 and C240.

[0121] For example, as shown in Table 8, D0 and D32, D16 and D48.

[0122] The data processing method in the present embodiment, when executing the computing task to be executed, no matter how much the parallelism of the computing task to be executed is, can determine the stage that needs to be rearranged based on the parallelism, that is, the preset computing stage. After determining the preset computing stage that needs to be rearranged, the operands read each time in the preset computing stage are rearranged according to the first preset rule, and then the butterfly calculation in the computing task to be executed can be performed.

[0123] In the embodiment of the present application, after the operands of the same order in the third array and the fourth array are combined into two operands required for a butterfly calculation, the data processing method further includes the following steps S600-S900: Step S600: Select operands with the same order from the third array and the fourth array to perform butterfly calculation.

[0124] In the embodiment of the present application, butterfly calculations may be performed based on A0 and A128, A16 and A144, A32 and A160, A48 and A176, A64 and A192, A80 and A208, A96 and A224, A112 and A240, respectively.

[0125] For another example, as shown in Table 4, butterfly calculations may be performed based on B0 and B64, B16 and B80, B32 and B96, B48 and B112, B128 and B192, B144 and B208, B160 and B224, and B176 and B240, respectively.

[0126] For another example, as shown in Table 6, butterfly calculations can be performed based on C0 and C32, C16 and C48, C64 and C96, C80 and C112, C128 and C160, C144 and C176, C192 and C224, and C208 and C240, respectively.

[0127] For another example, as shown in Table 8, butterfly calculations may be performed based on D0 and C32, D16 and D48, respectively.

[0128] Step S600: the calculation result with a higher order among the two calculation results obtained by each butterfly calculation is formed into a fifth array, and the calculation result with a lower order is formed into a sixth array.

[0129] Referring to Table 9 below, the fifth array s'[] and the sixth array p'[] in Table 9 are the results of butterfly calculation based on the operands in the third array g'[] and the fourth array h'[] in Table 2.

[0130] Table 9

[0131] As shown in Table 9 above, the operands in the same order of the fifth array and the sixth array are the calculation results obtained by butterfly calculation of the operands in the corresponding positions of the third array and the fourth array. For example, B0 and B128 are the results obtained by butterfly calculation based on A0 and A128.

[0132] Step S800: Rearrange the fifth array and the sixth array according to the second preset rule to obtain the seventh array and the eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

[0133] As shown in Table 2 and Table 9, B0 and B128 are the results obtained by butterfly calculation based on A0 and A128, but B0 and B128 are the calculation results obtained by reordering the obtained A0 and A16 and using the reordered A0 and A128 as two operands of a pair of butterfly calculations. B0 is the replacement result of the two butterfly calculation results (B0, B128) corresponding to A0, and B128 is the replacement result of the two butterfly calculation results (B0, B128) corresponding to A128, that is, the write-back positions corresponding to B0 and B128 are A0 and A128, not A0 and A16. Therefore, the obtained calculation results need to be rearranged according to the second preset rule before they can be written back to the corresponding storage space, wherein the second preset rule and the first preset rule are inverse to each other, that is, the data rearranged according to the second preset rule and the data rearranged according to the first preset rule are in reverse order.

[0134] In an embodiment of the present application, when the obtained calculation results are reordered according to the second preset rule, the corresponding preset operation stage is the same as the preset operation stage when rearranged according to the first preset rule, that is, at any stage as long as the read operands are reordered according to the first preset rule, then the calculation results need to be reordered according to the second preset rule after the butterfly calculation.

[0135] The second preset rule includes the following cases 3 and 4: Case 3: K>2 Case 3 corresponds to case 1 in the first preset rule, and includes two stages r∈[0, b-2] and r=b-1.

[0136] When r∈[0, b-2], calculate according to the following formulas (9), (10), (11), and (12): s'[2*m+grp* ]=s[m+grp* ] (9) s'[2*m+1+grp* ]=p[m+grp* ] (10) p'[2*m+grp* ]=s[m+ +grp* ] (11) p'[2*m+1+grp* ]=p[m+ +grp* ] (12) When r=b-1, calculate according to the following formulas (13), (14), (15), and (16): s'[2*u]=s[2*u](13) s'[2*u+1]=p[2*u](14) s'[2*u]=s[2*u+1](15) p'[2*u+1]=p[2*u+1](16) Case 4: K=2 Case 4 corresponds to Case 2 in the first preset rule and is calculated only according to formulas (13), (14), (15), and (16).

[0137] Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

[0138] Next, taking Tables 2, 4, and 6 as examples, situation three in the second preset rule is explained, and taking Table 8 as an example, situation four in the second preset rule is explained, and it is specifically explained how the calculation results after re-arrangement and butterfly calculation according to the first preset rule are sorted according to the second preset rule.

[0139] Case 3 Referring to Table 9, the fifth array s'[] and the sixth array p'[] in Table 9 are calculation results obtained by performing butterfly calculations on operands of the same order in the third array g'[] and the fourth array h'[] in Table 2, respectively.

[0140] When r=0, grp∈[0, ), m∈[0,4), that is, grp=0,m=0,1,2,3.

[0141] When m=0 s'[2*m+grp* ]=s[m+grp* ], that is, s'[0]=s[0]; s'[2*m+1+grp* ]=p[m+grp* ], that is, s'[1]=p[0]; p'[2*m+grp* ]=s[m+ +grp* ], that is, p'[0]=s[4]; p'[2*m+1+grp* =p[m+ +grp* , that is, p’[1]=p[4].

[0142] When m = 1 s’[2*m+grp* =s[m+grp* , that is, s’[2]=s[1]; s’[2*m+1+grp* =p[m+grp* , that is, s’[3]=p[1]; p’[2*m+grp* =s[m+ +grp* , that is, p’[2]=s[5]; p’[2*m+1+grp* =p[m+ +grp* , that is, p’[3]=p[5].

[0143] When m = 2 s’[2*m+grp* =s[m+grp* , that is, s’[4]=s[2]; s’[2*m+1+grp* =p[m+grp* , that is, s’[5]=p[2]; p’[2*m+grp* =s[m+ +grp* , that is, p’[4]=s[6]; p’[2*m+1+grp* =p[m+ +grp* , that is, p’[5]=p[6].

[0144] When m = 3 s’[2*m+grp* =s[m+grp* , that is, s’[6]=s[3]; s’[2*m+1+grp* =p[m+grp* , that is, s’[7]=p[3]; p’[2*m+grp* =s[m+ +grp* ], that is, p'[6]=s[7]; p'[2*m+1+grp* ]=p[m+ +grp* ], that is, p'[7]=p[7].

[0145] At this point, the reverse sorting of the butterfly calculation results when r=0, j=0 is completed, as shown in Table 9. Similarly, in each parallel butterfly calculation order of r=0, j=1-15, the butterfly calculation results can be reverse sorted according to the above method.

[0146] Referring to Table 10, Table 10 is the calculation result obtained by butterfly calculation after rearrangement in Table 4 above.

[0147] Table 10

[0148] The fifth array s'[] and the sixth array p'[] in Table 10 are the results obtained by butterfly calculation based on the third array g'[] and the fourth array h'[] in Table 4.

[0149] r=1,grp∈[0, ), m∈[0,2), that is, grp=0,1,m=0,1.

[0150] When grp=0, m=0 s'[2*m+grp* ]=s[m+grp* ], that is, s'[0]=s[0]; s'[2*m+1+grp* ]=p[m+grp* ], that is, s'[1]=p[0]; p'[2*m+grp* ]=s[m+ +grp* ], that is, p'[0]=s[2]; p'[2*m+1+grp* ]=p[m+ +grp* ], that is, p'[1]=p[2].

[0151] When grp=0, m=1 s'[2*m+grp* ]=s[m+grp* ], that is, s'[2]=s[1]; s’[2*m + 1 + grp * = p[m + grp * , that is, s’[3] = p[1]; p’[2*m + grp * = s[m + + grp * , that is, p’[2] = s[3]; p’[2*m + 1 + grp * = p[m + + grp * , that is, p’[3] = p[3].

[0152] When grp = 1 and m = 0 s’[2*m + grp * = s[m + grp * , that is, s’[4] = s[4]; s’[2*m + 1 + grp * = p[m + grp * , that is, s’[5] = p[4]; p’[2*m + grp * = s[m + + grp * , that is, p’[4] = s[6]; p’[2*m + 1 + grp * = p[m + + grp * , that is, p’[5] = p[6].

[0153] When grp = 1 and m = 1, s’[2*m + grp * = s[m + grp * , that is, s’[6] = s[5]; s’[2*m + 1 + grp * = p[m + grp * , that is, s’[7] = p[5]; p’[2*m + grp * = s[m + + grp * , that is, p’[6] = s[7]; p’[2*m + 1 + grp * = p[m + + grp * , that is, p’[7] = p[7].

[0154] At this point, the reverse sorting of the butterfly calculation results when r=1 and j=0 is completed, as shown in Table 10. Similarly, in each parallel butterfly calculation order when r=1 and j=1-15, the butterfly calculation results can be reverse sorted according to the above method.

[0155] Referring to Table 11, Table 11 is the calculation result obtained by butterfly calculation after rearrangement in Table 6 above.

[0156] Table 11

[0157] The fifth array s'[] and the sixth array p'[] in Table 11 are the results obtained by butterfly calculation based on the third array g'[] and the fourth array h'[] in Table 4.

[0158] r=2, u∈[0, 4), that is, u=0, 1, 2, 3.

[0159] When u=0 s'[2*u]=s[2*u], that is, s'[0]=s[0]; s'[2*u+1]=p[2*u], that is, s'[1]=p[0]; s'[2*u]=s[2*u+1], that is, s'[0]=s[1]; p'[2*u+1]=p[2*u+1], that is, p'[1]=p[1].

[0160] When u=1 s'[2*u]=s[2*u], that is, s'[2]=s[2]; s'[2*u+1]=p[2*u], that is, s'[3]=p[2]; s'[2*u]=s[2*u+1], that is, s'[2]=s[3]; p'[2*u+1]=p[2*u+1], that is, p'[3]=p[3].

[0161] When u=2 s'[2*u]=s[2*u], that is, s'[4]=s[4]; s'[2*u+1]=p[2*u], that is, s'[5]=p[4]; s'[2*u]=s[2*u+1], that is, s'[4]=s[5]; p'[2*u+1]=p[2*u+1], that is, p'[5]=p[5].

[0162] When u=3 s'[2*u]=s[2*u], that is, s'[6]=s[6]; s'[2*u+1]=p[2*u], that is, s'[7]=p[6]; s'[2*u]=s[2*u+1], that is, s'[6]=s[7]; p'[2*u+1]=p[2*u+1], that is, p'[7]=p[7].

[0163] At this point, the reverse sorting of the butterfly calculation results when r=2 and j=0 is completed, as shown in Table 11. Similarly, in each parallel butterfly calculation sequence of r=2 and j=1-15, the butterfly calculation results can be reverse sorted according to the above method.

[0164] Case 4 Referring to Table 12, Table 12 is the calculation result obtained by butterfly calculation after rearrangement in Table 8 above.

[0165] Table 12

[0166] The fifth array s'[] and the sixth array p'[] in Table 12 are the results obtained by butterfly calculation based on the third array g'[] and the fourth array h'[] in Table 8.

[0167] When r=0, u∈[0,1), that is, u=0.

[0168] When u=0 s'[2*u]=s[2*u], that is, s'[0]=s[0]; s'[2*u+1]=p[2*u], that is, s'[1]=p[0]; s'[2*u]=s[2*u+1], that is, s'[0]=s[1]; p'[2*u+1]=p[2*u+1], that is, p'[1]=p[1].

[0169] At this point, the reverse sorting of the butterfly calculation results when r=0, j=0 is completed, as shown in Table 12. Similarly, in each parallel butterfly calculation order of r=2, j=1-15, the butterfly calculation results can be reverse sorted according to the above method.

[0170] The above introduces the reverse sorting of butterfly calculation results in case three and case four respectively.

[0171] As shown in Table 9, each operand in the seventh array s[] in Table 9 is a replacement result of the butterfly calculation result corresponding to each operand in the first array g[] in Table 2, and each operand in the eighth array p[] in Table 9 is a replacement result of the butterfly calculation result corresponding to each operand in the second array h[] in Table 2. For example, B0, B32, B64, B96, B128, B160, B192, and B224 are the replacement results of the butterfly calculation results corresponding to A0, A32, A64, A96, A128, A160, A192, and A224 respectively. B0, B32, B64, B96, B128, B160, B192, and B224 can replace A0, A32, A64, A96, A128, A160, A192, and A224 respectively, and are written back to the storage addresses of A0, A32, A64, A96, A128, A160, A192, and A224 respectively, which can be used as operands in the next calculation stage. B16, B48, B80, A112, B144, B176, B208, and B240 are the replacement results of the butterfly calculation results corresponding to A16, A48, A80, A112, B144, A176, A208, and A240 respectively. That is, B16, B48, B80, A112, B144, B176, B208, and B240 can replace A16, A48, A80, A112, B144, A176, A208, and A240 respectively, and are written back to the storage addresses of A16, A48, A80, A112, B144, A176, A208, and A240 respectively, and can be used as operands in the next operation stage.

[0172] By analogy, each operand in the seventh array s[] in Table 10 is a replacement result of the butterfly calculation results corresponding to each operand in the first array g[] in Table 4, and each operand in the eighth array p[] in Table 10 is a replacement result of the butterfly calculation results corresponding to each operand in the second array h[] in Table 4.

[0173] The operands in the seventh array s[] in Table 11 are replacement results of the butterfly calculation results corresponding to the operands in the first array g[] in Table 6, and the operands in the eighth array p[] in Table 11 are replacement results of the butterfly calculation results corresponding to the operands in the second array h[] in Table 6.

[0174] The operands in the seventh array s[] in Table 12 are replacement results of the butterfly calculation results corresponding to the operands in the first array g[] in Table 8, and the operands in the eighth array p[] in Table 12 are replacement results of the butterfly calculation results corresponding to the operands in the second array h[] in Table 8.

[0175] The data processing method in the embodiment of the present application can determine the preset operation stage that needs to be rearranged based on the degree of parallelism when facing pending computing tasks with different degrees of parallelism. After determining the preset operation stage, the butterfly calculation can be performed after the operands read each time in the preset operation stage are rearranged according to the first preset rule. Therefore, the degree of parallelism can be easily switched without rewriting the logic circuit on the FPGA board.

[0176] Exemplary Devices like Figure 2 As shown, this exemplary embodiment provides a data processing device 100, including: The acquisition module 110 is used to determine the parallelism of the computing task to be executed; the computing task to be executed is to perform a number-theoretic transformation or an inverse number-theoretic transformation on the data to be processed, the computing task to be executed includes multiple parallel butterfly calculations, and the parallelism represents the number of butterfly calculations included in one parallel butterfly calculation; the data to be processed includes multiple operands; In a preset operation stage of the computing task to be executed, two operands are read from a preset address in each memory at a time in an order of parallel butterfly calculations based on the degree of parallelism; the preset operation stage is determined based on the degree of parallelism; the number of operands obtained by each parallel butterfly calculation is twice the degree of parallelism; The processing module 120 is used to form a first array with an operand with a front address and a second array with an operand with a back address among two operands read from each memory in each parallel butterfly calculation order; Rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array; The operands in the same order in the third array and the fourth array are obtained as two operands participating in the same butterfly calculation.

[0177] In the embodiment of the present application, the data to be processed is pre-stored in respective memories whose number is the same as the degree of parallelism according to the degree of parallelism, and the number of operands stored in each memory is the same.

[0178] In the embodiment of the present application, the depth of each memory is preconfigured as , the storage addresses in each memory are y∈[0, ); The storage addresses of the memories are sequentially stored with the first To ( -1) operands; Where N= , K , N represents the sequence length of the data to be processed, K represents the degree of parallelism, y represents the storage address of the memory, t represents the number of the memory, t∈[0,K).

[0179] In the embodiment of the present application, the processing module 120 determines the range of the preset operation stage based on the following method: r∈[0, b-1]; Among them, r represents the operation stage of the computing task to be executed, K , K represents the degree of parallelism.

[0180] In the embodiment of the present application, the first preset rule includes: When K=2, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; When K>2, When r∈[0,b-2], g'[2*m+grp* ]=g[m+grp* ], g'[2*m+1+grp* ]=h[m+grp* ], h'[2*m+grp* ]=g[m+ +grp* ], h'[2*m+1+grp* ]=h[m+ +grp* ]; When r=b-1, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array.

[0181] In the embodiment of the present application, the processing module 120 is further used for: After taking the operands of the same order in the third array and the fourth array as two operands of the same butterfly calculation, performing the butterfly calculation; The calculation result with the earlier order among the two calculation results obtained by each butterfly calculation is formed into a fifth array, and the calculation result with the later order is formed into a sixth array; The fifth array and the sixth array are rearranged according to a second preset rule to obtain a seventh array and an eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

[0182] In the embodiment of the present application, the second preset rule includes: When K=2, s'[2*u]=s[2*u], s'[2*u+1]=p[2*u], p'[2*u]=s[2*u+1], p'[2*u+1]=p[2*u+1]; When K>2, When r∈[0,b-2], s'[2*m+grp* ]=s[m+grp* ]; s'[2*m+1+grp* ]=p[m+grp* ]; p'[2*m+grp* ]=s[m+ +grp* ]; p'[2*m+1+grp* ]=p[m+ +grp* ]; When r=b-1, s'[2*u]=s[2*u]; s'[2*u+1]=p[2*u]; s'[2*u]=s[2*u+1]; p'[2*u+1]=p[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

[0183] The data processing device 100 and the processing module 120 in the embodiment of the present application can determine the preset operation stage that needs to be rearranged based on the degree of parallelism when facing the pending computing tasks with different degrees of parallelism. After determining the preset operation stage, the butterfly calculation can be performed after the operands read each time in the preset operation stage are rearranged according to the first preset rule. Therefore, the degree of parallelism can be easily switched without rewriting the logic circuit on the FPGA board.

[0184] Exemplary Media After introducing the method, medium and system of the exemplary embodiments of the present application, next, reference is made to Figure 3 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 3 , the computer-readable storage medium shown is a CD 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, it will implement the steps recorded in the above method implementation, for example, determining the parallelism of the computing task to be executed; reading two operands from the preset addresses in each memory each time in the order of parallel butterfly calculation based on the parallelism; forming a first array with an operand with a front address and a second array with an operand with a rear address among the two operands read from each memory in each parallel butterfly calculation order; rearranging the first array and the second array according to the first preset rule to obtain a third array and a fourth array; obtaining operands of the same order in the third array and the fourth array as two operands participating in the same butterfly calculation. The specific implementation method of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0185] Exemplary Chips After introducing the method, apparatus, and medium of the exemplary embodiment of the present application, next, the chip of the exemplary embodiment of the present application is introduced.

[0186] The present application proposes a chip, which includes a programmable logic circuit and / or program instructions. When the chip works on a computer device, it is used to implement the method described in any of the above embodiments, and therefore has all the beneficial effects of the data processing method described in the above embodiments, which are not described one by one here.

[0187] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0188] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A data processing method, comprising: Determine the degree of parallelism of the computational tasks to be performed; The computing task to be executed is to perform a number-theoretic transformation or an inverse number-theoretic transformation on the data to be processed, the computing task to be executed includes a plurality of parallel butterfly calculations, and the degree of parallelism indicates the number of butterfly calculations included in one parallel butterfly calculation; the data to be processed includes a plurality of operands; In a preset operation phase of the computing task to be executed, two operands are read from a preset address in each memory at a time in an order of parallel butterfly calculation based on the degree of parallelism; The preset operation stage is determined based on the parallelism; the number of operands obtained by each parallel butterfly calculation is twice the parallelism; The operands read from each memory in each parallel butterfly calculation order are composed of the operand with the earlier address into a first array and the operand with the later address into a second array; Rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array; The operands in the same order in the third array and the fourth array are obtained as two operands participating in the same butterfly calculation.

2. The data processing method according to claim 1, wherein: The data to be processed are pre-stored in respective memories whose number is the same as the parallelism degree according to the parallelism degree, and the number of operands stored in each memory is the same.

3. The data processing method according to claim 2, wherein: The depth of each memory is preconfigured to , the storage addresses in each memory are y∈[0, ); The storage addresses of the memories are sequentially stored with the first To ( -1) operands; Where N= , K , N represents the sequence length of the data to be processed, K represents the degree of parallelism, y represents the storage address of the memory, t represents the number of the memory, t∈[0,K).

4. The data processing method according to claim 1, wherein: The range of the preset operation stage is: r∈[0, b-1]; Among them, r represents the operation stage of the computing task to be executed, K , K represents the degree of parallelism.

5. The data processing method according to claim 1, wherein: The first preset rule includes: When K=2, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; When K>2, When r∈[0,b-2], g’[2*m+grp* ]=g[m+grp* ], g’[2*m+1+grp* ]=h[m+grp* ], h’[2*m+grp* ]=g[m+ +grp* ], h’[2*m+1+grp* ]=h[m+ +grp* ]; When r=b-1, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array.

6. The data processing method according to claim 1, wherein: After taking the operands of the same order in the third array and the fourth array as two operands of the same butterfly calculation and performing the butterfly calculation, the data processing method further includes: The first calculation result of the two calculation results obtained by each butterfly calculation is used to form a fifth array, and the second calculation result is used to form a sixth array; The fifth array and the sixth array are rearranged according to a second preset rule to obtain a seventh array and an eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

7. The data processing method according to claim 6, wherein: The second preset rule includes: When K=2, s'[2*u]=s[2*u], s'[2*u+1]=p[2*u], p'[2*u]=s[2*u+1], p'[2*u+1]=p[2*u+1]; When K>2, When r∈[0,b-2], s’[2*m+grp* ]=s[m+grp* ]; s’[2*m+1+grp* ]=p[m+grp* ]; p’[2*m+grp* ]=s[m+ +grp* ]; p’[2*m+1+grp* ]=p[m+ +grp* ]; When r=b-1, s'[2*u]=s[2*u]; s'[2*u+1]=p[2*u]; s'[2*u]=s[2*u+1]; p'[2*u+1]=p[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

8. A data processing device, comprising: An acquisition module is used to determine the parallelism of the computing task to be executed; The computing task to be executed is to perform a number-theoretic transformation or an inverse number-theoretic transformation on the data to be processed, the computing task to be executed includes a plurality of parallel butterfly calculations, and the degree of parallelism indicates the number of butterfly calculations included in one parallel butterfly calculation; the data to be processed includes a plurality of operands; In a preset operation phase of the computing task to be executed, two operands are read from a preset address in each memory at a time in an order of parallel butterfly calculation based on the degree of parallelism; A processing module, configured to form a first array with an operand with a front address and a second array with an operand with a back address of two operands read from each memory in each parallel butterfly calculation order; the preset operation stage is determined based on the parallelism; the number of operands obtained by each parallel butterfly calculation is twice the parallelism; Rearrange the first array and the second array respectively according to a first preset rule to obtain a third array and a fourth array; The operands in the same order in the third array and the fourth array are obtained as two operands participating in the same butterfly calculation.

9. The data processing apparatus according to claim 8, wherein: The data to be processed are pre-stored in respective memories whose number is the same as the parallelism degree according to the parallelism degree, and the number of operands stored in each memory is the same.

10. The data processing apparatus according to claim 9, wherein: The depth of each memory is preconfigured to , the storage addresses in each memory are y∈[0, ); The storage addresses of the memories are sequentially stored with the first To ( -1) operands; Where N= , K , N represents the sequence length of the data to be processed, K represents the degree of parallelism, y represents the storage address of the memory, t represents the number of the memory, t∈[0,K).

11. The data processing apparatus according to claim 8, wherein: The processing module determines the range of the preset operation stage based on the following method: r∈[0, b-1]; Among them, r represents the operation stage of the computing task to be executed, K , K represents the degree of parallelism.

12. The data processing apparatus according to claim 8, wherein: The first preset rule includes: When K=2, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; When K>2, When r∈[0,b-2], g’[2*m+grp* ]=g[m+grp* ], g’[2*m+1+grp* ]=h[m+grp* ], h’[2*m+grp* ]=g[m+ +grp* ], h’[2*m+1+grp* ]=h[m+ +grp* ]; When r=b-1, g'[2*u]=g[2*u], g'[2*u+1]=h[2*u], h'[2*u]=g[2*u+1], h'[2*u+1]=h[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), g[] represents the first array, h[] represents the second array, g'[] represents the third array, and h'[] represents the fourth array.

13. The data processing apparatus according to claim 8, wherein: The processing module is also used for: After taking the operands of the same order in the third array and the fourth array as two operands of the same butterfly calculation, performing the butterfly calculation; The first calculation result of the two calculation results obtained by each butterfly calculation is used to form a fifth array, and the second calculation result is used to form a sixth array; The fifth array and the sixth array are rearranged according to a second preset rule to obtain a seventh array and an eighth array; wherein the operands of each order in the seventh array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the first array, and the operands of each order in the eighth array are replacement results of the butterfly calculation results corresponding to the operands of the corresponding order in the second array.

14. The data processing apparatus according to claim 13, wherein: The second preset rule includes: When K=2, s'[2*u]=s[2*u], s'[2*u+1]=p[2*u], p'[2*u]=s[2*u+1], p'[2*u+1]=p[2*u+1]; When K>2, When r∈[0,b-2], s’[2*m+grp* ]=s[m+grp* ]; s’[2*m+1+grp* ]=p[m+grp* ]; p’[2*m+grp* ]=s[m+ +grp* ]; p’[2*m+1+grp* ]=p[m+ +grp* ]; When r=b-1, s'[2*u]=s[2*u]; s'[2*u+1]=p[2*u]; s'[2*u]=s[2*u+1]; p'[2*u+1]=p[2*u+1]; Where r represents the operation stage of the computing task to be executed, grp∈[0, ), represents the group order of the computing tasks to be executed in the operation stage r, m∈[0, ), u∈[0, ), s'[] represents the fifth array, p'[] represents the sixth array, s[] represents the seventh array, and p[] represents the eighth array.

15. A computer-readable storage medium comprising instructions, which, when executed on a computer, enables the computer to perform the method according to any one of claims 1 to 7.

16. A chip, comprising a programmable logic circuit and / or program instructions, and when the chip is operated on a computer device, is used to implement the method according to any one of claims 1 to 7.

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