Logic unit mapping method and device, electronic equipment and storage medium

Abstract

The invention relates to a logic unit mapping method and device, electronic equipment and a computer readable storage medium, and belongs to the field of integrated circuits. The logic unit mapping method comprises the following steps: acquiring a target logic unit needing engineering change in a target object; obtaining all standby units which can be mapped by the target logic unit in the target object to obtain a standby unit set; a repairable index after simulation mapping of the target logic unit and each standby unit in the standby unit set is obtained, and the repairable index represents the difficulty degree of violation caused after mapping of the target logic unit and the standby unit is repaired; according to all repairable indexes, selecting a standby unit with the maximum repairable index value from the standby unit set; and performing mapping replacement on the target logic unit and the standby unit with the maximum repairable index value. According to the invention, the ECO time sequence convergence speed can be accelerated, and the success rate of ECO is increased.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuits, and specifically relates to a logic unit mapping method, device, electronic device and computer-readable storage medium. Background Art

[0002] After the physical design of the chip is tape-out, the logic function may need to be changed due to design defects, so an engineering change order (ECO) is required. In order to reduce mask costs and manufacturing time, the ECO of the metal layer can be changed. This change requires finding a spare cell (spare cell) for mapping and replacing the added logic cell (ECO cell). Mapping ECO cells to different spare cells will produce different timing results. If a violation occurs in the timing path related to the mapped ECO cell, and no suitable spare cell that can be mapped to a cache cell can be found on the physical shortest path to repair the violation, then if a spare cell that can be mapped to a cache cell is found farther away for mapping, it will increase the difficulty of repair; if a spare cell that can be mapped to a cache cell cannot be found farther away, this ECO will fail. Therefore, when mapping ECO cells, the mapping strategy of spare cells is very important. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a logic unit mapping method, device, electronic device and storage medium to reduce the difficulty of repairing violations caused by ECO cell mapping, accelerate the ECO timing convergence speed, and increase the success rate of ECO.

[0004] The embodiment of the present application is implemented as follows:

[0005] In a first aspect, an embodiment of the present application provides a logic unit mapping method, comprising: obtaining a target logic unit in a target object that requires an engineering change; obtaining all spare units in the target object that can be mapped to the target logic unit to obtain a spare unit set; obtaining a repairability index after simulated mapping of the target logic unit with each spare unit in the spare unit set, wherein the repairability index represents the difficulty of repairing a violation caused by mapping the target logic unit with the spare unit; selecting a spare unit with the largest repairability index value from the spare unit set based on all repairability indicators; and mapping and replacing the target logic unit with the spare unit with the largest repairability index value.

[0006] In the above embodiment, before the ECO cell mapping decision is made, the repairability of the timing path after the ECO cell mapping is considered in advance, and by introducing a repairability index, the repairability index of the target logic unit and each spare unit in the spare unit set after simulation mapping is obtained, and then the best mapped spare unit is selected according to the repairability index to complete the mapping replacement with the ECO cell. This can reduce the difficulty of repairing violations caused by ECO cell mapping, accelerate the ECO timing convergence speed, and increase the success rate of ECO.

[0007] In combination with a possible implementation manner of the embodiment of the first aspect, obtaining all spare units in the target object that can be mapped to the target logical unit includes: obtaining a target unit in the target object that has a connection relationship with the target logical unit; obtaining a first rectangular area in the target object that includes all target units that have a connection relationship with the target logical unit; and obtaining all spare units that can be mapped to the target logical unit from the first rectangular area.

[0008] In the above embodiment, the target units in the target object that are connected to the target logical unit are obtained to determine the first rectangular area containing all the target units, and then all the spare units that can be mapped to the target logical unit are obtained only from the first rectangular area, which is conducive to shortening the Manhattan distance between the mapped spare units and the target units, thereby shortening the timing path length.

[0009] In combination with a possible implementation manner of the embodiment of the first aspect, obtaining a repairability index after simulated mapping between the target logical unit and each spare unit in the spare unit set includes: traversing each spare unit in the spare unit set to obtain a repairability index of each target unit that has a connection relationship with the target logical unit; and obtaining a repairability index after simulated mapping between each spare unit and the target logical unit according to the repairability index of each target unit that has a connection relationship with the target logical unit.

[0010] In the above embodiment, when obtaining the repairability index after simulated mapping between the target logical unit and each spare unit in the spare unit set, the repairability index of the spare unit and each target unit is obtained by traversing each spare unit in the spare unit set, so as to quickly obtain the repairability index after simulated mapping between the spare unit and the target logical unit, for example, the sum of the repairability indexes of the spare unit and each target unit.

[0011] In combination with a possible implementation manner of the embodiment of the first aspect, obtaining the repairability index of each target unit that has a connection relationship with the target logic unit includes: obtaining the number of target spare units in each second rectangular area corresponding to each spare unit, wherein the number of target spare units represents the repairability index; one of the second rectangular areas is a rectangular area including a spare unit and a target unit that has a connection relationship with the target logic unit, and the target spare unit is a spare unit that can be mapped into a buffer unit or an inverter unit.

[0012] In the above embodiment, by obtaining the number of target spare cells (which are spare cells that can be mapped into buffer cells or inverter cells) in each second rectangular area corresponding to each spare cell, the corresponding repairability index can be quickly obtained. Since the subsequent repair work on the timing violations caused by ECO will be based on the target spare cells, the repair will be performed. Therefore, the corresponding repairability index can be characterized by obtaining the number of target spare cells, thereby providing an objective method for quantifying the repairability index.

[0013] In combination with a possible implementation method of the first aspect, the number of target spare units in each second rectangular area corresponding to each spare unit is obtained, including: traversing each second rectangular area corresponding to each spare unit, and obtaining the number of target spare units in each second rectangular area; selecting the minimum value between the number of target spare units in each second rectangular area and the upper limit threshold as the number of target spare units in each second rectangular area.

[0014] In the above embodiment, when the repairability index is characterized based on the number of target spare units, an upper limit value for the quantification of the repairability index is specified. If the number of target spare units in a second rectangular area is M, after exceeding the upper limit threshold, the number of target spare units in the second rectangular area is the upper limit threshold, otherwise, it is the actual number M. The purpose of this is to avoid interference with the judgment of the final overall index due to the excessive number of target spare units in a second rectangular area.

[0015] In combination with a possible implementation method of the first aspect, if there is a target spare unit located at the boundary of the second rectangular area, the number of target spare units in each second rectangular area corresponding to each spare unit is obtained, including: traversing each second rectangular area corresponding to each spare unit, and obtaining the first number of target spare units located in each second rectangular area; obtaining the second number of boundary target spare units located at the boundary of each second rectangular area; and obtaining the number of target spare units in each second rectangular area based on the first number and the second number.

[0016] In the above embodiment, if there are target spare units located at the boundary of the second rectangular area, when obtaining the number of target spare units in the second rectangular area, the number of target spare units in the second rectangular area is obtained by obtaining the first number of target spare units located in the second rectangular area and obtaining the second number of boundary target spare units located at the boundary of each second rectangular area, thereby obtaining the number of target spare units in the second rectangular area, for example, the sum of the first number and the second number, thereby providing an objective and scientific method for obtaining the number of target spare units in the second rectangular area.

[0017] In combination with a possible implementation method of the first aspect, obtaining the second number of boundary target spare units located at the boundary of each second rectangular area includes: for each boundary target spare unit, calculating the area ratio of the area of ​​each boundary target spare unit located within the boundary of the second rectangular area to the area of ​​the entire boundary target spare unit; according to the area ratio of each boundary target spare unit, obtaining the second number of boundary target spare units located at the boundary of each second rectangular area.

[0018] In the above embodiment, when calculating the second number of boundary target backup units located at the boundary of each second rectangular area, the area allocation method is used to calculate the area ratio of the target backup units falling within the area boundary, and this is used to calculate the second number of boundary target backup units, which can reduce the interference caused by the subsequent judgment of the overall indicator.

[0019] In combination with a possible implementation method of the first aspect, based on all repairability indicators, a spare unit with the largest repairability indicator value is selected from the spare unit set, including: sorting all repairability indicators to obtain a sorting result; based on the sorting result, selecting the spare unit with the largest repairability indicator value from the spare unit set.

[0020] In the above embodiment, by sorting all the repairability indices, the spare unit with the largest repairability index value can be quickly selected from the spare unit set according to the sorting result, which is conducive to improving the efficiency of selecting the best mapping spare unit.

[0021] In a second aspect, an embodiment of the present application further provides a logical unit mapping device, comprising: an acquisition module, a selection module and a mapping module; the acquisition module is used to acquire a target logical unit in a target object that requires an engineering change; acquire all spare units in the target object that can be mapped to the target logical unit to obtain a spare unit set; acquire a repairability index after simulated mapping between the target logical unit and each spare unit in the spare unit set, wherein the repairability index represents the difficulty of repairing a violation caused by mapping the target logical unit with the spare unit; the selection module is used to select a spare unit with the largest repairability index value from the spare unit set based on all repairability indicators; the mapping module is used to map and replace the target logical unit with the spare unit with the largest repairability index value.

[0022] In a third aspect, an embodiment of the present application further provides an electronic device, comprising: a memory and a processor, the processor being connected to the memory; the memory being used to store programs; the processor being used to call the programs stored in the memory to execute a method provided in the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment.

[0023] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method provided by the above-mentioned first aspect embodiment and / or any possible implementation method in combination with the first aspect embodiment is executed.

[0024] Other features and advantages of the present application will be described in the following description. The purpose and other advantages of the present application can be realized and obtained through the structures specifically pointed out in the written description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. The above and other purposes, features and advantages of the present application will be more clearly shown in the drawings.

[0026] Figure 1 A flow chart of a logic unit mapping method provided in an embodiment of the present application is shown.

[0027] Figure 2 A schematic diagram showing a principle of obtaining repairability indicators of C1 and C2 provided in an embodiment of the present application is shown.

[0028] Figure 3 A schematic diagram showing another principle of obtaining a repairability index provided in an embodiment of the present application is shown.

[0029] Figure 4 A schematic diagram showing the principle of a logic unit mapping method provided in an embodiment of the present application is shown.

[0030] Figure 5 A schematic diagram showing a principle of obtaining all spare units from a physical design module provided in an embodiment of the present application.

[0031] Figure 6 Shows Figure 5 Schematic diagram of the principle after the X1 and S6 mappings are replaced.

[0032] Figure 7 Shows the calculation Figure 6 Schematic diagram of the principle of repairability indicators of X1 and A, B, and C.

[0033] Figure 8 Shows Figure 5 Schematic diagram of the physical design timing repairability after the X1 and S7 mappings are replaced.

[0034] Fig. 9 Shows Figure 5 Schematic diagram of the physical design timing repairability after the X1 and S6 mappings are replaced.

[0035] Fig.10 A module schematic diagram of a logic unit mapping device provided in an embodiment of the present application is shown.

[0036] Fig.11 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The following embodiments can be used as examples to more clearly illustrate the technical solutions of the present application, and cannot be used to limit the scope of protection of the present application. It will be appreciated by those skilled in the art that, in the absence of conflict, the features in the following embodiments and embodiments can be combined with each other.

[0038] It should be noted that similar numbers and letters represent similar items in the following figures, so once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. At the same time, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0039] Furthermore, the term "and / or" in this application is merely a term used to describe the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0040] In the description of the embodiments of the present application, unless otherwise clearly specified or limited, the technical term "connection" may refer to a direct connection or an indirect connection through an intermediate medium.

[0041] In modern integrated circuit design, bugs are hard to avoid, especially in the design of digital logic. In order to prevent new problems from being discovered during testing after the chip is produced, many spare cells are usually placed in the entire digital logic area. During the later revision of the chip, the chip function can be changed or repaired by simply changing the ECO of the metal layer.

[0042] The purpose of ECO in chip design is very clear, which is to fix the bugs in the chip, and the lower the cost, the better. ECO can occur after tape-out, and the ECO at this time is called the Post-mask ECO stage (the transistors of the chip have been processed, but the engineering modifications during the transistor wiring have not been made). In this stage, since the position and direction of all spare units cannot be changed, the design function can only be modified by modifying the digital netlist or the corresponding EDA (Electronic Design Automation) tool commands based on the existing spare units, which will cause timing violations. It is necessary to perform relevant repair work on the timing violations caused by ECO until the signoff requirements are met. Among them, signoff is a very important stage in chip design, which is used to ensure that the chip can meet all the requirements in the specification, such as the performance, reliability and manufacturability of the chip meet the design specifications and requirements, so that it can be smoothly produced and delivered.

[0043] In order to reduce the difficulty of repairing violations caused by ECO cell mapping, accelerate the ECO timing convergence speed, and increase the success rate of ECO, the embodiment of the present application provides a logic unit mapping method in chip design. Figure 1 The logical unit mapping method provided in the embodiment of the present application is described.

[0044] Step S110: Acquire the target logical unit in the target object that needs to undergo engineering change.

[0045] When there is a need for engineering design change, the target logic unit (ECO cell) that needs to be changed in the target object is obtained, and the target unit in the target object that has a connection relationship with the target logic unit can also be obtained. The number of target logic units can be multiple, and since the principle of mapping each target logic unit is the same, the embodiment of the present application only describes the mapping process of one target logic unit.

[0046] The target object may be a physical design module in the chip or the entire chip. It is understandable that a chip may involve many physical design modules, and during design, each physical design module may be designed in parallel to speed up the design process.

[0047] In one implementation, the target logic unit that needs to undergo engineering changes in the target object may be obtained based on the design change file of the target object; wherein the design change file records the content that needs to be changed in this design, which may include adding a cell, adding a net (wire), connecting a pin to a net, and disconnecting a pin from a net. For example, after adding a cell, a new net needs to be connected to other cells in the target object, and when connecting, a pin of other cells needs to be connected to a net, and a pin may need to be disconnected from a net).

[0048] The above-mentioned design change file can be a netlist of the target object after the design change or a script recording the design change, and the script contains the content of the design change. The target object and the design change file of the target object can be read by EDA tools to obtain the target logic unit that needs to be engineered in the target object.

[0049] S120: Acquire all spare units in the target object that can be mapped to the target logical unit to obtain a spare unit set.

[0050] After obtaining the target logic unit that needs engineering change, all spare units in the target object that can be mapped to the target logic unit are obtained. These spare units may be pre-embedded single logic units or variable logic units (which can be changed into multiple logics).

[0051] In a possible implementation, all spare units in the target object that can be mapped to the target logical unit may be obtained.

[0052] In another possible implementation, all spare units that can be mapped to the target logical unit in a specified area of ​​the target object may be obtained.

[0053] When acquiring all spare units that can be mapped to the target logical unit in a specified area of ​​the target object, in a possible implementation, the acquisition process of S120 may include: acquiring the target unit that has a connection relationship with the target logical unit in the target object; acquiring a first rectangular area in the target object that includes all target units that have a connection relationship with the target logical unit; and acquiring all spare units that can be mapped to the target logical unit from the first rectangular area. In this implementation, the target unit that has a connection relationship with the target logical unit in the target object is first acquired, and then the first rectangular area that includes all target units is determined according to the location of the target unit, and then all spare units that can be mapped to the target logical unit can be acquired from the first rectangular area.

[0054] Among them, when obtaining the target unit in the target object that has a connection relationship with the target logic unit, it can be obtained according to the above-mentioned design change file. After adding an ECO cell, the ECO cell needs to be connected with other units in the target object, otherwise it is meaningless. The target unit is the unit in the target object that has a connection relationship with the target logic unit.

[0055] The first rectangular area may be a minimum rectangular area that includes all target cells that are connected to the target logic cell. In some possible implementations, the first rectangular area may not be a minimum rectangular area. Selecting a spare cell in the minimum rectangular area that can be mapped to the target logic cell is conducive to shortening the Manhattan distance between the mapped spare cell and the target cell, thereby shortening the timing path length.

[0056] S130: Obtain a repairability index after simulation mapping between the target logical unit and each spare unit in the spare unit set.

[0057] After obtaining the spare cell set, obtain the repairability index after the simulation mapping between the target logic cell and each spare cell in the spare cell set. Among them, the repairability index represents the difficulty of repairing the violation caused by the mapping between the target logic cell and the spare cell. The violation caused by the mapping between the target logic cell and the spare cell includes but is not limited to timing violation. In addition, it may also include design violation, such as DRV (Design Rule Violation, DRV) violation, which means that in the integrated circuit design, some design parameters violate the design rules. These violations may need to be repaired with a buffer.

[0058] In order to reduce the difficulty of repairing violations caused by ECO cell mapping, accelerate the ECO timing convergence speed, and increase the success rate of ECO. This application no longer selects a spare cell in a relatively central position to map with the target logic cell for mapping replacement, but before the ECO cell mapping decision, by introducing a repairability index, considers the repairability of the timing path after ECO cell mapping in advance, obtains the repairability index of each spare cell in the target logic cell and spare cell set after simulation mapping, and then selects the best mapped spare cell according to the repairability index.

[0059] In one implementation, the process of obtaining the repairability index of the target logical unit and each spare unit in the spare unit set after simulation mapping includes: traversing each spare unit in the spare unit set, obtaining the repairability index of each target unit that has a connection relationship with the target logical unit, and obtaining the repairability index of each spare unit after simulation mapping with the target logical unit based on the repairability index of each target unit that has a connection relationship with the target logical unit. That is, for each spare unit in the spare unit set, obtain the repairability index of each target unit that has a connection relationship with the spare unit and the target logical unit, and obtain the repairability index of the spare unit after simulation mapping with the target logical unit based on the repairability index of each target unit that has a connection relationship with the spare unit and the target logical unit. For example, the repairability index of the spare unit after simulation mapping with the target logical unit is the sum of the repairability indexes of the spare unit and each target unit.

[0060] In a possible implementation, the process of obtaining the repairability index of each target unit that has a connection relationship between each spare unit and the target logical unit may include: obtaining the number of target spare units in each second rectangular area corresponding to each spare unit, wherein the number of target spare units represents the repairability index. That is, for each spare unit, the number of target spare units in each second rectangular area corresponding to the spare unit is obtained.

[0061] A second rectangular area is a rectangular area including a spare unit and a target unit. For example, assuming that the number of target units connected to the target logical unit is N (N is an integer greater than or equal to 1), there are N second rectangular areas, and one target unit corresponds to one second rectangular area.

[0062] In one possible implementation, the second rectangular area may be a minimum rectangular area including a spare unit and a target unit. Only counting the number of target spare units in the minimum rectangular area is conducive to shortening the Manhattan distance between the target spare unit and the target unit, thereby shortening the timing path length and improving the repairability of the timing.

[0063] The target spare cell is a spare cell that can be mapped to a buffer cell or an inverter cell. Some spare cells in the target object can be mapped to a target logic cell, but cannot be mapped to a buffer cell or an inverter cell; some can be mapped to a buffer cell or an inverter cell, but cannot be mapped to a target logic cell; and some can be mapped to both a target logic cell and a buffer cell or an inverter cell. For example, if the spare cell is a variable logic cell, it can be mapped to multiple types of logic cells.

[0064] In one possible implementation, the process of obtaining the repairability index after the simulated mapping between the target logical unit and each spare unit in the spare unit set includes: obtaining the repairability index after the simulated mapping between the target logical unit and each spare unit according to the number of target spare units corresponding to each spare unit. In this embodiment, the number of target spare units corresponding to each spare unit can be used to characterize the repairability index after the simulated mapping between the target logical unit and each spare unit, that is, the value of the target spare unit is equal to the value of the repairability index. The larger the value of the target spare unit, the better the repairability. The number of target spare units corresponding to each spare unit is determined according to the number of target spare units in each second rectangular area corresponding to each spare unit. For example, the number of target spare units corresponding to each spare unit can be the sum of the number of target spare units in each second rectangular area.

[0065] In another embodiment, the process of obtaining the repairability index after simulated mapping between the target logical unit and each spare unit in the spare unit set includes: traversing each spare unit in the spare unit set, obtaining the number of target spare units in each second rectangular area corresponding to each spare unit, obtaining the number of target spare units corresponding to each spare unit according to the number of target spare units in each second rectangular area corresponding to each spare unit, and obtaining the repairability index after simulated mapping between the target logical unit and each spare unit according to the number of target spare units corresponding to each spare unit.

[0066] The number of target spare units corresponding to each spare unit may be the sum of the number of target spare units in each second rectangular area corresponding to each spare unit. For example, assuming that there are 3 second rectangular areas corresponding to a spare unit, the number of target spare units corresponding to the spare unit is the sum of the number of target spare units in the 3 second rectangular areas.

[0067] In one implementation, the process of obtaining the number of target spare units in each second rectangular area corresponding to each spare unit includes: traversing each second rectangular area corresponding to each spare unit, obtaining the number of target spare units in each second rectangular area; selecting the minimum value between the number of target spare units in each second rectangular area and the upper limit threshold as the number of target spare units in each second rectangular area. The upper limit threshold may be the value of the target spare units that can meet the ECO repair requirements. After the number of target spare units exceeds the upper limit threshold, the effect on the ECO repair effect is small or has no effect. When setting the upper limit threshold, different second rectangular areas may correspond to different upper limit thresholds, or multiple second rectangular areas may correspond to the same upper limit threshold.

[0068] In this implementation, an upper threshold value max is set. If the number of target spare units in a second rectangular area is M and exceeds the upper threshold value, then the number of target spare units in the second rectangular area is the upper threshold value. Otherwise, it is the actual number M. The purpose of this is to avoid interference with the final overall indicator judgment due to the excessive number of target spare units in a second rectangular area. For example, the three second rectangular areas corresponding to the spare units are box1, box2, and box3. Assuming that the number of target spare units in box1 is M1, and the number of target spare units in box2 and box3 is 0, since M1 is too large, the number of target spare units M1 corresponding to the spare unit is also too large, thereby interfering with the final overall indicator judgment. By introducing the upper threshold value max, the maximum number of target spare units in box1 is max, so this problem can be solved.

[0069] In a possible implementation, the process of obtaining the number of target spare units in each second rectangular area corresponding to each spare unit includes: traversing each second rectangular area corresponding to each spare unit, obtaining the first number of target spare units located in each second rectangular area, and obtaining the number of target spare units in each second rectangular area according to the first number. In this embodiment, only the first number of target spare units located in each second rectangular area may be considered.

[0070] In one possible implementation, the process of obtaining the number of target spare units in each second rectangular area corresponding to each spare unit includes: traversing each second rectangular area corresponding to each spare unit, obtaining the first number of target spare units located in each second rectangular area, and obtaining the second number of boundary target spare units located at the boundary of each second rectangular area; according to the first number and the second number, obtaining the number of target spare units in each second rectangular area. For example, the number of target spare units in each second rectangular area = the first number + the second number. In this embodiment, in addition to considering the first number of target spare units located in each second rectangular area, the second number of boundary target spare units located at the boundary of each second rectangular area is also considered.

[0071] In a possible implementation, when obtaining the second number of boundary target spare units located at the boundary of each second rectangular area, the area allocation method may be used to obtain the second number of boundary target spare units, and the process may include: for each boundary target spare unit, calculating the area ratio of the area of ​​each boundary target spare unit located within the boundary of the second rectangular area to the area of ​​the entire boundary target spare unit; according to the area ratio of each boundary target spare unit, obtaining the second number of boundary target spare units located at the boundary of each second rectangular area. In this implementation, the second number may not be an integer.

[0072] Among them, the process of obtaining the second number of boundary target spare units located at the boundary of each second rectangular area is the same. Assuming that the number of boundary target spare units located at the boundary of a second rectangular area is 3, it is necessary to obtain the area ratio of each boundary target spare unit separately, and then add the area ratios of the 3 boundary target spare units to obtain the second number of boundary target spare units located at the boundary of the second rectangular area.

[0073] It can be understood that the above-mentioned area allocation method is only an example of a method for obtaining the second number of boundary target spare units located at the boundary of each second rectangular area in the present application, and can also be expanded into other calculation methods, such as counting a boundary target spare unit located at the boundary of the second rectangular area as 0.5 (which can be considered as a special case of an area ratio of 0.5), or directly recording it as 1.

[0074] For better explanation, the above process of obtaining the number of target spare units in each second rectangular area corresponding to each spare unit is the process of obtaining the repairability index P of each spare unit and each target unit.

[0075] Combine the following Figure 2 and Figure 3The principle of obtaining the repairability index of C1 and C2 is explained. Since the process of obtaining the number of target spare cells in each second rectangular area is the same, the following is only to explain how to obtain the number of target spare cells in one second rectangular area. Assume that the second rectangular area box determined by the spare cell C1 and the target cell C2 is as follows Figure 2 As shown, the number of spare cells M in the box that can be mapped into buffer cells or inverter cells can be used to characterize the repairability index value of the connection relationship between C1 and C2, which is recorded as PC1_C2 = M. Assume Figure 2 As shown, S1, S2, and S3 are all spare cells that can be mapped to buffers or inverters, so PC1_C2 = 3. In one implementation, an upper threshold max can also be set. In this case, PC1_C2 = MIN(max, M). When the number of spare cells in the box exceeds the max value, that is, M>max, the max value is taken as PC1_C2, otherwise M is taken as PC1_C2.

[0076] If there is a spare cell (assuming it is S1) falling on the border of the box, the area allocation method can be used to determine the number of spare cells. The number of spare cells in the current box is recorded as: the area of ​​spare cells falling in this box divided by the total area of ​​spare cells. Figure 3 As shown, the black area is the area of ​​S1 falling in the box, recorded as Ss1', and the dark gray area is the total area Ss1 of S1, so the number of spare cells is recorded as Ss1' / Ss1. At this time, PC1_C2 = M + Ss1' / Ss1.

[0077] S140: According to all the repairability indices, a spare unit with the largest repairability index value is selected from the spare unit set.

[0078] After obtaining the repairability index of each spare unit in the target logic unit and the spare unit set after simulation mapping, the spare unit with the largest repairability index value is selected from the spare unit set according to all the repairability indexes. This spare unit is the best mapped spare unit.

[0079] In one possible implementation, when selecting a spare unit with the largest repairability index value from a spare unit set based on all repairability indexes, two repairability indexes can be randomly selected for comparison, and the repairability index with the larger value is retained, and then compared with the remaining repairability indexes until the repairability index with the largest value is screened out, and then the spare unit with the largest repairability index value is selected from the spare unit set.

[0080] In another possible implementation, when selecting the standby unit with the largest repairability index value from the standby unit set based on all the repairability indexes, all the repairability indexes may be sorted to obtain a sorting result; and based on the sorting result, the standby unit with the largest repairability index value may be selected from the standby unit set. For example, the standby unit may be sorted in descending order of values, and then the standby unit corresponding to the first repairability index in the sorting result is selected, which is the best mapped standby unit.

[0081] S150: Map and replace the target logical unit with the spare unit having the largest repairability index value.

[0082] After obtaining the best mapped spare unit (the spare unit with the largest repairability index value), the target logical unit is mapped and replaced with the spare unit with the largest repairability index value.

[0083] After that, it is necessary to perform relevant repair work on the violations caused by ECO mapping until the signoff requirements are met. When repairing, the target spare cell corresponding to the spare cell with the largest repairability index value in the target object (a spare cell that can be mapped to a buffer cell or an inverter cell) can be used to repair the violation. The specific repair process is a prior art and will not be described here.

[0084] In a possible implementation manner, the principle of the above logic unit mapping method can be as follows: Figure 4 After reading the design change file (which can be a netlist or script), the logic unit ECO cell list L1 = {X1, X2, ..., Xn} can be obtained. Then, all spare cells that can be mapped to the ECO cells in the list L1 are obtained one by one, and a list of all ECO cells and spare cells that can be mapped is obtained. Then, for each ECO cell in the ECO cell list, the spare cell list is traversed to obtain the repairable index P corresponding to each spare cell. Then, the spare cell with the largest P value is selected to complete the mapping replacement with the ECO cell. Finally, the relevant repair work is performed on the violations caused by the ECO until the signoff requirements are met.

[0085] In order to better illustrate the above logic unit mapping method, an example is provided below for illustration. Figure 5The block in the figure is a physical design module, or it can be the physical design of an entire chip. X1 is the ECO cell to be mapped. A, B, and C are the target cells connected to X1. region-ABC is the smallest rectangular area containing A, B, and C, that is, an area framed by the outer boundaries of A, B, and C (the lower edge of A, the right edge of B, the upper edge of B, and the left edge of C). Figure 5 Among them, {S1, S2, S3, ..., S12} are spare cells in the block that can be functionally mapped with X1, and {S4, S5, S6, ..., S11} in region-ABC is a list of spare cells to be selected that can be mapped with X1. Figure 5 In the figure, {S13, S14, S15, S16} are spare cells that can be mapped to buffers, but cannot be mapped to X1. It should be noted that in actual physical design, {S1, S2, .., S12} may be mapped to both X1 and buffers; may only be mapped to X1 but not to buffers; or may only be mapped to buffers but not to X1.

[0086] In the process of selecting and mapping spare cells, the present application considers the subsequent repairability of violations and uses corresponding indicators to characterize them. The spare cells that can be mapped to X1 are {S4, S5, S6, ..., S11}. Since the process of obtaining the repairability index of X1 after simulation mapping with each spare cell in the spare cell set is the same, the following is an explanation of the simulation mapping between X1 and S6 in the set to obtain the repairability index of S6, as shown in Figure 6 As shown in the figure, after X1 is simulated and mapped to S6, X1 has replaced the position of S6. Then, the repairability index corresponding to S6 (i.e., X1) is obtained, which can be obtained by respectively obtaining the number of target spare cells that can be mapped to buffer cells or inverter cells in box-C containing S6 and C, box-A containing S6 and A, and box-B containing S6 and B. After X1 is mapped to S6, the rectangular area box-A, box-B, box-C surrounded by A, B, and C is obtained, as shown in the schematic diagram. Figure 7 As shown, then, according to the calculation method of S130, under the mapping relationship between X1 and S6, the repairability index of ECO cell and A is PX1_S6_A, and the repairability index of ECO cell and B and C is PX1_S6_B and PX1_S6_C. Then, the repairability index of the mapping relationship between X1 and S6 is calculated as PX1_S6_A+PX1_S6_B+PX1_S6_C, which is recorded as PX1_S6.

[0087] In this way, the repairability index PX1_S6 of the single mapping relationship between X1 and S6 is obtained. In the same way, the repairability index of X1 and all optional mapping spare cells {S4, S5, ..., S11} is calculated, which is recorded as {PX1_S4, PX1_S5, ..., PX1_S11}. In the same way, the repairability index of the mapping relationship between all ECO cells and their corresponding spare cells in the list L1 = {X1, X2, ..., Xn} can be obtained. After that, for each ECO cell, the spare cell corresponding to the mapping relationship with the highest P value is selected to complete the mapping replacement of the ECO cell. For example, in {PX1_S4, PX1_S5, ..., PX1_S11}, the PX1_S6 value is the largest, so S6 is selected to complete the mapping with X1. In the same way, for {X1, X2, ..., Xn}, the spare cell with the largest repairability index value is found to complete the mapping.

[0088] The following example illustrates the adverse effects of not considering the repairability of subsequent violations. Figure 5 S7 in is mapped and replaced with X1, assuming Figure 8 A violation occurs in the timing path related to X1 and C, and it is necessary to use a buffer to repair it on the shortest physical path between X1 and C (that is, within the range of box-C), where box-C is the smallest rectangular area containing C and X1, that is, the outer boundaries of cells C and X1 (the left edge of C, the upper edge of C, the right edge of X1, and the lower edge of X1) form a box-C, but there is no spare cell in box-C that can be mapped to a buffer, then it is necessary to use a farther spare cell, such as S15, so that the Manhattan distance from C to S15 plus the Manhattan distance from X1 to S15 is greater than the Manhattan distance from C to X1. Compared with the case where a spare cell that can be mapped to a buffer is found in box-C, taking S15 increases the length of the timing path, thereby increasing the delay and reducing the repairability of the timing.

[0089] After considering the repairability of the timing path after ECO cell mapping, X1 and S7 mapping will not be selected. If X1 and S6 mapping are selected, and it is also assumed that the timing path related to X1 and C is violated after mapping, the schematic diagram is as follows: Fig. 9As shown, there is S16 in box-C that can be used to map into a buffer, which can be used to repair timing violations, so that the timing repairability of the X1 and C paths is improved. This application starts from the perspective of the repairability of the timing path after mapping. Before the mapping decision is made, the repairability indicators of the ECO cell and different spare cells after simulation mapping are obtained, and then the spare cell that is most conducive to subsequent timing repair is taken out for mapping.

[0090] The present application embodiment also provides a logic unit mapping device 100, such as Fig.10 As shown, the logic unit mapping device 100 includes: an acquisition module 110 , a selection module 120 and a mapping module 130 .

[0091] The acquisition module 110 is used to acquire a target logic unit in a target object that needs an engineering change; acquire all spare units in the target object that can be mapped to the target logic unit to obtain a spare unit set; and acquire a repairability index after simulated mapping between the target logic unit and each spare unit in the spare unit set, wherein the repairability index represents the difficulty of repairing a violation caused by mapping the target logic unit to the spare unit.

[0092] The selection module 120 is used to select a spare unit with the largest repairability index value from the spare unit set according to all the repairability indexes.

[0093] The mapping module 130 is used to map and replace the target logical unit with the spare unit with the largest repairability index value.

[0094] Optionally, the acquisition module 110 is used to acquire the target unit in the target object that is connected to the target logical unit; acquire a first rectangular area in the target object that includes all target units that are connected to the target logical unit; and acquire all spare units that can be mapped to the target logical unit from the first rectangular area.

[0095] Optionally, the acquisition module 110 is used to traverse each spare unit in the spare unit set, and obtain the repairability index of each target unit that has a connection relationship with the target logical unit; based on the repairability index of each target unit that has a connection relationship with the target logical unit, obtain the repairability index of each spare unit after simulated mapping with the target logical unit.

[0096] Optionally, the acquisition module 110 is used to obtain the number of target spare units in each second rectangular area corresponding to each spare unit, wherein the number of target spare units represents a repairability index; a second rectangular area is a rectangular area including a spare unit and a target unit that is connected to the target logic unit, and the target spare unit is a spare unit that can be mapped into a buffer unit or an inverter unit.

[0097] Optionally, the acquisition module 110 is used to traverse each second rectangular area corresponding to each backup unit to obtain the number of target backup units in each second rectangular area; and select the minimum value between the number of target backup units in each second rectangular area and the upper limit threshold as the number of target backup units in each second rectangular area.

[0098] Optionally, the acquisition module 110 is used to traverse each second rectangular area corresponding to each backup unit, obtain the first number of target backup units located in each second rectangular area; obtain the second number of boundary target backup units located at the boundary of each second rectangular area; and obtain the number of target backup units in each second rectangular area based on the first number and the second number.

[0099] Optionally, the acquisition module 110 is used to calculate, for each boundary target spare unit, the area ratio of each boundary target spare unit located within the boundary of the second rectangular area to the area of ​​the entire boundary target spare unit; based on the area ratio of each boundary target spare unit, obtain the second number of boundary target spare units located at the boundary of each second rectangular area.

[0100] Optionally, the selection module 120 is used to sort all the repairability indicators to obtain a sorting result; and select a spare unit with the largest repairability indicator value from the spare unit set according to the sorting result.

[0101] In some implementations, the various modules shown above may be partially or completely integrated together to form an independent part, or a module may be functionally split to form more modules.

[0102] The implementation principle and technical effects of the logical unit mapping device 100 provided in the embodiment of the present application are the same as those of the aforementioned method embodiment. For the sake of brief description, for matters not mentioned in the device embodiment, reference may be made to the corresponding contents in the aforementioned method embodiment.

[0103] like Fig.11 As shown, Fig.11The electronic device 200 provided in the embodiment of the present application is shown in the structural block diagram. The electronic device 200 comprises: a transceiver 210, a memory 220, a communication bus 230 and a processor 240.

[0104] The transceiver 210, the memory 220, and the processor 240 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses 230 or signal lines. The transceiver 210 is used to send and receive data. The memory 220 is used to store computer programs, such as storing Fig.10 The software function module shown in is the logical unit mapping device 100. The logical unit mapping device 100 includes at least one software function module that can be stored in the memory 220 in the form of software or firmware or fixed in the operating system (OS) of the electronic device 200. The processor 240 is used to execute the executable module stored in the memory 220, such as the software function module or computer program included in the logical unit mapping device 100. For example, the processor 240 is used to execute the above-mentioned logical unit mapping method.

[0105] Among them, the memory 220 can be, but is not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read-only memory (Programmable Read-Only Memory, PROM), erasable programmable read-only memory (Erasable Programmable Read-Only Memory, EPROM), electrically erasable read-only memory (Electric Erasable Programmable Read-Only Memory, EEPROM), etc.

[0106] The processor 240 may be an integrated circuit chip with signal processing capabilities. The above-mentioned processor may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a graphics processor (GPU), an accelerated processing unit (Accelerated Processing Unit), a multimedia application processor (MAP), a microprocessor, etc.; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The disclosed methods, steps and logic block diagrams in the embodiments of the present application may be implemented or executed. Alternatively, the processor 240 may also be any conventional processor, etc.

[0107] The electronic device 200 mentioned above includes but is not limited to a tablet, a notebook, a computer, etc.

[0108] An embodiment of the present application further provides a non-volatile computer-readable storage medium (hereinafter referred to as storage medium), on which a computer program is stored. When the computer program is run by a computer such as the above-mentioned electronic device 200, the above-mentioned logical unit mapping method is executed.

[0109] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0110] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0111] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0112] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a computer-readable storage medium, including several instructions for a computer device (which can be a personal computer, a laptop, a server, or an electronic device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned computer-readable storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0113] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A logical unit mapping method, characterized in that: include: Obtain the target logical unit that needs engineering change in the target object; Acquire all spare units in the target object that can be mapped to the target logical unit to obtain a spare unit set; Obtaining a repairability index after simulated mapping between the target logical unit and each spare unit in the spare unit set, wherein the repairability index represents the difficulty of repairing a violation caused by mapping between the target logical unit and the spare unit; According to all the repairability indices, a spare unit with the largest repairability index value is selected from the spare unit set; The target logic unit is mapped and replaced with the spare unit with the largest repairability index value.

2. The method according to claim 1, characterized in that Acquiring all spare units in the target object that can be mapped to the target logical unit, including: Acquire a target unit in the target object that has a connection relationship with the target logical unit; Acquire a first rectangular area in the target object that includes all target units that are connected to the target logical unit; All spare cells available for mapping to the target logical unit are acquired from the first rectangular area.

3. The method according to claim 1, characterized in that Obtaining a repairability index after simulation mapping between the target logical unit and each spare unit in the spare unit set, including: Traversing each spare unit in the spare unit set, and obtaining a repairability index of each target unit having a connection relationship between each spare unit and the target logical unit; According to the repairability index of each target unit having a connection relationship between each spare unit and the target logic unit, the repairability index of each spare unit after simulated mapping with the target logic unit is obtained.

4. The method according to claim 3, characterized in that Obtaining the repairability index of each target unit that has a connection relationship between each spare unit and the target logical unit, including: The number of target spare units in each second rectangular area corresponding to each spare unit is obtained, wherein the number of the target spare units represents a repairability index; a second rectangular area is a rectangular area including a spare unit and a target unit connected to the target logic unit, and the target spare unit is a spare unit that can be mapped into a buffer unit or an inverter unit.

5. The method according to claim 4, characterized in that Obtaining the number of target spare units in each second rectangular area corresponding to each spare unit includes: Traversing each second rectangular area corresponding to each spare unit, and obtaining the number of target spare units in each second rectangular area; The minimum value between the number of target spare units in each second rectangular area and the upper threshold is selected as the number of target spare units in each second rectangular area.

6. The method according to claim 4, characterized in that If there is a target spare unit located at the boundary of the second rectangular area, obtaining the number of target spare units in each second rectangular area corresponding to each spare unit includes: Traversing each second rectangular area corresponding to each spare unit, and obtaining a first number of target spare units located in each second rectangular area; Acquire a second number of boundary target spare cells located at a boundary of each second rectangular area; The number of target spare cells in each second rectangular area is acquired according to the first number and the second number.

7. The method according to claim 6, characterized in that Obtaining a second number of boundary target spare cells located at a boundary of each second rectangular region includes: For each boundary target spare unit, calculating the area ratio of the area of ​​each boundary target spare unit located within the boundary of the second rectangular area to the area of ​​the entire boundary target spare unit; According to the area ratio of each boundary target spare cell, a second number of boundary target spare cells located at the boundary of each second rectangular area is obtained.

8. The method according to claim 1, characterized in that According to all the repairability indicators, a spare unit with the largest repairability indicator value is selected from the spare unit set, including: Sort all repairability indicators to obtain sorting results; According to the sorting result, a spare unit with the largest repairability index value is selected from the spare unit set.

9. A logical unit mapping device, characterized in that: include: An acquisition module is used to acquire a target logic unit in a target object that needs to undergo an engineering change; acquire all spare units in the target object that can be mapped to the target logic unit to obtain a spare unit set; acquire a repairability index after simulated mapping between the target logic unit and each spare unit in the spare unit set, wherein the repairability index represents the difficulty of repairing a violation caused by mapping the target logic unit to the spare unit; A selection module, configured to select a standby unit with a maximum value of a repairability index from the standby unit set according to all the repairability indexes, wherein the standby unit has a maximum value of a repairability index; A mapping module is used to map and replace the target logical unit with the spare unit with the largest repairability index value.

10. An electronic device, characterized in that: include: A memory and a processor, wherein the processor is connected to the memory; The memory is used to store programs; The processor is used to call the program stored in the memory to execute the method according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: A computer program is stored thereon, and when the computer program is executed by a processor, the method according to any one of claims 1 to 8 is executed.

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