Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. A shift register in the display panel comprises N cascaded shift register units, each shift register unit comprises a driving module and a gating module, and one control end of each gating module is connected with the output end of the corresponding driving module; the output end of the driving module in the ith-level shift register unit is connected with the input end of the driving module in the (i + 1) th-level shift driving unit, i and N are integers, and 1 < = ilt; n; the gating module is configured to at least receive a signal output by the driving module and a frequency sweep control signal and output a frequency sweep signal; the sweep frequency control signal and the sweep frequency signal respectively comprise a ramp signal, the period of the sweep frequency control signal is n * H, H is the scanning time of a row of pixels, n is an integer, and n is greater than or equal to 2; in the period of the sweep frequency control signal, the width of a ramp signal in the sweep frequency control signal is (n-1) * H + A, 0lt; alt; h). According to the invention, gray scale regulation and control are more accurate, and the display effect is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, light-emitting diodes (LEDs) are widely used in the display field. For example, Micro-LEDs and Mini-LEDs are often used as display pixels. Micro-LEDs and Mini-LEDs are usually driven by pulse amplitude modulation (PAM) circuits and pulse width modulation (PWM) circuits. Among them, the PWM circuit regulates the light pulse width, and the PAM regulates the light pulse amplitude. A sweep frequency signal is required in the PWM+PAM circuit. Currently, one way to set the sweep frequency signal is to generate it using a shift register circuit and a gating circuit. At present, the sweep frequency signal generated in this way has a short working time when applied, and it is possible that the light-emitting path cannot be completely shut down during the working time. In addition, the short working time cannot achieve accurate grayscale control, which affects the display effect. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a display panel and a display device to solve the technical problem of increasing the working time of the sweep frequency signal and improving the display effect.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a shift register, the shift register comprising N cascaded shift register units, the shift register unit comprising a driving module and a gating module, a control end of the gating module is connected to an output end of the driving module; the output end of the driving module in the i-th shift register unit is connected to an input end of the driving module in the i+1-th shift driving unit, i and N are integers, 1≤i <N;

[0005] The gating module is configured to at least receive the signal output by the driving module and the sweep control signal, and output the sweep signal; the sweep control signal and the sweep signal respectively include a ramp signal, the period of the sweep control signal is n*H, H is the scanning time of a row of pixels, n is an integer, n≥2; wherein, in the period of the sweep control signal, the width of the ramp signal in the sweep control signal is (n-1)*H+A, 0 <A<H。

[0006] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the display panel provided by any embodiment of the present invention.

[0007] The display panel and the display device provided by the embodiments of the present invention have the following beneficial effects: the embodiment of the present invention sets the width of the ramp signal in the sweep control signal to (n-1)*H+A, and the width of the GND holding period in the sweep control signal is less than H, which can increase the proportion of the ramp signal in the sweep control signal cycle as much as possible, and then increase the width of the ramp signal of the sweep signal generated by the shift register unit, thereby increasing the working time of the sweep signal, and can ensure that the light-emitting path is completely shut down when the slope of the sweep signal remains unchanged, and make the grayscale control more precise, thereby improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0009] Figure 1 A schematic diagram of a period of a frequency sweep control signal in a related technology;

[0010] Figure 2 A schematic diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 3A A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0012] Figure 3B A signal timing diagram provided by an embodiment of the present invention;

[0013] Figure 4 Another signal timing diagram provided by an embodiment of the present invention;

[0014] Figure 5 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0015] Figure 6 A timing diagram of a pixel circuit provided by an embodiment of the present invention;

[0016] Figure 7 Another signal timing diagram provided by an embodiment of the present invention;

[0017] Figure 8 Another signal timing diagram provided by an embodiment of the present invention;

[0018] Fig. 9 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0020] The terms used in the embodiments of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise.

[0021] In the related art, the sweep signal sweep is generated by a shift register circuit and a gating circuit, and the sweep control signal sweep-in is output as the corresponding sweep signal sweep at the gating moment through the gating circuit. Figure 1 It is a schematic diagram of the period of the sweep control signal in a related art. In Figure 1 the embodiment, the period of the sweep control signal sweep-in is 6*H, where H represents the line time, that is, the scanning time corresponding to one row of pixels during display. There are 6 sweep control signals arranged in the display panel, namely the sweep control signal sweep-in1 to the sweep control signal sweep-in6. It can be seen from the signal waveform that in order to prevent signal interference between the sweep signals sweep corresponding to each pixel circuit row, it is necessary to set the sweep control signal sweep-in to have a GND holding period. Then the duration of the ramp signal in the sweep control signal sweep-in is 4*H + A′, where A′ < H. Thus, the working time of the generated sweep signal sweep is 4*H + A′. However, the working time of 4*H + A′ has limited gray-scale regulation for the light-emitting device and cannot achieve precise gray-scale regulation, and there may be a situation where the light-emitting path cannot be completely turned off during the working time.

[0022] To solve the problems existing in the related art, an embodiment of the present invention provides a display panel that generates a sweep signal using a shift register unit and sets the width of the ramp signal in the scan control signal to increase the proportion of the ramp signal in the period. Thereby, the waveform of the generated sweep signal can be adjusted, and the working time of the sweep signal can be increased in cooperation with other signals.

[0023] Figure 2 It is a schematic diagram of a display panel provided by an embodiment of the present invention. As Figure 2 shown, the display panel includes a shift register 1, and the shift register 1 includes N cascaded shift register units 10. Figure 2The two-stage shift register unit 10 is shown. The shift register unit 10 includes a driving module 11 and a gating module 12, wherein a control terminal of the gating module 12 is connected to an output terminal of the driving module 11; the output terminal of the driving module 11 in the i-th stage shift register unit 10(i) is connected to an input terminal of the driving module 11 in the i+1-th stage shift driving unit 10(i+1), where i and N are integers, and 1≤i <N。

[0024] The display panel also includes a plurality of pixel circuits 20, which are used to drive sub-pixels, and the sub-pixels may be, for example, Micro-LED, Mini-LED, or organic light-emitting devices. The plurality of pixel circuits 20 are arranged in a pixel circuit row 20h in the horizontal direction. For LED devices, they are current-driven devices, and the use of constant current drive can ensure that they can work stably under different working conditions, and can also significantly improve the service life of the device. The brightness of the LED is related to the current flowing through it, and the longer the current flows, the greater the luminous brightness. Therefore, the brightness of the LED can be adjusted by adjusting the flow time of the current, and the grayscale adjustment when the LED is used as a pixel can be realized in the application. In the embodiment of the present invention, the pixel circuit includes a first drive circuit PAM and a second drive circuit PWM, the first drive circuit PAM is a pulse amplitude modulation circuit, the second drive circuit PWM is a pulse width modulation circuit, the first drive circuit PAM is configured to control the amplitude of the drive current provided to the sub-pixel based on the first data voltage, and the second drive circuit PWM is configured to control the duration of the drive current provided to the sub-pixel based on the second data voltage. The output end of the gating module 12 is connected to the second drive circuit PWM. A plurality of sweep signal lines sweep (using the same mark as the scan signal sweep) are arranged in the display panel, and one sweep signal line sweep provides a sweep signal sweep to a plurality of second drive circuits PWM in a pixel circuit row 20h. Figure 2 It can be seen that the gating module 12 in the shift register unit 10 is connected to the second driving circuit PWM through the sweep signal line sweep. The sweep signal sweep includes a ramp signal. The sweep signal sweep and the second data voltage are used to cooperate to control the moment when the second driving circuit PWM provides a control signal to the first driving circuit PAM, thereby controlling the closing moment of the driving transistor in the first driving circuit PAM, and adjusting the time length of providing the driving current to the sub-pixel. The specific circuit operation process will be described in the following embodiment involving the pixel circuit.

[0025] in addition, Figure 2 The shift register unit 10 is shown as being located on one side of the pixel circuit row 20h. In some embodiments, the shift register unit 10 is disposed between two adjacent pixel circuit rows 20h, which can help narrow the frame of the display panel, and is not shown in the figure.

[0026] In the embodiment of the present invention, the gating module 12 is configured to at least receive the signal output by the driving module 11 and the sweep control signal sweep-in, and output the sweep signal sweep. Figure 3A A schematic diagram of a shift register unit provided by an embodiment of the present invention is shown in FIG. Figure 3A As shown, the shift register unit 10 includes a driving module 11 and a gating module 12, the driving module 11 includes an input terminal IN and an output terminal OUT, when the shift register unit 10 is cascaded, the input terminal IN of the driving module 11 is connected to the output terminal OUT of the driving module 11 in the previous stage shift register unit 10. The driving module 11 is any circuit structure capable of realizing signal shifting. The driving module includes a first transistor M1 and a second transistor M2, the control terminal of the first transistor M1 is connected to the first node Q1, the control terminal of the second transistor M2 is connected to the second node Q2, the first transistor M1 provides the first voltage signal VGH to the output terminal OUT of the driving module 11 under the control of the first node potential, and the second transistor M2 provides the second voltage signal VGL to the output terminal OUT of the driving module 11 under the control of the second node Q2 potential. The gating module 12 includes a third transistor M3 and a fourth transistor M4, the control end of the third transistor M3 is connected to the output end OUT of the driving module 11, and the control end of the fourth transistor M4 is connected to the first node Q1; the first end of the third transistor M3 receives the sweep control signal sweep-in, the first end of the fourth transistor M4 receives the third voltage signal sweep-V0, and the second end of the third transistor M3 and the second end of the fourth transistor M4 are connected to the output end of the gating module 12.

[0027] Optional, such as Figure 3AAs shown, the driving module 11 also includes a fifth transistor M5 to an eighteenth transistor M18. In the figure, M6 is the sixth transistor, M7 is the seventh transistor, and the other transistors are not described one by one. The driving module 11 also includes four capacitors, namely a first capacitor C1, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. The first node Q1, the second node Q2, the node Q3 and the node Q4 in the driving module 11, as well as the nodes Q5, Q6, QB1, and QB2 are marked. The operation of the driving module 11 requires a reset signal RST, a first clock signal CK, a second clock signal XCK, a first voltage signal VGH, and a second voltage signal VGL. The gating module 12 also includes a nineteenth transistor M19 and a fifth capacitor C5. The control end of the gating module 12 is connected to the driving module 11. Specifically, the control end of the third transistor M3 is connected to the output end OUT of the driving module 11 through the nineteenth transistor M19, and the control end of the fourth transistor M4 is connected to the first node Q1. For the driving module 11, when the second node Q2 is at a low potential and the first node Q1 is at a high potential, the output end OUT of the driving module 11 outputs a low level signal of the second voltage signal VGL; when the first node Q1 is at a low potential, the output end OUT of the driving module 11 outputs a high level signal of the first voltage signal VGH.

[0028] Figure 3B A signal timing diagram provided by an embodiment of the present invention can be applied to Figure 3A In combination with FIG. 3 and Figure 4In the t10 period, the first clock signal CK is low, the second clock signal XCK is high, the input terminal IN is high, the node Q3 is written to the high level, the node Q4 is written to the low level, the first node Q1 is written to the low level, the second node Q2 is written to the high level, and the output terminal OUT of the driving module 11 outputs a high level signal. In the t11 period, the first clock signal CK is high, the second clock signal XCK is low, the input terminal IN is low, the node Q3 maintains a high level, the node Q4 maintains a low level, the second node Q2 maintains a high potential, the first node Q1 maintains a low potential, and the output terminal OUT of the driving module 11 outputs a high level signal. In the t12 period, the first clock signal CK is low, the second clock signal XCK is high, the input terminal IN is low, the node Q3 is written to the low level, the node Q4 is written to the low level, the node Q3 controls the eighteenth transistor M18 to open, the first node Q1 is written to the high level, and at this time the second node Q2 is written to the low potential, and the output terminal OUT of the driving module 11 outputs a low level signal. During the t13 period, the first clock signal CK is at a low level, the second clock signal XCK is at a high level, the input terminal IN is at a high level, the node Q3 is written at a high level, the node Q4 is written at a low level, the first node Q1 is written at a high level, the second node Q2 is written at a high level, and the output terminal OUT of the driving module 11 maintains the output of a low-level signal. During the t14 period, the first clock signal CK is at a high level, the second clock signal XCK is at a low level, the input terminal IN is at a high level, the node Q3 maintains a high level, the node Q4 maintains a low level, the first node Q1 is written at a low level, the second node Q2 is written at a high level, and the output terminal OUT of the driving module 11 outputs a high-level signal. In addition, between the t12 and t13 periods, the first node Q1 maintains a high level, the second node Q2 maintains a low level, and the output terminal OUT of the driving module 11 outputs a low-level signal.

[0029] Figure 4 A signal timing diagram provided by an embodiment of the present invention can be applied to Figure 3A The shift register unit 10 is provided. Figure 3A , Figure 3B and Figure 4From the perspective of FIG. 1 , during the period when the second node Q2 is at a low potential and the first node Q1 is at a high potential, the output terminal OUT of the driving module 11 outputs a low-level signal, controls the third transistor M3 to turn on, and the gating module 12 outputs the waveform of the sweep control signal sweep-in as the sweep signal sweep. During the period when the first node Q1 is at a low potential, the output terminal OUT of the driving module 11 outputs a high-level signal, the low potential of the first node Q1 controls the fourth transistor M4 to turn on, and the gating module 12 outputs the voltage signal provided by the third voltage signal sweep-V0. According to the working process of the shift driving unit 10, the waveform of the sweep control signal sweep-in affects the working time of the sweep signal sweep.

[0030] In the embodiment of the present invention, the sweep control signal sweep-in is a periodic signal. The sweep control signal sweep-in and the sweep signal sweep respectively include ramp signals, and the ramp signal refers to a signal whose voltage varies with time. The period of the sweep control signal sweep-in is n*H, where H is the scanning time of a row of pixels, and n is an integer, n≥2; wherein, in the period of the sweep control signal sweep-in, the width of the ramp signal in the sweep control signal sweep-in is (n-1)*H+A, 0 <A<H。 Figure 4 Taking n=6 as an example, Figure 4 It can be seen that the sweep control signal sweep-in includes a ramp signal and a GND holding period. During the GND holding period, the sweep control signal sweep-in is a constant voltage signal, and the sum of the width of the ramp signal and the width of the GND holding period is one cycle. It can be understood that the width of the signal in the embodiment of the present invention refers to the duration of the signal.

[0031] In the embodiment of the present invention, the width of the ramp signal in the sweep control signal sweep-in is set to (n-1)*H+A, so the width of the GND holding period in the sweep control signal sweep-in is less than H, which can increase the proportion of the ramp signal in the sweep control signal sweep-in period as much as possible, and then increase the width of the ramp signal of the sweep signal sweep generated by the shift register unit 10, thereby increasing the working time of the sweep signal sweep, and can ensure that the light-emitting path is completely turned off when the slope of the sweep signal sweep remains unchanged, and make the grayscale control more accurate, thereby improving the display effect.

[0032] In the embodiment of the present invention, the driving module 11 has the function of signal shifting, and the effective level width of the output signal of the output terminal OUT of the driving module 11 is not less than the effective level width of the received signal of the input terminal IN. The effective level refers to the level that can control the transistor connected to it to turn on. Figure 4The effective level is low level for illustration. The input end of the driving module 11 in the first-stage shift register unit 10 receives the start signal STV, and the width of the effective level in the start signal STV is t 0 , t 0 ≥(n-1)*H+A. Taking n=6 as an example, the width of the ramp signal in the sweep control signal sweep-in is 5*H+A, and the width of the effective level in the start signal STV is t 0 ≥5*H+A. In the embodiment of the present invention, the width of the effective level in the start signal STV is set to be not less than the width of the ramp signal in the sweep control signal sweep-in, and the effective level width of the signal output by the output terminal OUT of the driving module 11 is not less than the width of the ramp signal in the sweep control signal sweep-in. Therefore, when the control gating module 12 is working, the ramp signal in the sweep control signal sweep-in can be completely output as the sweep signal sweep through the signal at the output terminal OUT of the driving module 11, thereby increasing the working time of the sweep signal sweep.

[0033] In some embodiments, n is an even number, and the width t of the effective level in the start signal STV is 0 =(n+1)*H. Combination Figure 3B From the schematic timing diagram, the signal shifting work of the driving module 11 requires the cooperation of the first clock signal CK and the second clock signal XCK. Among them, in the t12 period, the first clock signal CK is at a low level, and the output terminal OUT of the driving module 11 starts to output a low-level signal. In the t14 period, the first clock signal CK is at a high level, and the output terminal OUT of the driving module 11 starts to output a high-level signal, that is, the output of the low-level signal ends. From the start time of the t12 period to the start time of the t14 period, the first clock signal CK has four low-level pulses and three high-level pulses, and one pulse is one line time, that is, the duration of the low-level signal output by the output terminal OUT is an odd number of line times. Therefore, limited by the structure and working principle of the driving module 11, the effective level signal output by its output terminal OUT can only exist for an odd number of line times, and the t14 period is set. 0 =(n+1)*H, which can make the effective level width of the output signal at the output end OUT of the driving module 11 be (n+1)*H. The effective level width of the output signal at the output end OUT of the driving module 11 is greater than the period of the sweep control signal sweep-in, and when the control gating module 12 is working, the signal at the output end OUT of the driving module 11 can be used to control the complete output of the ramp signal in the sweep control signal sweep-in as the sweep signal sweep, thereby increasing the working time of the sweep signal sweep.

[0034] In some embodiments, Figure 4As shown, the ramp signal in the sweep signal sweep includes a first ramp signal B1 and a second ramp signal B2, and the width of the second ramp signal B2 is smaller than the width of the first ramp signal B1. The width of the first ramp signal B1 is (n-1)*H+A. Figure 3A and Figure 4 From the perspective of FIG. 1 , during the period when the output terminal OUT of the driving module 11 outputs a low level (i.e., an effective level), the nineteenth transistor M19 is controlled to be turned on, and the ramp signal in the sweep control signal sweep-in is output as the sweep signal sweep. The width of the first ramp signal B1 in the sweep signal sweep is the working time of the sweep signal sweep. Since the effective level width of the output signal at the output terminal OUT of the driving module 11 is greater than the cycle of the sweep control signal sweep-in, during the period when the output terminal OUT of the driving module 11 outputs a low level, the gating module 12 not only outputs the waveform of the sweep control signal sweep-in within one cycle, but also outputs the waveform of part of the sweep control signal sweep-in within the next cycle. As a result, the ramp signal in the sweep signal sweep includes the first ramp signal B1 and the second ramp signal B2. The second ramp signal B2 is equivalent to a small tailing phenomenon of the sweep signal sweep.

[0035] In the embodiment of the present invention, the width of the second ramp signal B2 is smaller than H. Figure 4 From the perspective of the sweep control signal sweep-in waveform, during the period when the output terminal OUT of the driving module 11 outputs a low level, the sweep signal sweep includes not only the first ramp signal B1 and the second ramp signal B2, but also a constant voltage signal. For example, there will be a constant voltage signal V between the first ramp signal B1 and the second ramp signal B2, and the width of the constant voltage signal V is substantially equal to the width of the GND holding period. The width of the second ramp signal B2 is set to be less than H, and the sum of the width of the constant voltage signal V and the width of the second ramp signal B2 is equal to H, which can ensure that the width of the first ramp signal B1 is large enough, so that the sweep signal sweep has a larger working time.

[0036] In some embodiments, Figure 5 A schematic diagram of a pixel circuit provided by an embodiment of the present invention is shown in FIG. Figure 5 As shown, the pixel circuit includes a first driving circuit PAM and a second driving circuit PWM. The first driving circuit PAM is configured to control the amplitude of the driving current provided to the sub-pixel based on the first data voltage PAM-Data, and the second driving circuit PWM is configured to control the duration of the driving current provided to the sub-pixel based on the second data voltage PWM-Data. Figure 5 The sub-pixel is illustrated as including a light emitting device LED.

[0037] The first driving circuit PAM includes a first driving transistor T7, a first gate reset transistor T8, a first data writing transistor T9, a first compensation transistor T10, a first control transistor T11, a second control transistor T12, an electrode reset transistor T13 and a first storage capacitor C20. The first storage capacitor C20 is a storage capacitor in the first driving circuit PAM. The first driving transistor T7 is connected in series between the first control transistor T11 and the second control transistor T12, the first control transistor T11 is connected between the first power supply voltage PAM-vdd and the first electrode of the second driving transistor T7, and the second control transistor T12 is connected between the second electrode of the first driving transistor T7 and the light emitting device LED. The first driving transistor T7 is configured to generate a driving current under the control of its gate voltage. The first data writing transistor T9 is connected to the first electrode of the first driving transistor T7, the first compensation transistor T10 is connected to the second electrode and the control end of the first driving transistor T7, and the first gate reset transistor T8 is connected to the control end (i.e., the gate) of the first driving transistor T7. The first plate of the first storage capacitor C20 is connected to the gate of the first driving transistor T7, and the second plate of the first storage capacitor C20 is connected to the first power supply voltage PAM-vdd. The electrode reset transistor T13 is connected to the first electrode of the light-emitting device LED, the second control transistor T12 is also connected to the first electrode of the light-emitting device LED, and the second electrode of the light-emitting device LED is connected to the third power supply voltage VEE. The gate of the first gate reset transistor T8 is connected to the first scan signal PAM-S1; the gates of the first data write transistor T9, the first compensation transistor T10, and the electrode reset transistor T13 are connected to the second scan signal PAM-S2. The control end of the first control transistor T11 and / or the control end of the second control transistor T12 receive the first control signal PAM-EM. In addition, Figure 5 The first end of the electrode reset transistor T13 receives the third power supply voltage VEE, and the second end is connected to the first electrode of the light emitting device LED. In other embodiments, the first end of the electrode reset transistor T13 may receive the reset signal PAM-REF or the constant voltage signal PAM-INIT.

[0038] The second driving circuit PWM includes a second driving transistor T1, a second gate reset transistor T2, a second data writing transistor T3, a second compensation transistor T4, a third control transistor T5, a fourth control transistor T6, and a second storage capacitor C10. The third control transistor T5 is connected between the second power supply voltage PWM-vdd and the first electrode of the second driving transistor T1, and the fourth control transistor T6 is connected between the second electrode of the second driving transistor T1 and the gate of the first driving transistor T7. The second data writing transistor T3 is connected to the first electrode of the second driving transistor T1, the second compensation transistor T4 is connected to the second electrode and the gate of the second driving transistor T1, and the second gate reset transistor T2 is connected to the gate of the second driving transistor T1, wherein the gate of the second gate reset transistor T2 is connected to the third scanning signal PWM-S1; the gates of the second data writing transistor T3 and the second compensation transistor T4 are connected to the fourth scanning signal PWM-S2. The gates of the third control transistor T5 and the fourth control transistor T6 are connected to the second control signal PWM-EM.

[0039] 5 shows that the output end of the second driving circuit PWM (i.e., the output end of the fourth control transistor T6) is connected to the gate of the first driving transistor T7. In another embodiment, the output end of the second driving circuit PWM is connected to the gate of the second control transistor T12, which is not shown in the figure. In another embodiment, an additional light-emitting duration control transistor is provided in the light-emitting series circuit of the first driving circuit PAM, such as Figure 5 A light-emission duration control transistor is connected in series between the second control transistor T12 and the light-emitting device LED, and the output end of the second drive circuit PWM is connected to the gate of the light-emission duration control transistor.

[0040] Figure 6 A timing diagram of a pixel circuit provided by an embodiment of the present invention. Figure 6 From the perspective of the first driving circuit PAM, in the reset phase t21, the first scanning signal PAM-S1 provides a low level period to control the first gate reset transistor T8 to turn on, and the reset signal PAM-REF is used to reset the gate of the first driving transistor T7; in the writing phase t22, the second scanning signal PAM-S2 provides a low level to control the first data writing transistor T9 and the first compensation transistor T10 to turn on and write the first data voltage PAM-Data to the gate of the first driving transistor T7. In the light-emitting phase t23, the first control signal PAM-EM provides a low level to control the first control transistor T11 and the second control transistor T12 to turn on, and the first driving transistor T7 generates a driving current to provide to the light-emitting device LED.

[0041] For the second driving circuit PWM, in the reset phase t21, the third scanning signal PWM-S1 provides a low level to control the second gate reset transistor T2 to turn on, and the reset signal PWM-REF is used to reset the gate of the second driving transistor T1; in the writing phase t22, the fourth scanning signal PWM-S2 provides a low level to control the second data writing transistor T3 and the second compensation transistor T4 to turn on, and the second data voltage PWM-Data is written into the gate of the second driving transistor T1. In the light-emitting phase t23, the second control signal PWM-EM provides a low level to control the third control transistor T5 and the fourth control transistor T6 to turn on. As the voltage on the sweep signal sweep gradually changes, the gate voltage of the second driving transistor T1 gradually changes due to the coupling effect of the second storage capacitor C10. When the gate voltage of the second driving transistor T1 changes to make the second driving transistor T1 reach the on state, the current generated by the second driving transistor T1 will cause the gate voltage of the first driving transistor T7 to change until the first driving transistor T7 is turned off, thereby the first driving circuit PAM stops providing the driving current to the light-emitting device LED, that is, the duration of providing the driving current is controlled by the second driving circuit PWM.

[0042] like Figure 6 As shown, in the operation of the pixel circuit, the effective level period in the first control signal PAM-EM and the second ramp signal B2 in the sweep signal sweep do not overlap. That is, in the second ramp signal B2 period of the sweep signal sweep, the first control signal PAM-EM is at a non-effective level, and during this period the first control transistor T11 and the second control transistor T12 are in a closed state, so the second ramp signal B2 in the sweep signal sweep does not cause the first drive circuit PAW to provide a drive current, and does not affect the duration of the pixel circuit providing a drive current.

[0043] In some embodiments, Figure 6 As shown, the first ramp signal B1 in the sweep signal sweep appears earlier than the second ramp signal B2. In the operation of the pixel circuit, the end time of the effective level in the first control signal PAM-EM is not later than the start time of the second ramp signal B2. In this way, the effective level period of the first control signal PAM-EM and the second ramp signal B2 in the sweep signal sweep do not overlap, and the effective level period of the first control signal PAM-EM overlaps with the first ramp signal B1, ensuring that the working time of the first ramp signal B1 in the sweep signal sweep is reasonable and fully utilized.

[0044] like Figure 6As shown, in the operation of the pixel circuit, the starting time of the first ramp signal B1 is earlier than the starting time of the effective level in the first control signal PAM-EM, that is, earlier than the falling edge of the first control signal PAM-EM. Such a setting can ensure that the sub-pixel can have a dark state without emitting light, and meet the grayscale setting requirements of the sub-pixel. Based on the working principle of the pixel circuit, it can be known that the duration of the light-emitting current is controlled by the second data voltage PWM-Data, that is, the actual light-emitting duration is controlled. The maximum value in the preset value range of the second data voltage PWM-Data controls the light-emitting device LED to have the maximum light-emitting time, and the minimum value controls the light-emitting device LED to have the minimum light-emitting time, that is, the light-emitting device LED is not emitting light. In order to ensure that the light-emitting device LED can have a non-emitting state, it is required that when the minimum value of the second data voltage PWM-Data is written into the second driving circuit PWM, the sweep signal sweep changes within a certain time period to enable the second driving transistor T1 in the second driving circuit PWM to reach the open state. When the second driving transistor T1 is already in the on state, the gate voltage of the first driving transistor T7 in the first driving circuit PAM has been pulled up so that the driving transistor is in the off state. Even if the first control signal PAM-EM is at a valid level, no driving current is generated, thereby making the light emitting device LED in a dark state.

[0045] like Figure 6 As shown, in the operation of the pixel circuit, the time length between the start time of the first ramp signal B1 and the start time of the effective level in the first control signal PAM-EM is t 1 The time length between the start time of the effective level in the first control signal PAM-EM and the end time of the first slope signal B1 is t 2 , t 1 <t 2 Such an arrangement not only ensures that the sub-pixel is in a dark state without emitting light, but also enables the duration for adjusting the grayscale display of the sub-pixel to be long enough, thereby achieving more accurate grayscale adjustment.

[0046] In some embodiments, t 1 ≥H. That is, t 1 The minimum value of is a row time H. 1 The setting of needs to consider the configurable value of the sweep signal sweep slope and the minimum value of the second data voltage PWM-Data. 1 To coordinate so that at t 1 During the time period, the second driving transistor T1 in the second driving circuit PWM can reach the turned-on state.

[0047] In some embodiments, H <t 2≤(n-2)*H+A. This arrangement allows the overlap time of the effective level in the first control signal PAM-EM and the first ramp signal B1 to be long enough, so that the working time of the first ramp signal B1 can be fully utilized, ensuring that the light-emitting path is completely turned off, and making the grayscale control more accurate, thereby improving the display effect.

[0048] In some embodiments, the effective level period in the first control signal PAM-EM may partially overlap with the constant voltage signal period between the first ramp signal B1 and the second ramp signal B2. The width of the effective level in the first control signal PAM-EM is (n-1)*H. For example, when n=6, the width of the first ramp signal B1 is 5*H+A, and the width of the effective level in the first control signal PAM-EM is 5*H. The width of the effective level in the first control signal PAM-EM can be coordinated with the width of the first ramp signal B1 to ensure that the working time of the first ramp signal B1 is reasonably and fully utilized, so that the grayscale control is more accurate.

[0049] In some embodiments, Figure 7 Another signal timing diagram provided by an embodiment of the present invention, Figure 7 The timing of several control signals required by the display panel is illustrated in FIG. Among them, the input terminal IN of the driving module 11 in the first-stage shift register unit 10 receives the start signal STV, and the effective level width of the output signal of the output terminal OUT of the driving module 11 is affected by the signal of its input terminal IN. It can be known from the relevant description of the above embodiment that the effective level of the output terminal OUT of the driving module 11 controls the sweep control signal sweep-in output by the selection module 12 as the sweep signal sweep. Figure 7 It can be seen that in the embodiment of the present invention, the width of the effective level in the start signal STV is set to be greater than the width of the effective level in the first control signal PAM-EM, thereby enabling the width of the first ramp signal B1 in the sweep signal sweep to match the width of the effective level in the first control signal PAM-EM, thereby increasing the working time of the sweep signal sweep.

[0050] In some embodiments, Figure 5 As shown, the control end of the third control transistor T5 and / or the control end of the fourth control transistor T6 in the second driving circuit PWM receives the second control signal PWM-EM. Figure 6It can be seen from the timing diagram that in the operation of the pixel circuit, the width of the effective level in the second control signal PWM-EM is greater than the width of the effective level in the first control signal PAM-EM. This arrangement enables the second driving transistor T1 to be turned on by the sweep signal sweep at any time point when the first control signal PAM-EM provides an effective level, thereby controlling the gate voltage change of the first driving transistor T7 in the first driving circuit PAM, thereby controlling the duration of providing the driving current.

[0051] like Figure 6 As shown, in the operation of the pixel circuit, the start time of the effective level in the second control signal PWM-EM is earlier than the start time of the effective level in the first control signal PAM-EM. Such a setting can realize the coordination of the second control signal PWM-EM with the first ramp signal B1. When the minimum value of the second data voltage PWM-Data is written into the second driving circuit PWM, the sweep signal sweep changes within a certain time period to enable the second driving transistor T1 to reach the on state, and then the gate voltage of the first driving transistor T7 in the first driving circuit PAM is pulled up to make the driving transistor in the off state. Even if the first control signal PAM-EM is at an effective level later, no driving current will be generated, so that the light-emitting device LED is in a dark state.

[0052] like Figure 6 As shown, in the operation of the pixel circuit, the end time of the effective level in the second control signal PWM-EM is later than the end time of the effective level in the first control signal PAM-EM. This arrangement enables the second driving transistor T1 to be turned on by the sweep signal sweep at any time point when the first control signal PAM-EM provides an effective level, thereby controlling the gate voltage change of the first driving transistor T7 in the first driving circuit PAM, thereby achieving control of the duration of providing the driving current.

[0053] In some embodiments, Figure 6 As shown, in the operation of the pixel circuit, the width of the effective level in the second control signal PWM-EM is greater than the sum of the widths of the first ramp signal B1 and the second ramp signal B2 in the sweep signal sweep. The width of the effective level in the second control signal PWM-EM is set large enough to ensure that it can match the working time of the sweep signal sweep and make full and reasonable use of the working time of the sweep signal sweep.

[0054] In some embodiments, Figure 8Another signal timing diagram provided for an embodiment of the present invention. In the embodiment of the present invention, the period of the sweep control signal sweep-in is n*H. The display panel includes n sweep control signal lines, that is, the number of sweep control signal lines is the same as the number of periods of the sweep control signal sweep-in. The sweep control signal line sweep-in provides the sweep control signal sweep-in, and the sweep control signal line sweep-in and the sweep control signal sweep-in provided by it use the same mark. The n sweep control signal lines sweep-in include the first sweep control signal line sweep-in1, the second sweep control signal line sweep-in2, to the nth sweep control signal line sweep-inn arranged in sequence, and the start time of the period of the sweep control signal sweep-in provided by two adjacent sweep control signal lines sweep-in in the order differs by H. Figure 8 In the figure, n=6 is used for illustration.

[0055] In the embodiment of the present invention, the gating module 12 in the j-th shift register unit 10 and the gating module 12 in the n*m+j-th shift register unit 10 are connected to the j-th sweep control signal line sweep-in, where j and m are integers, 1≤j≤n, 1≤m≤(N / n)-1. For example, when n=6, the gating module 12 in the 1st shift register unit 10 and the gating module 12 in the 7th shift register unit 10 are connected to the 1st sweep control signal line sweep-in1. In the embodiment of the present invention, n sweep control signal lines sweep-in are arranged in the display panel, and the number of stages of the shift register unit 10 connected to the sweep control signal line sweep-in is set, so that multiple sweep control signals sweep-in can be sequentially output through the multi-stage shift register unit 10 to achieve row-by-row driving of multiple pixel circuit rows.

[0056] Based on the same inventive concept, an embodiment of the present invention provides a display device, Fig. 9 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Fig. 9 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, a mobile phone, a tablet, a television, a smart billboard, or a spliced ​​display device.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that: The invention comprises a shift register, wherein the shift register comprises N cascaded shift register units, wherein the shift register unit comprises a driving module and a gating module, wherein a control end of the gating module is connected to an output end of the driving module; wherein the output end of the driving module in the i-th shift register unit is connected to an input end of the driving module in the i+1-th shift driving unit, wherein i and N are integers, and 1≤i <N; The gating module is configured to at least receive the signal output by the driving module and the sweep control signal, and output the sweep signal; the sweep control signal and the sweep signal respectively include a ramp signal, and the period of the sweep control signal is n*H, H is the scanning time of a row of pixels, n is an integer, n≥2; wherein, in the period of the sweep control signal, the width of the ramp signal in the sweep control signal is (n-1)*H+A, 0 <A<H。 2. The display panel according to claim 1, characterized in that: The input end of the driving module in the first-stage shift register unit receives a start signal, and the width of the effective level in the start signal is t0, t0≥(n-1)*H+A.

3. The display panel according to claim 2, characterized in that: n is an even number, t0=(n+1)*H.

4. The display panel according to claim 1, characterized in that: The ramp signal in the frequency sweep signal includes a first ramp signal and a second ramp signal. The width of the first ramp signal is (n-1)*H+A, and the width of the second ramp signal is smaller than that of the first ramp signal.

5. The display panel according to claim 4, characterized in that: The width of the second ramp signal is smaller than H.

6. The display panel according to claim 4, characterized in that: The display panel includes a pixel circuit, wherein the pixel circuit includes a first driving circuit and a second driving circuit, wherein the first driving circuit is configured to control the amplitude of a driving current provided to a sub-pixel based on a first data voltage, and the second driving circuit is configured to control the duration of the driving current provided to the sub-pixel based on a second data voltage; The output end of the gating module is connected to the second driving circuit; The first driving circuit includes a first driving transistor, a first control transistor and a second control transistor, wherein the first driving transistor is connected in series between the first control transistor and the second control transistor; a control terminal of the first control transistor and / or a control terminal of the second control transistor receives a first control signal; During operation of the pixel circuit, the effective level period in the first control signal and the second ramp signal do not overlap.

7. The display panel according to claim 6, characterized in that: During operation of the pixel circuit, the end time of the effective level in the first control signal is no later than the start time of the second ramp signal.

8. The display panel according to claim 6, characterized in that: During operation of the pixel circuit, a starting time of the first ramp signal is earlier than a starting time of a valid level in the first control signal.

9. The display panel according to claim 8, characterized in that: In the operation of the pixel circuit, the time length between the start time of the first ramp signal and the start time of the effective level in the first control signal is t1, the time length between the start time of the effective level in the first control signal and the end time of the first ramp signal is t2, t1 <t2。 10. The display panel according to claim 9, characterized in that: t1≥H.

11. The display panel according to claim 9, characterized in that: H <t2≤(n-2)*H+A。 12. The display panel according to claim 6, characterized in that: The width of the effective level in the first control signal is (n-1)*H.

13. The display panel according to claim 6, characterized in that: The input end of the driving module in the shift register unit of the first stage receives a start signal; The width of the effective level in the start signal is greater than the width of the effective level in the first control signal.

14. The display panel according to claim 6, characterized in that: The second driving circuit comprises a second driving transistor, a third control transistor and a fourth control transistor, wherein the second driving transistor is connected in series between the third control transistor and the fourth control transistor; a control terminal of the third control transistor and / or a control terminal of the fourth control transistor receives a second control signal; In the operation of the pixel circuit, a width of an effective level in the second control signal is greater than a width of an effective level in the first control signal.

15. The display panel according to claim 14, characterized in that: During operation of the pixel circuit, a starting time of a valid level in the second control signal is earlier than a starting time of a valid level in the first control signal.

16. The display panel according to claim 6, characterized in that: During operation of the pixel circuit, an end time of the effective level in the second control signal is later than an end time of the effective level in the first control signal.

17. The display panel according to claim 6, characterized in that: The second driving circuit comprises a second driving transistor, a third control transistor and a fourth control transistor, wherein the second driving transistor is connected in series between the third control transistor and the fourth control transistor; a control terminal of the third control transistor and / or a control terminal of the fourth control transistor receives a second control signal; During operation of the pixel circuit, a width of an effective level in the second control signal is greater than a sum of widths of the first ramp signal and the second ramp signal in the frequency sweep signal.

18. The display panel according to claim 1, characterized in that: The display panel comprises n sweep frequency control signal lines, wherein the sweep frequency control signal lines provide the sweep frequency control signal; the n sweep frequency control signal lines comprise the first sweep frequency control signal line, the second sweep frequency control signal line, to the nth sweep frequency control signal line arranged in sequence, and the start time of the cycle of the sweep frequency control signal provided by two adjacent sweep frequency control signal lines in the sequence differs by H; Among them, the gating module in the j-th shift register unit and the gating module in the n*m+j-th shift register unit are connected to the j-th frequency sweep control signal line, j and m are integers, 1≤j≤n, 1≤m≤(N / n)-1.

19. The display panel according to claim 1, characterized in that: The driving module comprises a first transistor and a second transistor, wherein a control end of the first transistor is connected to a first node, a control end of the second transistor is connected to a second node, the first transistor provides a first voltage signal to an output end of the driving module under the control of the potential of the first node, and the second transistor provides a second voltage signal to the output end of the driving module under the control of the potential of the second node; The gating module includes a third transistor and a fourth transistor, the control end of the third transistor is connected to the output end of the driving module, and the control end of the fourth transistor is connected to the first node; the first end of the third transistor receives the frequency sweep control signal, the first end of the fourth transistor receives the third voltage signal, and the second end of the third transistor and the second end of the fourth transistor are connected to the output end of the gating module.

20. A display device, characterized in that: A display panel comprising any one of claims 1 to 19.

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