Surface-mounted electronic ceramic chip for multi-layer lamination, manufacturing method and system

Abstract

The invention discloses a surface-mounted electronic ceramic chip for multi-layer lamination, a manufacturing method and a system, the surface-mounted electronic ceramic chip comprises a ceramic body and an electrode group, and the electrode group comprises a first electrode and a second electrode; the ceramic body is provided with upper and lower end faces and side faces between the upper and lower end faces, the side faces at least comprise a first side face and a second side face, the first electrode covers part of the upper end face and at least part of the first side face, and the second electrode covers part of the lower end face and at least part of the second side face; the first electrode and the second electrode are formed through one-time machining, and the thickness of the first electrode and the thickness of the second electrode are uniform. According to the surface-mounted electronic ceramic chip provided by the embodiment of the invention, the first electrode and the second electrode which are uniform in thickness are processed and formed on the three-dimensional ceramic body at one time, so that the electrode group formed on the three-dimensional ceramic body has better consistency and compactness, and the electrical performance of the single-layer surface-mounted electronic ceramic chip is effectively improved; and meanwhile, the ceramic chips can be easily connected in parallel and stacked to form a multi-layer patch element.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic ceramic components including varistors, and in particular to a surface-mount electronic ceramic chip for multi-layer stacking, a manufacturing method and a system. Background Art

[0002] In the current electronic manufacturing industry, the surface mount technology (SMT) using patch components has become the mainstream production process, occupying 80% to 90% of the market share of printed circuit board (PCB) processing. However, in a few fields such as power modules, some components have slow progress in patch structure due to their electrical characteristics, and they are mainly processed by traditional lead insertion welding. Varistors are one of them. Varistors require large electrodes due to instantaneous overcurrent, so their patch structure has great technical difficulties.

[0003] At present, there are varistors that have realized a single-layer chip structure, for example: a rectangular strip varistor device disclosed in a Chinese patent application number of 2013203516840; it is first made into a rectangular porcelain body (ceramic body) of the varistor, and then metal electrodes are coated on the two end faces, and a thin copper strip is welded on the metal electrode, and then the ceramic body coated with electrodes is insulated and packaged with resin, and the exposed lead copper strip is shaped to form a lead terminal, which is convenient for surface mounting welding. Since the porcelain body of the chip varistor of this structure can be made thicker, a product that can be used in low-voltage power grid voltage-for example, AC 220V voltage can be obtained. However, considering the high working voltage, it is also necessary to withstand the instantaneous pulses of high voltage and high current brought by strong surges such as lightning surges. The bending and forming of the lead copper strip at the end part must fully consider sufficient insulation space to ensure that there is no short circuit and no high-voltage arc discharge breakdown when discharging the surge, which leads to the disadvantages of complex structure of the end lead part, excessive space occupation, and inability to stack ceramic pieces in parallel. Since the electrode area of ​​the single-layer ceramic body is limited and the allowed flow rate is too small, if the flow rate needs to be increased, the electrode area needs to be increased, thereby increasing the length and width of the component, which is inconsistent with the requirements of small size and high performance of modern electronic technology. Therefore, the application scope of the single-layer chip varistor is currently greatly limited. Summary of the invention

[0004] The purpose of the present invention is to overcome the problems of the existing single-layer SMD varistor structure that the end surfaces are coated with metal electrodes and a thin copper strip is welded on the metal electrode, such as the end lead part has a complex structure, occupies too much space, and cannot be stacked in parallel with ceramic chips. The present invention provides a SMD electronic ceramic chip, a manufacturing method and a system. The present invention forms a first electrode and a second electrode with uniform thickness on a three-dimensional ceramic body at one time, so as to ensure that the electrode group formed on the three-dimensional ceramic body has better consistency and density.， Effectively improve the electrical performance of single-layer SMD electronic ceramic chips. Only the lead-out electrode needs to be connected to the electrode on the side of the ceramic body, and there is no need to extend it to the end surface for connection. At the same time, it is easy to stack ceramic chips in parallel to form multi-layer SMD components.

[0005] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0006] A patch-type electronic ceramic chip for multi-layer stacking includes: a ceramic body and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body, and the electrode group includes: a first electrode and a second electrode;

[0007] The ceramic body has an upper and lower end surface and side surfaces between the upper and lower end surfaces, the side surfaces at least include a first side surface and a second side surface, the first electrode covers a portion of the upper end surface and at least a portion of the first side surface, and the second electrode covers a portion of the lower end surface and at least a portion of the second side surface; wherein the first electrode covered on the first side surface is used to connect with the corresponding first extraction electrode, and the second electrode covered on the second side surface is used to connect with the corresponding second extraction electrode;

[0008] The first electrode and the second electrode are formed by one-time processing, and the thickness of the first electrode and the second electrode is uniform.

[0009] According to a specific embodiment, in the above-mentioned surface-mount electronic ceramic chip, the thickness of the first electrode and the second electrode is 2um to 15um. ；

[0010] The nominal thickness error rate of the first electrode (1) and the nominal thickness error rate of the second electrode (2) do not exceed a preset value, and the preset value ranges from [-15%, 15%].

[0011] According to a specific implementation, in the above-mentioned surface-mount electronic ceramic chip, the preset value has a value range of [-8%, 8%].

[0012] According to a specific implementation, in the above-mentioned surface-mount electronic ceramic chip, the first electrode and the second electrode are formed by a sputtering process.

[0013] According to a specific embodiment, in the above-mentioned surface-mount electronic ceramic chip, there is a partition between the first electrode and the second electrode, and the partition is located at the edge position of the upper end surface of the ceramic body, and another partition is arranged at the edge position of the lower end surface in the diagonal direction.

[0014] According to a specific implementation, in the above-mentioned surface-mount electronic ceramic chip, the electronic ceramic chip is a varistor chip, a capacitor chip or a thermistor chip.

[0015] Furthermore, the electronic ceramic chip is a varistor chip.

[0016] Another aspect of the present invention provides a method for manufacturing a surface mount electronic ceramic chip, wherein the surface mount electronic ceramic chip comprises: a ceramic body and an electrode group, wherein the electrode group is disposed on the outer surface of the ceramic body, and wherein the electrode group comprises: a first electrode and a second electrode;

[0017] The ceramic body has an upper and lower end surface and side surfaces between the upper and lower end surfaces, the side surfaces at least include a first side surface and a second side surface, the first electrode covers a portion of the upper end surface and at least a portion of the first side surface, and the second electrode covers a portion of the lower end surface and at least a portion of the second side surface; wherein the first electrode covered on the first side surface is used to connect with the corresponding first extraction electrode, and the second electrode covered on the second side surface is used to connect with the corresponding second extraction electrode;

[0018] The method comprises: in a vacuum environment, using a double-sided sputtering process to generate a first electrode and a second electrode of the surface-mount electronic ceramic chip by one sputtering process; or using two single-sided sputtering processes to generate the first electrode and the second electrode of the surface-mount electronic ceramic chip by sputtering respectively, wherein the thickness of the first electrode and the second electrode are uniform.

[0019] According to a specific implementation, in the above-mentioned surface-mount electronic ceramic chip manufacturing method, the thickness of the first electrode and the second electrode is 2um to 15um, and the nominal thickness error rate of the first electrode and the nominal thickness error rate of the second electrode do not exceed a preset value, and the preset value range is [-15%, 15%].

[0020] According to a specific embodiment, in the above-mentioned surface-mount electronic ceramic chip manufacturing method, the method also includes: using a sputtering mask shielding process to provide a partition between the first electrode and the second electrode; or using a grinding or cutting process to grind away the deposited metal layer on the surface of the ceramic body to provide a partition between the first electrode and the second electrode.

[0021] Another aspect of the present invention provides a sputtering electrode manufacturing system for surface-mount electronic ceramic chips, which uses a fixture and a mask with a specific inclination angle to achieve simultaneous and uniform vacuum sputtering coating of the end face and side face of any electrode of a ceramic body to form an electrode surface with uniform thickness.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The surface mount electronic ceramic chip provided in the embodiment of the present invention can ensure that there will be no oxidation phenomenon and structural dislocation phenomenon on any cross section of the electrode by forming the first electrode and the second electrode in one process. At this time, the first electrode or the second electrode is uniform on its corresponding end face and side face; on this basis, by integrally forming the first electrode and the second electrode with uniform thickness, the conductivity of the electrode group on any cross section can be the same, and no local hot spots will appear; therefore, the surface mount electronic ceramic chip provided in the present application has better consistency and density. ， It effectively improves the electrical performance of single-layer SMD electronic ceramic chips. At the same time, the lead-out electrodes made of thin copper strips only need to be connected to the side electrodes of the ceramic body and do not need to extend to the end electrodes of the ceramic body, which greatly simplifies the structure and lead-out method of the lead-out electrodes and makes it easy to stack ceramic chips in parallel to form multi-layer SMD components. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of the first structure of a surface-mount electronic ceramic chip according to an exemplary embodiment of the present invention;

[0025] Figure 2 A second structural schematic diagram of a surface-mount electronic ceramic chip according to an exemplary embodiment of the present invention;

[0026] Figure 3 It is a schematic diagram of the structure of a ceramic body (piezoresistive ceramic body) according to an exemplary embodiment of the present invention;

[0027] Figure 4 A third structural schematic diagram of a surface-mount electronic ceramic chip according to an exemplary embodiment of the present invention;

[0028] Figure 5 It is a schematic structural diagram of a deposited electrode metal material according to an exemplary embodiment of the present invention;

[0029] Reference numerals: 1 - first electrode, 2 - second electrode; 3 - ceramic body, 11 - first lead-out electrode, 12 - second lead-out electrode, 4 - partition. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with test examples and specific implementation methods. However, this should not be understood as the scope of the above subject matter of the present invention being limited to the following embodiments, and all technologies realized based on the content of the present invention belong to the scope of the present invention.

[0031] Example 1

[0032] Figure 1 、 Figure 2The surface-mount electronic ceramic chip of the exemplary embodiment of the present invention is shown, comprising: an electrode group, the electrode group comprising: a first electrode 1 and a second electrode 2; and further comprising: a ceramic body 3;

[0033] The ceramic body 3 has an upper and lower end surface and a side surface between the upper and lower end surfaces, the side surface at least includes a first side surface and a second side surface, the first electrode 1 covers a portion of the upper end surface and at least a portion of the first side surface, and the second electrode 2 covers a portion of the lower end surface and at least a portion of the second side surface; wherein the first electrode 1 covered on the first side surface is used to connect with the corresponding first extraction electrode 11, and the second electrode 2 covered on the second side surface is used to connect with the corresponding second extraction electrode 22;

[0034] The first electrode 1 and the second electrode 2 are formed by one-time processing, and the thickness of the first electrode 1 and the second electrode 2 are uniform.

[0035] It is understandable that in the prior art, an electrode group is formed on the surface of a ceramic body by mixing multiple processes and stacking multiple layers. However, the first electrode and the second electrode formed may be processed at different times and by different means, which may cause local over-oxidation and structural defects in the electrodes during processing and storage, affecting the conductivity of the electrodes, especially the ability to withstand large currents and high-energy pulses.

[0036] Therefore, in this embodiment, the first electrode and the second electrode are formed in one process, which can ensure that there will be no oxidation and structural dislocation on any cross section of the electrode. At this time, the first electrode or the second electrode is uniform on its corresponding end face and side face; on this basis, by integrally forming the first electrode and the second electrode with uniform thickness, the conductivity of the electrode group on any cross section can be the same, and no local hot spots will appear; therefore, the surface-mount electronic ceramic chip provided in this application has better consistency and density. ， Effectively improve the electrical performance of single-layer SMD electronic ceramic chips. Only by connecting the lead-out electrode to the electrode on the side of the ceramic body, without extending to the end electrode of the ceramic body, large current and high energy pulses can be transmitted to the corresponding end electrode, which is particularly suitable for surge absorption components such as varistors. At the same time, it is easy to parallel stack ceramic chips to form multi-layer SMD components.

[0037] Example 2

[0038] In one possible implementation, Figures 1 to 3 As shown, the ceramic body 3 is a rectangular hexahedron with a length of L, a width of W, and a height (thickness) of H. Among them, L*W is the end face of the ceramic body, and W*H is the side face of the ceramic body.

[0039] In this embodiment, by configuring the ceramic body as a rectangular hexahedron and extending the upper and lower end surface electrodes to the first and second side surfaces respectively, the electrodes are changed in direction and turned at a 90-degree angle, so that the overlapping area of ​​the projections of the first electrode and the second electrode on the upper and lower end surfaces is maximized; the overlapping electrode area on the upper and lower end surfaces is the effective electrode area of ​​the electronic ceramic component, which is closely related to the electrical parameters of the electronic ceramic component, for example, it is proportional to the flow rate of the varistor and the capacitance of the capacitor. Pursuing a larger proportion of the effective electrode area on the ceramic body can improve the electrical parameters of the component and reduce the external dimensions of the component, which is of great significance.

[0040] In a possible implementation, the thickness of the first electrode 1 and the second electrode 2 is 2 micrometers to 15 micrometers;

[0041] The nominal thickness error rate of the first electrode 1 and the second electrode 2 does not exceed a preset value, and the preset value ranges from [-15%, 15%].

[0042] Specifically, taking the first electrode with a nominal thickness of 5 microns and an error rate of plus or minus 15% as an example, the absolute value of the 15% error corresponding to 5um is 0.75um, that is, the overall thickness of the first electrode of this embodiment will be within the range of "5um±0.75um". Accordingly, the overall thickness of the first electrode is uniform.

[0043] In a possible implementation, chamfers R are provided at the corners of the end faces and side faces of the first electrode 1 and the second electrode 2 for achieving a smooth transition.

[0044] In this embodiment, chamfers R for achieving smooth transition are provided at the corners of the end faces and side faces of the electrode, thereby further ensuring the uniformity of the thickness of the electrode.

[0045] In a possible implementation, the preset value is [-8%, 8%].

[0046] Specifically, taking the first electrode with a nominal thickness of 5um and an error rate of plus or minus 8% as an example, the absolute value of the 8% error corresponding to 5um is 0.4um, that is, the overall thickness of the first electrode in this embodiment will be within the range of "5um±0.4um", accordingly, the overall thickness of the first electrode is uniform.

[0047] It is understandable that any processing technology will have certain errors during the processing. Considering the relationship between processing accuracy, the preset value is preferably set to [-8%, 8%].

[0048] In a possible implementation, the first electrode 1 and the second electrode 2 are formed by a sputtering process.

[0049] In one possible implementation, Figure 4As shown, there is a partition 4 between the first electrode 1 and the second electrode 2; the partition is located at the edge position of the upper end surface of the ceramic body, and another partition is provided at the edge position of the lower end surface in the diagonal direction.

[0050] In this embodiment, the partition is arranged at the edge of the electrode end surface, so that the effective electrode area of ​​the surface-mount electronic ceramic chip can be maximized, and the practicality is enhanced.

[0051] In a possible implementation, the surface-mount electronic ceramic chip is a varistor chip, a capacitor chip or a thermistor chip.

[0052] In summary, the surface mount electronic ceramic chip provided in this embodiment has the following advantages:

[0053] 1. Extend the electrodes on the upper and lower end surfaces to the first and second side surfaces respectively, and change the direction of the electrodes. Under the premise of turning at a 90-degree angle, since the partition 4 is located at the edge of the ceramic body, the overlapping area of ​​the projections of the first electrode and the second electrode on the upper and lower end surfaces is the largest; the overlapping electrode area on the upper and lower end surfaces is the effective electrode area of ​​the electronic ceramic component, which is closely related to the electrical parameters of the electronic ceramic component, such as being proportional to the flow rate of the varistor and the capacitance of the capacitor. Pursuing a larger proportion of the effective electrode area on the ceramic body can improve the electrical parameters of the component and reduce the external dimensions of the component, which is of great significance;

[0054] 2. The first electrode and the second electrode are formed in one process and have uniform thickness. Therefore, the first electrode covering the upper end face and the first side face (the second electrode on the lower end face and the second side face is similar) has the following characteristics: 1). The processing technology is simpler and the cost is lower than multiple processing. 2). It is made of the same conductive material. 3). It is made as a whole at the same time, with no joints or breakpoints in the middle, and there is no local over-oxidation of the electrode during processing and storage due to processing at different times and by different means; therefore, there will be no oxidation and structural dislocation on any section of the electrode, which can be understood as the first electrode being homogeneous on the upper end face and the first side face; coupled with the uniform thickness of the electrode, its conductivity is the same on any cross section, and there will be no local over-hot spots. This feature is very important for electronic ceramic components such as varistors, because they are often subjected to large currents and high-energy surges; local hot spot defects in the components will become quality risks and seriously affect the service life of the components. At the same time, because the electrodes provided in this embodiment have the characteristic of uniform conductivity, it is only necessary to limit the connection area of ​​the lead-out electrode to the side of the ceramic body. It is not necessary to connect the lead-out electrode to the upper and lower end surfaces of the ceramic body to achieve the normal transmission of large currents and high energy, thereby ensuring the normal function of such electronic ceramic components. Since the side of the ceramic body has been defined as the connection area with the lead-out electrode, the following benefits will be brought about: 1. The size of the lead-out electrode is reduced, the graphic structure of the lead-out electrode is simplified, and the cost is reduced. 2. The connection between the ceramic body and the lead-out electrode is simpler, takes up less space, and is conducive to the miniaturization of the component.

[0055] 3. It is only necessary to design the lead-out electrode with fixed positioning and connection functions, so that multiple ceramic bodies can be easily overlapped and connected in parallel to increase the electrical parameters exponentially.

[0056] Example 3

[0057] Another aspect of the present invention provides a method for manufacturing the surface-mount electronic ceramic chip described in Example 1 or 2, the method comprising: in a vacuum environment, using a double-sided sputtering process to sputter once to generate the first electrode 1 and the second electrode 2 of the surface-mount electronic ceramic chip; or, using two single-sided sputtering processes to sputter separately to generate the first electrode 1 and the second electrode 2 of the surface-mount electronic ceramic chip, and the thickness of the first electrode 1 and the second electrode 2 are uniform.

[0058] In this embodiment, the first electrode or the second electrode is uniformly deposited at one time by vacuum sputtering technology, ensuring that the electrode group formed on the three-dimensional ceramic body has better consistency and density. ， It effectively improves the electrical performance of single-layer SMD electronic ceramic chips, and is easy to stack ceramic chips in parallel to form multi-layer SMD components.

[0059] In a possible implementation, the thickness of the first electrode 1 and the second electrode 2 is 2 um to 15 um, and the nominal thickness error rate of the first electrode (1) and the second electrode (2) does not exceed a preset value, and the preset value ranges from [-15%, 15%].

[0060] In a possible implementation, the preset value ranges from [-8%, 8%]

[0061] In a possible implementation, the method for manufacturing a surface-mount electronic ceramic chip further includes:

[0062] A sputtering mask shielding process is used to provide a partition 4 between the first electrode and the second electrode; or a grinding or cutting process is used to remove the deposited metal layer on the surface of the ceramic body 3 between the first electrode 1 and the second electrode 2 to provide a partition 4 between the first electrode 1 and the second electrode 2.

[0063] Example 4

[0064] Another aspect of the present invention provides a sputtering electrode manufacturing system for surface-mount electronic ceramic chips, which uses a fixture and a mask with a specific inclination angle to achieve simultaneous and uniform vacuum sputtering coating of the end face and side face of any electrode of a ceramic body to form an electrode surface with uniform thickness.

[0065] like Figure 5 As shown, the fixture and mask with a specific inclination angle are used to make the ceramic body 3 to be sputtered form a certain angle with the deposition direction of the electrode metal material.

[0066] In this embodiment, a specific fixture and mask are set in the vacuum sputtering coating process implemented by the system so that the ceramic body 3 to be sputtered forms an angle with the deposition direction of the electrode material, so that the adjacent end faces and side faces of the ceramic body 3 are uniformly deposited at one time to form the first electrode or the second electrode.

[0067] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A surface-mount electronic ceramic chip for multi-layer stacking, comprising: A ceramic body and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body, and is characterized in that the electrode group comprises: a first electrode (1) and a second electrode (2); The ceramic body (3) has an upper and lower end surface and side surfaces between the upper and lower end surfaces, the side surfaces at least including a first side surface and a second side surface, the first electrode (1) covers a portion of the upper end surface and at least a portion of the first side surface, and the second electrode (2) covers a portion of the lower end surface and at least a portion of the second side surface; wherein the first electrode covered on the first side surface is used to connect to the corresponding first extraction electrode, and the second electrode covered on the second side surface is used to connect to the corresponding second extraction electrode; The first electrode (1) and the second electrode (2) are formed by one-step processing, and the thickness of the first electrode (1) and the second electrode (2) are uniform.

2. The surface-mount electronic ceramic chip according to claim 1, characterized in that: The thickness of the first electrode (1) and the second electrode (2) is 2 um to 15 um. ； The nominal thickness error rate of the first electrode (1) and the nominal thickness error rate of the second electrode (2) do not exceed a preset value, and the preset value ranges from [-15%, 15%].

3. The surface-mount electronic ceramic chip according to claim 2, characterized in that: The preset value ranges from [-8%, 8%].

4. The surface-mount electronic ceramic chip according to claim 2, characterized in that: The first electrode (1) and the second electrode (2) are formed by a sputtering process.

5. The surface-mount electronic ceramic chip according to claim 1, characterized in that: A partition (4) is provided between the first electrode (1) and the second electrode (2), wherein one partition (4) is located at an edge position on the upper end surface of the ceramic body, and another partition (4) is provided at an edge position on the lower end surface in the diagonal direction.

6. The surface mount electronic ceramic chip according to any one of claims 1 to 5, characterized in that: The electronic ceramic chip is a varistor chip, a capacitor chip or a thermistor chip.

7. A method for manufacturing a surface mount electronic ceramic chip, the surface mount electronic ceramic chip comprising: A ceramic body (3) and an electrode group, wherein the electrode group is arranged on the outer surface of the ceramic body (3), and is characterized in that the electrode group comprises: a first electrode (1) and a second electrode (2); The ceramic body (3) has an upper and lower end surface and side surfaces between the upper and lower end surfaces, the side surfaces at least including a first side surface and a second side surface, the first electrode (1) covers a portion of the upper end surface and at least a portion of the first side surface, and the second electrode (2) covers a portion of the lower end surface and at least a portion of the second side surface; wherein the first electrode covered on the first side surface is used to connect to the corresponding first extraction electrode, and the second electrode covered on the second side surface is used to connect to the corresponding second extraction electrode; The method comprises: in a vacuum environment, using a double-sided sputtering process to sputter once to generate a first electrode (1) and a second electrode (2) of the surface-mount electronic ceramic chip; or using single-sided sputtering twice to sputter respectively to generate the first electrode (1) and the second electrode (2) of the surface-mount electronic ceramic chip, wherein the thickness of the first electrode (1) and the second electrode (2) are uniform.

8. The method for manufacturing a surface mount electronic ceramic chip according to claim 7, characterized in that: The thickness of the first electrode (1) and the second electrode (2) is 2 um to 15 um, and the nominal thickness error rate of the first electrode (1) and the nominal thickness error rate of the second electrode (2) do not exceed a preset value, and the preset value ranges from [-15%, 15%].

9. The method for manufacturing a surface mount electronic ceramic chip according to claim 7, characterized in that: The method further comprises: using a sputtering mask shielding process to provide a partition (4) between the first electrode (1) and the second electrode (2); or using a grinding or cutting process to remove the deposited metal layer on the surface of the ceramic body (3) to provide a partition (4) between the first electrode (1) and the second electrode (2).

10. A surface-mount electronic ceramic chip sputtering electrode manufacturing system, characterized in that: The system adopts a fixture and a mask plate with a specific inclination angle to realize simultaneous and uniform vacuum sputtering coating of the end face and side face of any electrode of the ceramic body, so as to form an electrode surface with uniform thickness.

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