Semiconductor device and method of making and using dummy vias to reduce shorts between solder bumps

Abstract

A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die to form a reconstituted wafer. A first insulating layer is formed over the reconstituted wafer. A first dummy opening is formed in the first insulating layer. A first conductive layer is formed on the first insulating layer, including a first contact pad over the first dummy opening.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for making and using dummy vias to reduce short circuits between solder bumps. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide variety of functions such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are constantly striving to manufacture smaller semiconductor devices to meet the needs of electronic device manufacturers and consumers alike. As the size of semiconductor devices decreases, the density of interconnect bumps on semiconductor devices increases. The smaller pitch between bumps increases the vulnerability of the bumps to short circuits. Bumps that are close to each other may flow back into each other during manufacturing, causing undesirable short circuits between device terminals.

[0004] Figure 1a An example of two adjacent solder bumps 50a and 50b is shown. Bumps 50a and 50b are formed over substrate 60, where a redistributed interconnect structure is formed by insulating layer 62, conductive layer 64, and insulating layer 66. Openings are formed in insulating layer 66 to expose contact pads of conductive layer 64. Bumps 50a and 50b are appropriately reflowed onto their respective contact pads. However, Figure 1b Two adjacent bumps are shown, which have inadvertently and undesirably flowed back together into bump 70 , thus causing a short circuit.

[0005] One way short circuits occur is that adjacent bumps may roll toward each other when initially placed as solder balls on conductive layer 64 in openings of insulating layer 66. The openings of insulating layer 64 do not provide sufficient topology to hold the balls in place prior to reflow. Solder balls can roll out of the openings in insulating layer 64, or can remain within the insulating layer openings but roll close enough to reflow into each other. Therefore, there is a need for semiconductor devices and methods that reduce short circuits between adjacent solder bumps. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1a and 1b The diagram illustrates a short circuit between adjacent solder bumps;

[0007] Figure 2a-2cillustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0008] Figure 3a-3e A process for forming a semiconductor package having a reconstituted wafer and a built-up interconnect structure is illustrated;

[0009] Figure 4a-4h The process of forming a stacked interconnect structure with dummy vias and additional capture pads to reduce short circuits is illustrated;

[0010] Figures 5a-5f A second embodiment of forming a build-up interconnect structure with dummy vias and capture pads is illustrated;

[0011] Figure 6a-6c illustrates an embodiment of a dummy via formed below a redistribution layer contact pad;

[0012] Figures 7a-7d illustrates forming virtual vias at different heights of a build-up interconnect structure stack;

[0013] Figure 8a-8c illustrates the option of embodiments having different pitches in different areas of a device or reconstituted wafer; and

[0014] Figure 9a and 9b The diagram illustrates the integration of a semiconductor package into an electronic device. DETAILED DESCRIPTION

[0015] In the following description with reference to the figures, the present invention is described in one or more embodiments, wherein the same numerals represent the same or similar elements. Although the present invention is described with respect to the best mode for achieving the purpose of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same reference numerals in the figures have functions similar to each other. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0016] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of electrical current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit function.

[0017] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of ​​the wafer (called saw road or scribe line). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed above the semiconductor die are connected to the contact pads in the semiconductor package. Electrical connections can be made with conductive layers, bumps, columnar bumps, conductive glue, or wirebonds. Encapsulants or other molding materials are deposited above the semiconductor package to provide physical support and electrical isolation. The completed semiconductor package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0018] Figure 2a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0019] Figure 2bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed on or within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, power devices, or other signal processing circuits. The semiconductor die 104 may also include integrated passive devices (IPDs) for RF signal processing, such as inductors, capacitors, and resistors.

[0020] Conductive layer 112 is formed over active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0021] A passivation layer 114 is formed over the active surface 110. The passivation layer 114 comprises one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), photosensitive polyimide (PSPI), benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The passivation layer 114 may be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering, or thermal oxidation. The passivation layer 114 provides a protective coating for the active surface 110 and the contact pads 112 during subsequent handling and processing. Any of the materials or methods described for the passivation layer 114 may be used to form any of the insulating or passivation layers mentioned below.

[0022] exist Figure 2c 1 , semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested to identify known good dies (KGD) or known good units (KGU) after singulation.

[0023] Figure 3a-3e The process of forming an embedded wafer level ball grid array (eWLB) semiconductor package is illustrated. Figure 3aIn the embodiment of the present invention, a plurality of semiconductor dies 104 are picked up and placed on a carrier 120, which contains a sacrificial base material, such as silicon, a polymer, beryllium oxide, glass, or other suitable low-cost rigid materials for structural support. An interface layer or double-sided tape 122 is formed or arranged above the carrier 120 as a temporary bonding film, a thermal release layer, or a UV release layer. To simplify the description, the formed packages each include a single semiconductor die 104 and do not include other components. In other embodiments, a much more complex package can be formed with multiple semiconductor dies, additional discrete active or passive components, or any other desired electrical components. Although the carrier 120 is illustrated as being large enough to manufacture three devices together, a typical carrier can handle hundreds or thousands of devices together.

[0024] exist Figure 3b In the process, sealant or molding compound 124 is deposited over and around semiconductor die 104 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating, or other suitable applicators. Encapsulant 124 can be a liquid or particulate polymer composite material, such as epoxy resin, epoxy acrylate, or another suitable polymer, with or without a suitable filler. Encapsulant 124 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

[0025] The combination of semiconductor die 104 and encapsulant 124 forms a reconstituted wafer 126. The term reconstituted wafer indicates that reconstituted wafer 126 can be analogized to semiconductor wafer 100 from which semiconductor die 104 came. In a sense, semiconductor wafer 100 has been reconstituted, wherein semiconductor die 104 has been further expanded to facilitate forming a fan-out interconnect structure over active surface 110.

[0026] exist Figure 3c In the embodiment of the present invention, reconstituted wafer 126 is flipped over and a build-up interconnect structure 128 is formed over reconstituted wafer 126. It is called a build-up interconnect structure 128 because the interconnect structure is formed by building up conductive and insulating layers on top of a substrate, such as reconstituted wafer 126. Insulating layer 131 is formed on reconstituted wafer 126 using the methods and materials described above for passivation layer 114. Openings are formed through insulating layer 131 and passivation layer 114 to expose contact pads 112 of semiconductor die 104.

[0027] Conductive layer 134 is formed over insulating layer 131 and into openings in insulating layer 131 and passivation layer 114 to physically contact and electrically connect to contact pad 112. Conductive layer 134 is patterned using a mask, photolithography, chemical etching, laser ablation, jet printing, or another suitable method to form a redistribution layer (RDL) that fans out from contact pad 112. In other embodiments, conductive layer 112 forms a fan-in interconnect structure. Each conductive trace of conductive layer 134 has one end at contact pad 112 and has a contact pad or capture pad formed at its opposite end.

[0028] As described for insulating layer 131, another insulating layer 136 is formed over conductive layer 134. Openings are formed through insulating layer 136 to expose contact pads of conductive layer 134. Any number of additional insulating and conductive layers may be interleaved over conductive layer 134 and insulating layer 136 to increase RDL layers and allow for more complex signal routing. To simplify the description of the eWLB concept, only a single RDL layer is illustrated. Additional details of using multiple RDL layers are illustrated below.

[0029] Conductive bump material is deposited over conductive layer 134 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 134 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form bump 140. In one embodiment, bump 140 is formed over an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. Bump 140 can also be compression bonded or thermocompressed bonded to conductive layer 134.

[0030] exist Figure 3d In the embodiment of the present invention, a saw blade or laser cutting tool 152 is used to singulate the encapsulant 124 and the build-up interconnect structure 128 into individual semiconductor packages 150 . Figure 3e A completed semiconductor package 150 is shown. The contact pads 112 are electrically connected to the solder bumps 140 through the conductive layer 134 and any additional RDL layers that are optionally formed. Some of the bumps 140 are formed over the encapsulant 124, which exacerbates the problem of shorting solder bumps.

[0031] Figure 4a-4h One specific method of forming an RDL layer over the encapsulant 124 that fans out from the contact pads 112 using dummy openings to reduce shorting solder bumps is illustrated. Figure 4a-4h The RDL method shown in Figure 3a-3eThe eWLB package shown in is available. Figure 4a Insulating layer 160 is formed over reconstituted wafer 126 as described above with respect to insulating layer 131. Insulating layer 160 completely covers reconstituted wafer 126.

[0032] exist Figure 4b In the embodiment of the present invention, openings 162 and 164 are formed through insulating layer 160. Openings 162-164 are formed by photolithography, laser ablation, chemical etching or another suitable process. The insulating layer openings mentioned above and below may have openings formed using the same process. Opening 162 is a via that exposes contact pads 112 of semiconductor die 104 for subsequent electrical interconnection. Opening 164 is a virtual opening that only exposes sealant 124. In other embodiments, opening 164 is formed only partially through insulating layer 160. Virtual opening means that the opening is not required for electrical connection through the insulating layer, but rather for some other purpose. Here and in most of the following embodiments, virtual openings are formed for the purpose of modifying the shape of the overlying conductive layer.

[0033] exist Figure 4c 164. In the embodiment of the present invention, as described above for conductive layer 134, conductive layer 166 is formed over insulating layer 160. Conductive layer 166 is patterned to form a conductive trace extending between openings 162 and 164. Conductive layer 166 extends into opening 162 to form a conductive via 168 that physically and electrically contacts contact pad 112. Conductive layer 166 extends into opening 164 to form a recess 169 in, on, or above opening 164. Conductive layer 166 is conformally deposited so that the top surface of the conductive layer is recessed or recessed into opening 164. Virtual opening 164 has changed the shape of conductive layer 166 from having a flat contact pad to having a recessed contact pad at the end of the conductive trace opposite to contact pad 112. Conductive layer 166 forms a circular or other shaped contact pad at recess 169. The footprint of the contact pad of recess 169 is larger than and completely surrounds the footprint of opening 164.

[0034] exist Figure 4d 1 , an insulating layer 170 is formed over insulating layer 160 and conductive layer 166, as described above for insulating layer 160. An opening 172 is formed through insulating layer 170 over recess 169. The footprint of opening 172 is larger than opening 164, so that recess 169 is fully exposed within opening 172. The footprint of opening 172 is smaller than the contact pad of conductive layer 166, so that the edge of the contact pad is not exposed within opening 172.

[0035] exist Figure 4eIn the embodiment, a conductive layer is formed over insulating layer 170 and patterned into contact pads 176. A plurality of contact pads are formed, but Figure 4e Only a single contact pad 176 is shown in the limited partial cross-section of FIG. The contact pad 176 is conformally formed so that the top surface of the contact pad conforms to the combined topology of the underlying opening 172 and the recess 169. The contact pad 176 is generally circular or approximately circular and has a larger footprint than the opening 172 so that the contact pad extends outwardly onto the top surface of the insulating layer 170 surrounding the opening 172.

[0036] exist Figure 4f In the embodiment of the present invention, insulating layer 180 is formed over insulating layer 170 and contact pad 176, as described above with respect to insulating layer 170. An opening 182 is formed through insulating layer 180 over contact pad 176. The footprint of opening 182 is larger than opening 172 so that the recessed portion of contact pad 176 is fully exposed within opening 182, while being smaller than the contact pad so that the edge of the contact pad is not exposed within opening 182.

[0037] Contact pad 176 is the contact pad that will eventually have a solder bump mechanically attached thereto. Figure 4g As shown in , the process of protruding contact pad 176 usually starts with setting solder ball 186 onto the contact pad. Solder ball 186 is a loose ball that is not physically attached to contact pad 176, and is therefore able to roll around. Virtual opening 164 in insulating layer 160 causes contact pad 176 to have a deep groove, which keeps ball 186 captured above the contact pad, rather than allowing the ball to roll to other places on reconstructed wafer 126, and possibly short circuit with another solder ball. In some embodiments, solder ball 186 stays on the ring formed by groove 169 or opening 172, which helps to eliminate the possibility that solder ball can build momentum by rolling on a flat contact pad. In other embodiments, ball 186 stays on the flat bottom surface of contact pad 176, and the topology provided by groove 169 and opening 172 below reduces the possibility of bump rolling off the contact pad. Being restricted to rolling within the area of ​​recess 169 rather than within the entire contact pad reduces the likelihood that a bump will roll close enough to another bump to reflow with the other bumps.

[0038] exist Figure 4h 1 , ball 186 successfully reflows into bump 188 which is connected only to contact pad 176. The recess caused by dummy opening 164 and opening 172 holds the solder ball in place for proper reflow.

[0039] Figures 5a-5f It shows that it can be combined with Figure 4a-4h Another RDL contact pad topology used by the topology. Figure 5aThe end of another conductive trace 166' of the conductive layer 166 is shown without a virtual opening formed in the insulating layer 160. The end of the conductive trace 166' is a contact pad of a circular or other shape. Figure 5b In FIG. 1 , the insulating layer 170 is formed with an opening 172 above the contact pad of the conductive trace 166 ′. Figure 5b , conductive trace 166' is flat under opening 172, rather than Figure 4d It is concave like that.

[0040] exist Figure 5c In the embodiment, contact pad 176' is formed on the contact pad of conductive trace 166' above insulating layer 170 and within opening 172. Contact pad 176' follows the contour of opening 172, but is flat in the middle, unlike Figure 4e The contact pad 176 also follows the contour of the underlying virtual opening 164. Figure 5d In FIG. 1 , insulating layer 180 has an opening 182 formed over contact pad 176 ′.

[0041] Even though there is no virtual opening 164 through insulating layer 160, opening 172 can still be considered a virtual opening because opening 172 is not strictly necessary and is not typically used in the prior art. In the prior art, the contact pad would consist only of conductive layer 176, which remains as a flat contact pad exposed for the bump. There would be no opening in the insulating layer below conductive layer 176, and the contact pad presented to the bump would simply be a flat conductive layer with only an opening in the insulating layer above the contact pad to hold the solder ball in place. Conductive layer 176 would have conductive traces extending away from contact pad 176 or 176', rather than the conductive traces of the underlying RDL layer 166.

[0042] Adding opening 172 below contact pad 176' creates a groove in the contact pad, which helps prevent ball 186 from rolling out. Figure 5e In the location. Figure 5f After reflow in , bump 188 ′ remains physically isolated from surrounding bumps because solder ball 186 is held in place by the recess in contact pad 176 ′.

[0043] Contact pad 176' having an opening in insulating layer 170 only underneath the contact pad does not create a recess as deep as contact pad 176 which also has dummy opening 164 in insulating layer 160. Figure 4h Compared to the contact pad 176 having a deeper overall recess, Figure 5fContact pad 176' in the embodiment of the present invention has an overall shallower groove which reduces the protection provided against solder bump shorting. The tradeoff is that contact pad 176' is simpler to manufacture. In one embodiment, contact pads 176 and 176' are used in combination, wherein dummy openings 164 are formed only under contact pads for signal transmission, and no dummy openings 164 are formed under contact pads for power and ground traces. Bumps 188 for power and ground terminals are typically grouped together so that shorting has less negative impact because most adjacent bumps are already shorted by the underlying conductive layer.

[0044] Figure 6a-6c Additional contact pad embodiments are illustrated where a dummy opening is below the contact pad, but there is no separate underlying RDL layer, where another contact pad is connected to the top contact pad. Figure 6a-6c Each of the sectional views shows a portion of an encapsulant 124 having three insulating layers 200, 202, and 204 formed as part of a build-up interconnect structure above a reconstructed wafer. Two conductive redistribution layers (RDLs) are formed, a first RDL layer 206 on insulating layer 200 and a second RDL layer 208 on insulating layer 202. In the other cross-sectional views, the redistribution layers form an extensive RDL pattern, while in Figure 6a-6c Only a small portion of the RDL and a pair of contact pads are shown.

[0045] Figure 6a The contact pad 210, Figure 6b The contact pads 210' and Figure 6c The contact pads 210″ in FIG. 1 are all formed as part of a second RDL layer 208 on the insulating layer 202. Each contact pad is connected to somewhere else on the reconstructed wafer through the RDL layer 208, which extends laterally from the illustrated contact pad across the insulating layer 202. Like the contact pads 176 and 176′, the contact pads 210, 210′, and 210″ do not have another contact pad that is part of the first RDL layer 206.

[0046] exist Figure 6a-6c In each, a stacked interconnect structure is formed as described above. Insulating layer 200 is first formed over the reconstructed wafer. If desired, dummy openings 212 are formed in insulating layer 200 below where contact pads are to be formed. A first RDL layer 206 is formed on insulating layer 200. The RDL pattern on insulating layer 200 does not extend to where contact pads 210, 210' or 210" are to be formed. Insulating layer 202 is formed on insulating layer 200 and RDL layer 206. If desired, dummy openings 214 are formed in insulating layer 202 below where contact pads are to be formed.

[0047] A second RDL layer 208 is formed on the insulating layer 202. The second RDL layer 208 includes contact pads 210, 210', 210" or any combination thereof, and conductive traces interconnecting the contact pads to the first RDL layer 206. The insulating layer 204 is formed over the RDL layer 208 and the contact pads 210, 210', and 210". Openings 218 are formed in the insulating layer 204 over the contact pads 210, 210', and 210" for bumps. A single device may use a combination of the contact pads 210, 210', and 210", or all of the contact pads may be the same design for each device.

[0048] The contact pads 210 , 210 ′, and 210 ″ are each recessed due to the formation of a dummy opening below the contact pad. Figure 6a Contact pads 210 are shown with dummy openings 214 formed through insulating layer 202 beneath each contact pad, but without dummy openings 212 formed through insulating layer 200 . Figure 6b The contact pad 210 ′ is shown with a dummy opening 212 formed through the insulating layer 200 , but without a dummy opening 214 formed through the insulating layer 202 . Figure 6c Contact pads 210" are shown with both dummy openings 212 and dummy openings 214 formed beneath each contact pad. In either of the illustrated cases, the recessed contact pads hold the solder balls in place during reflow so that solder bumps 220 can be formed with a reduced risk of shorting between bumps.

[0049] Figure 4h , 5f 6a-6c all show contact pads formed as part of the second RDL layer 208 above the encapsulant 124, but each of those contact pad topologies can be used at any RDL level. When more complex signal routing is required, additional RDL layers can be formed below the layer used for the contact pads, and then the same contact pad RDL layer can be formed above it. Figure 7a A single additional RDL layer is shown, where an insulating layer 230 and an RDL layer 232 are formed from Figure 6a The insulating layers 200 - 204 and the RDL layers 206 - 208 are below.

[0050] In addition to forming an additional RDL layer over the encapsulant 124 and under the insulating layer 200, Figure 7a and Figure 6a The insulating layer 202 with the dummy opening 214 is now the third insulating layer instead of the second insulating layer. The contact pad 210 is formed as part of the third RDL layer in the stack instead of the second RDL layer.

[0051] Figure 7b Contact pad 210 is shown formed as part of a fourth RDL layer in a stack having two additional RDL layers formed below insulating layer 200 , including insulating layer 230 , RDL layer 232 , insulating layer 234 , and RDL layer 236 . Figure 7c and 7d shows the formation of the upper RDL layer from Figure 6b The contact pad 210'. Figure 7c In the embodiment, an additional RDL layer 232 is formed under the insulating layer 200. Figure 7c In the embodiment shown in FIG. 2 , two additional RDL layers 232 and 236 are formed under the insulating layer 200. Any of the previously illustrated or described embodiments may be formed at any RDL layer.

[0052] In all of the above embodiments, any dummy openings have been formed concentric with the overlying solder bumps.In some embodiments, the spacing between bumps may not be consistent across the entire reconstituted wafer. Figure 8a An embodiment with a reconstituted wafer 230 is shown in which solder bumps 220 are formed in two groups 232. The bumps 220 have a smaller bump pitch within a group 232 than between groups. The gaps 233 between bumps 220 within a group 232 are approximately half of the gaps 234 between bumps of adjacent groups. The gaps 234 between different groups 232 can be within a single unit or across the saw streets of the reconstituted wafer 230.

[0053] To provide more benefit where the bump pitch is smallest (e.g., within group 232), Figure 8b Virtual openings 212 and / or 214 are shown formed off-center within opening 218. The contact pad recesses caused by the virtual openings are formed further away from the closer adjacent contact pads. Virtual openings 212 and 214 have a more consistent pitch width across the reconstructed wafer compared to final bumps 220. When solder balls are placed on the contact pads, the balls are held within the recesses at a more consistent pitch across the entire reconstructed wafer 230.

[0054] Another option to reduce the likelihood of solder balls rolling into each other and shorting is to place solder balls that have already rolled toward each other in their grooves. Figure 8cVirtual openings 212 and 214 are shown formed concentrically with opening 218 in the top insulating layer. A solder ball 236 is placed onto the contact pad within the recess formed by the virtual openings. Ball 236 is placed on the flat bottom surface of the recess, against the ridge or edge of the bottom surface, toward the smaller gap 233. Placing ball 236 against the edge of the recess initially makes it more difficult for the balls to roll toward each other before reflow and shorting. The edges provided by openings 212 and 214 initially prevent solder ball 236 from rolling toward the smaller gap 233 and gathering momentum to escape the contact pad recess.

[0055] Figure 9a and 9b Integration of the semiconductor package described above (eg, semiconductor package 150 having any combination of the RDL and contact pad topologies described above) into a larger electronic device 300 is illustrated. Figure 9a A partial cross section of a semiconductor package 150 is shown mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300. Bumps 140 are reflowed onto a conductive layer 304 of the PCB 302 to physically attach and electrically connect the semiconductor package 150 to the PCB. In other embodiments, thermal compression or another suitable attachment and connection method is used. In some embodiments, an adhesive or underfill layer is used between the semiconductor package 150 and the PCB 302. The semiconductor die 104 is electrically coupled to the conductive layer 304 through the bumps 140 and the conductive layer 134.

[0056] Figure 9b An electronic device 300 is illustrated having a chip carrier substrate or PCB 302 with a plurality of semiconductor packages disposed on a surface of PCB 302, including semiconductor package 150. Electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0057] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASICs, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to facilitate installation into a more ergonomic and smaller device housing.

[0058] exist Figure 9b In the embodiment of the present invention, PCB 302 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed over the surface or within the layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 304 also provide power and ground connections to each semiconductor package.

[0059] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0060] For illustrative purposes, several types of first level packages are shown on PCB 302, including bond wire packages 346 and flip chips 348. In addition, several types of second level packages, including ball grid arrays (BGA) 350, bump chip carriers (BCC) 352, land grid arrays (LGA) 356, multi-chip modules (MCM) or SIP modules 358, quad flat no-lead packages (QFN) 360, quad flat packages 362, and embedded wafer level ball grid arrays (eWLB) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0061] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging styles and other electrical components can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0062] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing semiconductor dies; depositing an encapsulant over the semiconductor die to form a reconstituted wafer; forming a first insulating layer over the reconstituted wafer; forming a first dummy opening in the first insulating layer; and A first conductive layer is formed on the first insulating layer, the first conductive layer including a first contact pad over the first dummy opening.

2. The method according to claim 1, further comprising: forming a second insulating layer over the first conductive layer; forming an opening in the second insulating layer to expose the first contact pad; and A second contact pad is formed on the first contact pad and the second insulating layer.

3. The method according to claim 1, further comprising: forming a redistribution layer over the reconstituted wafer; and A first insulating layer is formed over the redistribution layer.

4. The method according to claim 1, further comprising: forming a second insulating layer over the first insulating layer; and A first conductive layer is formed over the second insulating layer. The method of claim 4 , further comprising forming a second dummy opening in a second insulating layer above the first dummy opening. The method of claim 1 , further comprising forming a first dummy opening off-center from the first contact pad.

7. A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a first insulating layer over the substrate; forming a first opening in the first insulating layer; and A first conductive layer including a first contact pad is formed over the first opening. The method according to claim 7 , further comprising forming a second insulating layer under the first insulating layer. 9 . The method of claim 7 , further comprising forming the first opening off-center from the first contact pad.

10. A semiconductor device comprising: substrate; forming a first insulating layer over the substrate; forming a first opening in the first insulating layer; and The first conductive layer includes a first contact pad formed above the first opening.

11. The semiconductor device according to claim 10, further comprising: a second insulating layer formed on the first conductive layer; a second opening formed in the second insulating layer over the first contact pad; and A second contact pad is formed on the first contact pad and the second insulating layer. 12 . The semiconductor device of claim 10 , further comprising a redistribution layer formed over the substrate, wherein the first insulating layer is formed over the redistribution layer. 13 . The semiconductor device according to claim 10 , further comprising a second insulating layer formed over the first insulating layer, wherein the first conductive layer is formed over the second insulating layer. 14 . The semiconductor device of claim 13 , further comprising a second opening formed in the second insulating layer above the first opening.

15. The semiconductor device according to claim 10, wherein The first opening is formed off-center with respect to the first contact pad.

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