Semiconductor device

Abstract

The invention relates to a semiconductor device. A semiconductor device according to an embodiment includes a semiconductor chip having a first MOSFET formed in a first region of a semiconductor substrate; a detection element formed in a second region within the first region; a source electrode formed over the first region and connected to a source of the first MOSFET; and a source electrode material arranged to cover the detection element and stitch-bonded to the source electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-148527 filed on September 13, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to semiconductor devices. Background Art

[0004] As is well known, when an abnormal current (overcurrent) passes through a power MOSFET, there is a detection element that protects the power MOSFET. Examples of such a detection element include a current detection element having a sense MOSFET, and a temperature detection element including a diode.

[0005] Patent document 1 discloses a technique related to the arrangement of a detection element in a power MOSFET. In patent document 1, a metal plate overlapping a source electrode includes a source connection portion connected to the source electrode and an extension portion extending toward a source terminal, and the source terminal is arranged on a short side of the source connection portion. In a plan view, the extension portion is arranged to overlap the detection element.

[0006] [Prior art documents]

[0007] [Patent document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2020-145219. Summary of the invention

[0009] The power MOSFET is composed of a plurality of unit transistor cells arranged in a matrix, and a source electrode formed on the main surface of the semiconductor substrate and a drain electrode formed on the back surface are common to the plurality of unit transistor cells. When an abnormal current (overcurrent) flows through the power MOSFET, it is known that the center portion of the semiconductor chip forming the power MOSFET is hotter than the edge portion, that is, a temperature difference occurs between the center portion and the edge portion of the semiconductor chip.

[0010] In Patent Document 1, the detection element is arranged at the edge portion of the semiconductor chip so as to overlap with the extension extending from the source electrode to the source terminal. When the detection element is arranged at the edge portion in this way, it takes several hundred μs for the detection element to react to the heat caused by the overcurrent and perform a cutoff operation due to the above-mentioned temperature difference. In a semiconductor device equipped with a power MOSFET, it is desired to improve the responsiveness of the detection element.

[0011] Other problems and novel features will be apparent from the description and drawings of this specification.

[0012] The semiconductor device according to the present embodiment includes a semiconductor chip, which includes: a first MOSFET, which is formed in a first region of a semiconductor substrate; a detection element, which is formed in a second region within the first region; a source electrode, which is formed above the first region and is electrically connected to the source of the first MOSFET; and a source electrode material, which is arranged to cover the detection element and is stitch-bonded to the source electrode.

[0013] The present disclosure can improve the responsiveness of a detection element of a semiconductor device equipped with a power MOSFET. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan perspective view showing a configuration example of the semiconductor device according to the first embodiment.

[0015] Figure 2 yes Figure 1 A cross-sectional view of the main part.

[0016] Figure 3 is shown along Figure 1 A photograph of a cross section of line II-II.

[0017] Figure 4 is shown along Figure 1 A photograph of a cross section of line II-II.

[0018] Figure 5 is a plan perspective view showing a configuration example of a semiconductor device according to a second embodiment.

[0019] Figure 6 is the explanation Figure 5 Graph showing the temperature difference-Ids (Vds=constant) characteristics of a semiconductor device in FIG.

[0020] Figure 7 is a circuit diagram showing a configuration example of a semiconductor device adopting a high-side configuration.

[0021] Figure 8 is a circuit diagram showing a configuration example of a semiconductor device adopting a low-side configuration.

[0022] Fig. 9 is a plan perspective view of a comparative example of a semiconductor device.

[0023] Fig.10 is along Fig. 9 Cross-sectional view of line XX in . DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Note that the accompanying drawings are simplified and the technical scope of the present disclosure should not be interpreted narrowly based on the description of these drawings. In addition, in each figure, the same elements are given the same reference numerals and redundant descriptions are omitted. Please note that for ease of explanation, each figure is not drawn to actual scale.

[0025] In the following embodiments, for convenience, the explanation is divided into multiple parts or embodiments when necessary. However, unless otherwise specified, they are not unrelated to each other, and one embodiment is related to another embodiment as part or all of a variation, application, detailed explanation, supplementary explanation, etc.

[0026] Furthermore, in the following embodiments, when referring to the number of elements, etc. (including number, value, amount, range, etc.), unless otherwise specified and it is fundamentally clear that it is limited to a specific number, it is not limited to the specific number and may be greater or less than the specific number.

[0027] Furthermore, unless specifically stated and when it is fundamentally clear that they are indispensable, in the following embodiments, components (including operation steps, etc.) are not necessarily essential. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., unless specifically stated and it is fundamentally clear that this is not the case, it includes shapes that are substantially similar or similar to the shape, etc. This applies to the above-mentioned quantities, etc. (including quantity, value, amount, range, etc.).

[0028] In the present disclosure, a field effect transistor is described as MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or MOS for short, but it includes not only an oxide film being used as a gate insulating film but also an insulating film other than an oxide film being used as a gate insulating film.

[0029] The embodiments relate to power semiconductor devices for driving loads such as motors, heaters, and lamps installed in automobiles, and semiconductor devices applied to industrial programmable logic controllers (PLCs). Such semiconductor devices use power MOSFETs and IGBTs (insulated gate bipolar transistors).

[0030] For example, the semiconductor device of the embodiment is applied to a driving circuit of a high-side configuration or a low-side configuration. Figure 7 1 is a circuit diagram showing a configuration example of a semiconductor device 1 adopting a high-side configuration. Figure 7As shown, the semiconductor device 1 includes an output transistor 3 and a body diode 4. The body diode 4 is provided between the source and the drain of the output transistor 3. Between a power supply terminal VBAT for providing a power supply voltage and a ground terminal GND for providing a ground voltage, the output transistor 3 and the load 2 are connected in series in this order. The output transistor 3 is provided between the power supply terminal VBAT and the load 2. That is, the output transistor 3 is used as a high-side switch.

[0031] Figure 8 1 is a circuit diagram showing a configuration example of a semiconductor device 1 adopting a low-side configuration. Figure 8 As shown, the semiconductor device 1 includes an output transistor 3 and a body diode 4. The body diode 4 is provided between the source and the drain of the output transistor 3. Between the power supply terminal VBAT and the ground terminal GND, the load 2 and the output transistor 3 are connected in series in this order. The output transistor 3 is provided between the load 2 and the ground terminal GND. That is, the output transistor 3 is used as a low-side switch.

[0032] These semiconductor devices are provided with a detection element for protecting the power MOSFET when an abnormal current (overcurrent) passes through the power MOSFET. First, a comparative example of a semiconductor device having a power MOSFET provided with a temperature detection element as a detection element will be described.

[0033] Fig. 9 is a plan view of a semiconductor device of a comparative example. Fig.10 yes Fig. 9 The cross-sectional view taken along line XX in FIG. Fig. 9 and Fig.10 As shown, the semiconductor device 1 of the comparative example mainly includes a semiconductor chip 10, a temperature detection element 11, and a metal plate 12. The semiconductor chip 10 is mounted on a main surface of a die pad 13 via an adhesive layer 14.

[0034] In the center of the main surface of the semiconductor chip 10 , a main MOS region (not shown) is provided, and at the edge, a temperature detection diode region serving as a temperature detection element 11 is provided.

[0035] The metal plate 12 is connected to a source pad (first source electrode, not shown) provided on the main MOS region via an adhesive layer 15. Fig. 9 In the example shown, the clip-shaped metal plate 12 is used as the source electrode material, and the source electrode material is connected to the source electrode of the power MOSFET. The adhesive layers 14 and 15 can be, for example, solder or silver paste. Thus, when the metal plate 12 is used, a bonding process is required to bond the metal plate 12 and the semiconductor chip 10 with the adhesive layer 15.

[0036] The metal plate 12 has a source connection portion 12a and an extension portion 12b, the extension portion including a protrusion and a lead connection portion. The metal plate 12 is connected to the source pad at the source connection portion and is connected to the source terminal at the lead connection portion. The protrusion between the source connection portion and the lead connection portion is positioned on the temperature detection element 11 and covers the metal plate 12.

[0037] The semiconductor chip 10, the metal plate 12 and the die pad 13 are covered with a sealing body 18. The sealing body 18 is composed of an insulating resin body (such as epoxy resin). The sealing body 18 is filled between the temperature detection element 11 on the semiconductor chip 10 and the protrusion of the metal plate 12, and they are electrically isolated by the insulating resin.

[0038] like Fig. 9 and Fig.10 As shown, the temperature detection element 11 is provided at the edge of the semiconductor chip 10. Fig. 9 There is a temperature difference between the point A (center of the semiconductor chip 10) and the point B (edge ​​of the semiconductor chip 10) shown, so the detection element needs several hundred μs to respond to the heat caused by the overcurrent and perform a cutoff operation. In a semiconductor device equipped with a power MOSFET, it is desirable to improve the responsiveness of the detection element. In addition, when the temperature detection element 11 is placed in the center of the semiconductor chip 10, an insulator needs to be provided between the metal plate 12 and the temperature detection element 11 to prevent a short circuit, thereby increasing the manufacturing process. Therefore, the inventors have designed the following configuration to solve these problems.

[0039] First embodiment

[0040] Figure 1 1 is a plan perspective view showing a configuration example of the semiconductor device 1 according to the first embodiment. Figure 1 As shown, the semiconductor device 1 is a SOP (Small Light Package) type semiconductor package. Figure 1 As shown, the semiconductor device 1 mainly includes a semiconductor chip 10 , a temperature detection element 11 and a ridge wire 20 .

[0041] The semiconductor chip 10 includes a main MOS region forming a power MOSFET, and a temperature detection diode region forming a temperature detection element 11. The power MOSFET is a transistor used for switching. Figure 7 and Figure 8As described above, when the on voltage is applied to the gate of the power MOSFET and the power MOSFET is turned on, current flows through the power MOSFET and the load 2 connected in series between the power supply terminal VBAT and the ground potential GND. On the other hand, if the off voltage is applied to the gate of the power MOSFET and the power MOSFET is turned off, current can be prevented from flowing through the power MOSFET and the load 2 connected in series.

[0042] In addition, the semiconductor chip 10 includes a source pad SP and a gate pad GP. The semiconductor device 1 is provided with a plurality of terminals used as external terminals. The plurality of terminals are electrically connected to the semiconductor chip 10. The plurality of terminals include a gate terminal GT, a source terminal ST, and a drain terminal DT. The plurality of terminals are composed of leads formed by processing a copper plate or a 42 alloy plate having a film thickness of about 250 μm into a desired shape. Figure 7 and Figure 8 As shown, the source terminal ST is a terminal for supplying current to the load 2.

[0043] exist Figure 1 In the example shown, a plurality of drain terminals DT connected to the drains of the power MOSFETs are arranged on the upper edge of the semiconductor device 1 .

[0044] A plurality of source terminals ST connected to sources of the power MOSFETs are arranged on the left side of a lower edge of the semiconductor device 1 , the lower edge facing an upper edge where the drain terminal DT is provided.

[0045] The gate terminal GT connected to the gate of the power MOSFET is arranged on the right side of the lower edge of the source terminal ST. The die pad DP and the plurality of drain terminals DT are formed integrally. The semiconductor chip 10 is mounted on the die pad DP via an adhesive layer 14. The gate terminal GT and the gate pad GP are connected by a wire 16. The wire 16 is made of, for example, a copper wire or a gold wire having a diameter of 30 to 50 μm. Additionally, instead of the wire 16, a metal ridge wire having a wider width than the wire 16 can also be used. The gate terminal GT is electrically connected to a drive circuit (not shown). The drive circuit controls the potential of the gate of the power MOSFET and controls the operation of the power MOSFET.

[0046] The ridge wire 20 is used as a source electrode material.

[0047] The ridge wire 20 is a strip-shaped electrode material made of a flexible aluminum foil having a thickness of about 150 to 250 μm. The ridge wire 20 is located on the source pad SP of the semiconductor chip 10. The ridge wire 20 electrically connects the source pad SP and the source terminal ST.

[0048] The ridge wire 20 is connected to the source terminal ST and the source pad SP by wire bonding. In the wire bonding, the tip of the ridge wire 20 held by a bonding tool (not shown) is connected to the center portion (first bonding point) of the source pad SP of the semiconductor device 1. Then, the ridge wire 20 is pulled, and its middle portion is connected to the end portion of the source pad SP (second bonding point). In addition, the ridge wire 20 is pulled and its middle portion is connected to the source terminal ST (third bonding point). Near the connection portion of the source terminal ST, the ridge wire 20 is cut, thereby ending one circle of wire bonding.

[0049] The connection between the ridge conductor 20 and the source pad SP or the source terminal ST is completed by stitch bonding. Specifically, the ridge conductor 20 is pressed against the source pad SP while applying ultrasonic vibration. As a result, the ridge conductor 20 is bonded to the source pad SP to form a stitch joint. Therefore, the embodiment performs the bonding of the ridge conductor 20 to the source pad SP and the source terminal ST by an ultrasonic bonding method, and a bonding process using solder or the like is not necessary. The stitch joint formed at the first bonding point is referred to as a first stitch joint 21a, the stitch joint formed at the second bonding point is referred to as a second stitch joint 21b, and the stitch joint formed at the third bonding point is referred to as a third stitch joint 21c.

[0050] The ridge conductor 20 between the first stitch joint 21a and the second stitch joint 21b is not bonded to the source pad SP, and there is a space between the ridge conductor 20 and the source pad SP. The ridge conductor 20 on this space is called the first protrusion 22a. In addition, the ridge conductor 20 between the second stitch joint 21b and the third stitch joint 21c is not bonded to the die pad DP, etc., and there is a space between the ridge conductor 20 and the die pad DP, etc. The ridge conductor 20 on this space is called the second protrusion 22b. In other words, the ridge conductor 20 includes the first stitch joint 21a, the second stitch joint 21b, the third stitch joint 21c, the first protrusion 22a, and the second protrusion 22b.

[0051] The area of ​​the first protrusion 22a facing the semiconductor chip 10 is a temperature diode area where the temperature detection element 11 is provided. The temperature detection element 11 is a temperature diode in which a plurality of diodes are connected in series. Figure 2 , the temperature detection element 11 will be described. Figure 2 is formed Figure 1 FIG. 1 is a cross-sectional view of an essential portion of the temperature detection element 11. FIG.

[0052] exist Figure 2In the example shown, an epitaxial wafer is used as a semiconductor substrate. The semiconductor substrate includes: a substrate body 30 made of, for example, n+ type single crystal silicon, into which n type impurities (such as arsenic (As)) have been introduced; and an epitaxial semiconductor layer 31 made of, for example, n- type single crystal silicon formed on the main surface of the substrate body 30. The semiconductor substrate SB may be n type single crystal silicon, into which n type impurities (such as arsenic (As)) have been introduced.

[0053] A power MOSFET (not shown) and a temperature detection element 11 are formed on a semiconductor substrate. In the center of the main surface of the semiconductor substrate, a main MOS region (a formation region of the power MOSFET) is arranged. In addition, in the main MOS region, a temperature diode region (a formation region of the temperature detection element 11) is arranged at a position facing the first protrusion 22a.

[0054] Although not shown here, a plurality of unit transistor cells constituting a power MOSFET are formed on a semiconductor substrate in a main MOS region. A power MOSFET is formed by connecting a plurality of unit transistor cells provided in the main MOS region in parallel. The semiconductor substrate has the function of a drain region of the unit transistor cells in the main MOS region. A backside electrode 32 for the drain is formed on the back side of the substrate body 30 (i.e., the back side of the semiconductor chip 10). The backside electrode 32 is formed by stacking a titanium (Ti) layer, a nickel (Ni) layer, and a gold (Au) layer from the back side of the substrate body 30. The backside electrode 32 is connected to Figure 1 The die pad DP and the drain terminal DT.

[0055] like Figure 2 As shown, in the temperature diode region, a temperature detection element 11 is formed in which a plurality of diodes 110 are connected in series. The diode 110 is composed of, for example, a polysilicon layer having a PN junction.

[0056] In the polysilicon layer, an anode 111 including a p-type impurity and a cathode 112 including an n-type impurity are formed. A plurality of diodes 110 are connected through a diode connection line 113.

[0057] A plurality of diodes 110 connected in series are connected to the anode electrode and the cathode electrode via anode wiring and cathode wiring (not shown), respectively. The plurality of diodes 110 and the diode connection line 113 are covered by a protective film 17 made of polyimide resin. In the protective film 17, an opening exposing a portion of the anode electrode and the cathode electrode is provided, and an anode pad and a cathode pad are formed therein.

[0058] Thus, in the first embodiment, the temperature detection element 11 is formed in the main MOS region, in which the power MOSFET is formed in the center of the semiconductor chip 10. The temperature detection element 11 is covered by the ridge wire 20 of the stitch bonding. The ridge wire 20 is stitch bonded at least at the first stitch joint 21a and the second stitch joint 21b. The temperature detection element 11 is arranged under the first protrusion 22a between the first stitch joint 21a and the second stitch joint 21b. In other words, the temperature detection element 11 is inserted into the space between the first protrusion 22a between the first stitch joint 21a and the second stitch joint 21b and the source pad SP.

[0059] Figure 3 is shown along Figure 1 A photograph of a cross section taken along line II-II. Figure 3 is from Figure 1 The photo is taken from the right side of the cross section of the semiconductor device 1 along the II-II line. Figure 3 As shown, there is a space 23 between the first protrusion 22 a and the semiconductor chip 10 .

[0060] like Figure 3 As shown, the heat generated by the semiconductor chip 10 is directly conducted to the temperature detection element 11 and also conducted from the ridge wire 20. This allows the heat generated by the semiconductor chip 10 to be transferred to the temperature detection element 11 more quickly, thereby improving the thermal response. In this way, by improving the thermal response, when an overcurrent state occurs due to a load short circuit, etc., a cutoff operation can be quickly entered, thereby protecting the element and improving the damage tolerance of the product.

[0061] Although in Figure 1 Although not shown in the drawings, the semiconductor device 1 further includes a sealing body which seals the semiconductor chip 10, the die pad DP, the plurality of terminals, the ridge wire 20, and the wire 16. The sealing body is composed of an insulating resin body such as epoxy resin. Figure 4 is shown along Figure 1 A photograph of a cross section taken along line II-II in FIG. Figure 4 is from Figure 1 The left side of the cross section of the semiconductor device 1 along the II-II line is taken in FIG. Figure 4 As shown, the space 23 between the first protrusion 22a and the semiconductor chip 10 is filled with the sealing body 18. The sealing body 18 electrically isolates the two.

[0062] In order to provide heat from the first protrusion 22a to the temperature detection element 11, it is sufficient for the first protrusion 22a to overlap at least a portion of the temperature detection element 11 in a plan view. It is preferable that the first protrusion 22a overlaps the entire area of ​​the temperature detection element 11.

[0063] Second embodiment

[0064] Figure 5 1 is a plan perspective view showing a configuration example of a semiconductor device 1 according to a second embodiment. Figure 2 In FIG. 1 , illustration of the source terminal ST, the gate terminal GT, the drain terminal DT, etc. is omitted. Figure 5 In, with Figure 1 The same components are denoted by the same reference numerals, and the description is appropriately omitted.

[0065] In the second embodiment, a sensing MOS 19 is formed to replace the temperature detection element 11. That is, the semiconductor chip 10 includes a main MOS region forming a power MOSFET and a sensing MOS region forming a sensing MOSFET, which is a current detection element that detects a current flowing through the power MOSFET. The sensing MOS 19 is formed in the main MOS region, wherein the power MOSFET is formed in the central portion of the semiconductor chip 10.

[0066] In the sense MOS region, a plurality of unit transistor cells constituting a sense MOSFET (current detection element) are formed on a semiconductor substrate. The sense MOSFET is formed by connecting these plurality of unit transistor cells provided in the sense MOS region in parallel.

[0067] Each unit transistor cell formed in the main MOS region and each unit transistor cell formed in the sense MOS region have substantially the same structure (configuration). However, the main MOS region and the sense MOS region are different in area, wherein the area of ​​the main MOS region is larger than that of the sense MOS region.

[0068] Therefore, the number of unit transistor cell connections between the power MOSFET and the sense MOSFET is different. The number of parallel-connected unit transistor cells constituting the sense MOSFET is less than the number of parallel-connected unit transistor cells constituting the power MOSFET. Therefore, if the source potentials of the sense MOSFET and the power MOSFET are the same, the current flowing through the sense MOSFET is less than the current flowing through the power MOSFET.

[0069] Each unit transistor cell in the main MOS region and the sense MOS region is formed by, for example, an n-channel MOSFET having a trench gate structure. In the second embodiment, on / off of the power MOSFET and the sense MOSFET is controlled by supplying a gate voltage to the gate terminal GT.

[0070] The sensing MOSFET is a field effect transistor for detecting the current flowing through the power MOSFET. The current flowing through the power MOSFET can be indirectly detected by the sensing MOSFET. The sensing MOSFET is formed in the semiconductor chip 10 to form a current mirror circuit with the power MOSFET.

[0071] The sense MOSFET has, for example, a size of 1 / n (where n is an arbitrary integer) of the power MOSFET. This size ratio can be changed as needed. If the source voltage of the sense MOSFET and the source voltage of the power MOSFET are equal, due to the above-mentioned current mirror configuration, 1 / n of the current flowing through the power MOSFET flows through the sense MOSFET. In other words, if the size ratio of the power MOSFET and the process MOSFET is known, the current flowing through the power MOSFET can be determined by monitoring the current flowing through the sense MOSFET.

[0072] The drain and gate of the sense MOSFET are shared with the power MOSFET. That is, the drains of the sense MOSFET and the power MOSFET are electrically connected. The common drain is connected to the drain terminal DT, and the same potential is supplied to the drain of the sense MOSFET and the drain of the power MOSFET. In addition, the gates of the sense MOSFET and the power MOSFET are electrically connected and shared. The common gate is connected to the gate terminal GT, and the same gate voltage is input to the gate of the sense MOSFET and the gate of the power MOSFET.

[0073] On the other hand, the source of the sense MOSFET is not shared with the source of the power MOSFET. The source pad SP (first source electrode) of the power MOSFET is connected to the source terminal ST, and the load 2 is connected to the source terminal ST. In contrast, the source electrode (second source electrode) of the sense MOSFET is connected to a source terminal different from the source terminal ST.

[0074] Figure 6 is the explanation Figure 5 The temperature difference-Ids (Vds = constant) characteristics of semiconductor devices are shown in Figure 1. Figure 6 , the horizontal axis represents the temperature difference between the power MOSFET and the sense MOSFET, and the vertical axis represents Ids. Ids(power MOSFET) represents the current flowing through the power MOSFET. Ids(sense MOSFET) represents the current flowing through the process MOSFET. Vds represents the drain-source potential of the sense MOSFET and the power MOSFET.

[0075] Theoretically, the current Ids(power MOSFET) flowing through the power MOSFET is equal to n times the current Ids(sense MOSFET) flowing through the sense MOSFET.

[0076] For example, Fig. 9 and Fig.10 As shown, when the sensing MOS 19 is provided on the edge of the semiconductor chip 10 on which the temperature detection element 11 is arranged, the temperature of the sensing MOSFET is lower than that of the power MOSFET. Figure 6 As shown, since the temperature difference ΔIds between the power MOSFET and the sensing MOSFET increases, that is, the difference between Ids (power MOSFET) and n×Ids (sensing MOSFET) increases, the current cannot be accurately detected (see Figure 6 large temperature differences in the

[0077] In contrast, in the second embodiment, the sensing MOS 19 is covered by the stitch-bonded ridge wire 20. The ridge wire 20 is stitch-bonded at least at the first stitch joint 21a and the second stitch joint 21b. The sensing MOS 19 is arranged under the first protrusion 22a between the first stitch joint 21a and the second stitch joint 21b. In other words, the sensing MOS 19 is inserted into the space between the first protrusion 22a between the first stitch joint 21a and the second stitch joint 21b and the source pad SP.

[0078] With the above configuration, the heat generated in the semiconductor chip 10 is directly conducted to the sense MOS 19 and also conducted from the ridge wire 20. This can reduce the temperature difference between the sense MOSFET and the power MOSFET, reduce ΔIds, and achieve accurate current detection (see Figure 6 small temperature differences in the

[0079] The present invention made by the inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments and can be variously modified within the scope of the gist of the present invention. For example, instead of the above SOP type package, an LGA (convex grid array) package can also be used, in which the semiconductor chip is mounted on the main surface side of a glass epoxy substrate or a stacked substrate, and the convex surface is arranged in a matrix on the back surface side of the substrate.

Claims

1. A semiconductor device, comprising: A semiconductor chip including a first MOSFET formed in a first region of a semiconductor substrate, and a detection element formed in a second region within the first region; and a source electrode formed over the first region and connected to a source of the first MOSFET; as well as A source electrode material is arranged to cover the sensing element and is stitch-bonded to the source electrode. 2 . The semiconductor device according to claim 1 , wherein the source electrode material is stitch-bonded at least at a first joint and a second joint, and the detection element is arranged under the source electrode material between the first joint and the second joint.

3. The semiconductor device according to claim 1, wherein the source electrode material is a ridge-shaped wire made of aluminum. 4 . The semiconductor device according to claim 1 , wherein the detection element is a temperature detection element, and the temperature detection element includes a plurality of diodes connected in series. 5 . The semiconductor device according to claim 1 , wherein the detection element is a current detection element, and the current detection element includes a second MOSFET and a second source electrode connected to a source of the second MOSFET.

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