Power transistor with resonant clamp circuit

Abstract

The invention relates to a power transistor with a resonant clamp circuit. In a general aspect, a circuit is provided that includes a metal oxide semiconductor field effect transistor (MOSFET) having a gate, a source, and a drain. The MOSFET has a first breakdown voltage. The circuit also includes a clamp circuit coupled between the drain and the source. The clamp circuit includes a diode having a second breakdown voltage less than the first breakdown voltage. A cathode of the diode is coupled to the drain of the MOSFET. The clamp circuit also includes an inductor having a first terminal coupled with an anode of the diode and a second terminal coupled with the source of the MOSFET.

Description

Technical Field

[0001] The present invention relates to semiconductor devices and, more particularly, to transistor circuits, such as field effect transistors implemented with resonant clamp circuits, which may be used, for example, in power converter circuits. Background Art

[0002] Power transistors are used in a variety of applications such as consumer electronics, automotive electronics, industrial electronics, etc. For example, power transistors are used in power conversion circuits, such as direct current to direct current (DC-DC) power converters (e.g., synchronous buck converters, etc.), where the power output of the power converter is coupled to a switch node between a high-side (HS) transistor and a low-side (LS) transistor of a half-bridge circuit included in the power converter. Voltage and current overshoots and / or oscillations may occur, for example, during switching of the half-bridge circuit. Such overshoots and / or oscillations may cause the voltage on the power supply node and / or the switch node to exceed the corresponding breakdown voltage of the HS or LS transistor, such as the drain-to-source breakdown voltage (BV ) of a vertical trench gate power metal oxide semiconductor field effect transistor (MOSFET). dss ), for example, the breakdown voltage of the body diode of a MOSFET. When the MOSFET BV is exceeded dss When the power conversion efficiency of the associated power converter is reduced, damage to the transistor may occur, such as threshold shift, breakdown voltage shift, structural damage, etc.

[0003] For example, for a given implementation, one approach to preventing such power efficiency loss and / or potential transistor damage is to increase the BV of the transistor. dss However, increasing BV dss It also increases the on-state resistance of the transistor, such as the drain-to-source on-state resistance (R dson ), which results in higher resistive losses and also reduces the power conversion efficiency. Summary of the invention

[0004] In a general aspect, a circuit is provided, the circuit comprising a metal oxide semiconductor field effect transistor (MOSFET) having a gate, a source and a drain. The MOSFET has a first breakdown voltage. The circuit also comprises a clamping circuit coupled between the drain and the source. The clamping circuit comprises a diode having a second breakdown voltage less than the first breakdown voltage. The cathode of the diode is coupled to the drain of the MOSFET. The clamping circuit also comprises an inductor having a first terminal coupled to an anode of the diode and a second terminal coupled to the source of the MOSFET.

[0005] Implementations may include one or more of the following features or aspects, alone or in combination.For example, the clamp circuit may be configured to resonate when the voltage applied to the drain of the MOSFET exceeds the breakdown voltage of the diode.

[0006] The clamp circuit may include a capacitor and a resistor coupled in series with the capacitor. The capacitor and resistor may be coupled in parallel with the diode and the inductor. The resistor and capacitor may be coupled in parallel with the diode and in series with the inductor.

[0007] The clamping circuit may include a frequency dependent resistor.The second terminal of the inductor may be coupled to the source of the MOSFET via the frequency dependent resistor.

[0008] The inductor may be a first inductor. The clamp circuit may include a resistor-inductor-capacitor (RLC) circuit having a capacitor, a resistor, and a second inductor. The capacitor, the resistor, and the second inductor may be coupled in series with each other. The RLC circuit may be coupled in parallel with the diode and the first inductor.

[0009] The MOSFET may be included in a first semiconductor die. The diode may be included in a second semiconductor die co-packaged with the first semiconductor die. The inductor may include an inductance of an electrical interconnect between the first semiconductor die and the second semiconductor die.

[0010] The circuit may be implemented in a semiconductor die. The diode may include a plurality of interconnect strips. The MOSFET may include a plurality of interconnect strips. The inductor may include an inductance from at least one of: an electrical contact to an anode of the diode; an electrical contact to a source of the MOSFET; an electrical connection between a first and a second of a plurality of interconnect strips of the diode; an electrical connection between a first and a second of a plurality of interconnect strips of the MOSFET; or an electrical connection between the anode of the diode and the source of the MOSFET.

[0011] The circuit may be implemented in a semiconductor die. The semiconductor die may include a metal layer that electrically couples a source of the MOSFET with an anode of the diode. The metal layer may have an inductance included in the inductor. The metal layer may include a plurality of openings configured to adjust the inductance of the metal layer.

[0012] In another general aspect, a half-bridge circuit includes a high-side transistor circuit and a low-side transistor circuit. The high-side transistor circuit includes a first metal oxide semiconductor field effect transistor (MOSFET) having a gate, a source, and a drain. The first MOSFET has a first breakdown voltage. The high-side transistor circuit also includes a first clamping circuit, which includes a first diode having a second breakdown voltage less than the first breakdown voltage. The cathode of the first diode is coupled to the drain of the first MOSFET. The first clamping circuit also includes a first inductor having a first terminal coupled to the anode of the first diode and a second terminal coupled to the source of the first MOSFET. The low-side transistor circuit includes a second MOSFET, which includes a gate, a source, and a drain. The second MOSFET has a third breakdown voltage. The drain of the second MOSFET is coupled to the source of the first MOSFET. The low-side transistor circuit also includes a second clamping circuit, which includes a second diode having a fourth breakdown voltage less than the third breakdown voltage. The cathode of the second diode is coupled to the drain of the second MOSFET. The second clamp circuit also includes a second inductor having a first terminal coupled to the anode of the first diode and a second terminal coupled to the source of the second MOSFET.

[0013] Specific implementations may include one or more of the following features or aspects, alone or in combination. For example, the first clamp circuit may be configured to resonate when the voltage applied to the drain of the first MOSFET exceeds the breakdown voltage of the first diode. The second clamp circuit may be configured to resonate when the voltage applied to the drain of the second MOSFET exceeds the breakdown voltage of the second diode.

[0014] The high-side transistor circuit may be implemented in a semiconductor die. The first diode may include a plurality of interconnect strips. The first MOSFET may include a plurality of interconnect strips. The first inductor may include an inductance from at least one of: an electrical contact to an anode of the first diode; an electrical contact to a source of the first MOSFET; an electrical connection between a first and a second of the plurality of interconnect strips of the first diode; an electrical connection between a first and a second of the plurality of interconnect strips of the first MOSFET; or an electrical connection between the anode of the first diode and the source of the first MOSFET.

[0015] The low-side transistor circuit may be implemented in a semiconductor die. The second diode may include a plurality of interconnect strips. The second MOSFET may include a plurality of interconnect strips. The second inductor may include an inductance from at least one of: an electrical contact with an anode of the second diode; an electrical contact with a source of the second MOSFET; an electrical connection between a first and a second of a plurality of interconnect strips of the second diode; an electrical connection between a first and a second of a plurality of interconnect strips of the second MOSFET; or an electrical connection between the anode of the second diode and the source of the second MOSFET.

[0016] In another general aspect, a power converter circuit includes an output impedance circuit and a half-bridge circuit coupled to the output impedance circuit. The half-bridge circuit includes a high-side transistor circuit and a low-side transistor circuit. The high-side transistor circuit includes a first metal oxide semiconductor field effect transistor (MOSFET) having a gate, a source, and a drain. The first MOSFET has a first breakdown voltage. The high-side transistor circuit also includes a first clamping circuit, which includes a first diode having a second breakdown voltage less than the first breakdown voltage. The cathode of the first diode is coupled to the drain of the first MOSFET. The first clamping circuit also includes a first inductor, which has a first terminal coupled to the anode of the first diode and a second terminal coupled to the source of the first MOSFET. The low-side transistor circuit includes a second MOSFET, which includes a gate, a source, and a drain. The second MOSFET has a third breakdown voltage. The drain of the second MOSFET is coupled to the source of the first MOSFET. The low-side transistor circuit also includes a second clamping circuit, which includes a second diode having a fourth breakdown voltage less than the third breakdown voltage. The cathode of the second diode is coupled to the drain of the second MOSFET. The second clamp circuit also includes a second inductor having a first terminal coupled to the anode of the first diode and a second terminal coupled to the source of the second MOSFET.

[0017] Specific implementations may include one or more of the following features or aspects, alone or in combination. For example, the power converter circuit may be a buck converter circuit. The output impedance circuit may include an output inductor having a first terminal coupled to a switch node of the half-bridge circuit and a second terminal coupled to an output node of the power converter circuit. The output impedance circuit may include an output capacitor having a first terminal coupled to the output node of the power converter circuit and a second terminal coupled to the source of the second MOSFET.

[0018] The first clamp circuit may be configured to resonate when a voltage applied to the drain of the first MOSFET exceeds a breakdown voltage of the first diode. The second clamp circuit may be configured to resonate when a voltage applied to the drain of the second MOSFET exceeds a breakdown voltage of the second diode.

[0019] The first inductor may be configured such that a resonant period of the first clamp circuit during operation of the power converter circuit is less than an avalanche time of the first diode. The second inductor may be configured such that a resonant period of the second clamp circuit during operation of the power converter circuit is less than an avalanche time of the second diode.

[0020] The first inductor may have a first inductance and the second inductor may have a second inductance greater than the first inductance. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a block diagram illustrating an exemplary transistor circuit with a resonant clamp circuit.

[0022] Figure 2 It is shown that the Figure 1 1 is a block diagram of an exemplary power converter circuit of a half-bridge circuit implemented with a transistor circuit.

[0023] Figure 3 It shows that it can be realized Figure 2 Schematic diagram of an exemplary power converter circuit of a power converter circuit.

[0024] Figure 4 is to be used as the high-side transistor Figure 1 A graph comparing the operation of a specific implementation of a transistor circuit with a comparable transistor circuit having a non-resonant clamp circuit in a power converter circuit.

[0025] Figure 5 is shown as a high-side transistor Figure 1 A graph of peak drain-to-source voltage versus clamping inductance for a specific implementation of a transistor circuit.

[0026] Figure 6 is a graph showing the efficiency of a high-side transistor compared to a comparable transistor circuit with a non-resonant clamp circuit. Figure 1 A graph of the power conversion efficiency variation versus clamping inductance for a specific implementation of the transistor circuit.

[0027] Figure 7 is to be used as a low-side transistor Figure 1 A graph comparing the operation of a specific implementation of a transistor circuit with a comparable transistor circuit having a non-resonant clamp circuit in a power converter circuit.

[0028] Figure 8is shown as a low-side transistor Figure 1 A graph of peak drain-to-source voltage versus clamping inductance for a specific implementation of a transistor circuit.

[0029] Fig. 9 is shown as a low-side transistor Figure 1 A graph of power usage efficiency versus clamping inductance for a specific implementation of a transistor circuit.

[0030] Fig. 10A and Fig. 10B is an example transistor circuit (such as Figure 3 Schematic diagram of a transistor circuit of a power converter circuit.

[0031] Fig.11A and Fig. 11B is a diagram illustrating another exemplary transistor circuit with a resonant clamp.

[0032] Fig. 12A and Fig. 12B is a diagram illustrating another exemplary transistor circuit with a resonant clamp.

[0033] Fig.13A and Fig. 13B is a diagram illustrating another exemplary transistor circuit with a resonant clamp.

[0034] Fig.14A and Fig. 14B is a diagram illustrating another exemplary transistor circuit with a resonant clamp.

[0035] Fig.15A and Fig. 15B is shown for implementing transistor circuits such as Fig. 10A and Fig. 10B Schematic diagram of an exemplary method of clamping an inductor in a transistor circuit.

[0036] Fig.16 is a diagram showing an example of adjusting the clamp inductance of a transistor circuit.

[0037] In the drawings that are not necessarily drawn to scale, similar reference symbols may indicate similar and / or similar parts (elements, structures, etc.) in different views. The drawings generally illustrate various specific implementations discussed in the present disclosure by way of example and not limitation. Reference symbols shown in one drawing may not be repeated for the same and / or similar elements in related views. Reference symbols repeated in multiple figures may not be specifically discussed with respect to each of the figures in these figures, but are provided for context between related views. In addition, not all similar elements in the drawings are specifically referenced by reference symbols when multiple instances of the element are shown. DETAILED DESCRIPTION

[0038] In some implementations, a method for reducing voltage and current oscillations and / or overshoot in transistors included in a power converter circuit (such as a synchronous buck DC to DC (DC-DC) power converter) includes the use of clamping diodes. For example, in such implementations, a respective clamping diode is coupled in parallel with each of a high-side (HS) transistor and a low-side (LS) transistor of a half-bridge circuit included in the power converter circuit. Each clamping diode can be a diode having a breakdown voltage that is less than the breakdown voltage of the associated transistor. For example, such a clamping diode can be configured to provide a voltage that is less than the voltage at which the associated transistor enters avalanche breakdown (BV dss ) voltage (BV ka ) enters avalanche breakdown.

[0039] However, since the primary mechanism by which such clamping diodes reduce voltage and current overshoots and / or oscillations is via periodic avalanche breakdown of the clamping diodes, such approaches may result in an undesirable loss of power conversion efficiency (e.g., due to power dissipated during the periodic avalanche). Furthermore, the periodic avalanche may cause the BV of the clamping diode to drop. ka drift, which may be due to BV ka The decrease in BV leads to increased power loss, or ka The increase of BV leads to an undesirable avalanche in the associated transistor. ka Drift can also affect the efficiency of the associated power converter, as well as the long-term reliability of the associated one or more transistors (e.g., LS and / or HS trench gate, vertical power metal oxide semiconductor field effect transistors (MOSFETs)) and the associated circuits of the power converter (such as drivers, controllers, etc.).

[0040] The present disclosure is directed to solving at least some of the above problems (e.g., efficiency loss, BV ka For example, the embodiments described herein provide for effecting discontinuous avalanche in a clamping diode (such as a clamping diode included in a HS transistor circuit and / or a LS transistor circuit), such as the exemplary embodiments described herein. The discontinuous avalanche is effected by, for example, causing a voltage drop in the corresponding clamping diode voltage (V ka ) and the corresponding clamping diode current (I ka). In an exemplary implementation, the resonance is induced (affected, generated, etc.) using at least one inductor (e.g., an inductor, a collection of multiple distributed inductors, etc.) coupled in series with the clamping diode and in parallel with the corresponding transistor. That is, in some implementations, such as those described herein, a clamping circuit for an HS transistor or an LS transistor may include a clamping diode in series with at least one clamping inductor, wherein the series-coupled diode and inductor are coupled in parallel with the associated transistor (e.g., between the source terminal and the drain terminal of the transistor).

[0041] Figure 1 is a block diagram showing an exemplary transistor circuit 110 with a resonant clamp circuit. Figure 1 As shown, transistor circuit 110 includes a power MOSFET 120 and a resonant clamp circuit 130. In some implementations, power MOSFET 120 can be a vertical trench gate MOSFET, such as an n-channel power MOSFET. In some implementations, transistor circuit 110 can be included in a power converter. For example, a corresponding implementation of transistor circuit 110 can be included in a power converter as an HS transistor circuit corresponding to a half-bridge circuit and an LS transistor circuit corresponding to a half-bridge circuit. As described above, in some implementations, resonant clamp circuit 130 can include a series-coupled diode and inductor (LD circuit), wherein the LD circuit is coupled in parallel with power MOSFET 120, for example, between a source terminal and a drain terminal of power MOSFET 120. At least the following description is about Figure 3 , FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B as well as FIG. 14A to FIG. 14B An exemplary implementation of transistor circuit 110 is shown and described.

[0042] In some implementations, the power MOSFET 120 and the resonant clamp circuit 130 can be implemented in a single semiconductor die. In other implementations, the transistor circuit 110 can be in a first semiconductor die, and at least the clamping diode of the resonant clamp circuit 130 can be implemented in a second die. In this example, the inductance of the resonant clamp circuit 130 can include at least the inductance associated with the electrical interconnect between the first semiconductor die and the second semiconductor die. For example, the first semiconductor die and the second semiconductor die can be co-packaged (as a multi-chip module in a single package assembly). The interconnect (such as a conductive clip, wire bond, etc.) between the first semiconductor die and the second semiconductor die can be configured to at least partially provide the inductance of the associated resonant clamp circuit.

[0043] Figure 2is a block diagram showing an exemplary power converter circuit 200 including a half-bridge circuit 215. In this example, the half-bridge circuit 215 may be used Figure 1 That is, the half-bridge circuit 215 of the power converter circuit 200 may include corresponding specific implementations of the transistor circuit 110 for the HS transistor and the LS transistor of the half-bridge circuit 215. For example, in the power converter circuit 200, each of the LS transistor circuit and the HS transistor circuit of the half-bridge circuit 215 may include a corresponding resonant clamp circuit, such as those described herein. For example, the half-bridge circuit 215 may use one or more of the exemplary transistor circuits described and shown herein (such as at least Figure 3 , FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B ) to achieve this.

[0044] like Figure 2 As shown, the power converter circuit 200 also includes an output impedance circuit 240, which can be an inductor-capacitor circuit (LC circuit) for implementing power conversion (e.g., DC-DC conversion) based on a signal generated (provided, produced, etc.) at a switch node of the half-bridge circuit 215. For example, the signal provided at the switch node can be an AC signal generated by the half-bridge circuit 215 from an input DC voltage signal. In this example, the power converter circuit 200 can be a synchronous buck converter, but in some specific implementations, the power converter circuit 200 can implement other types of power converters, such as a boost converter.

[0045] Figure 3 It shows that it can be Figure 2 FIG. 3 is a schematic diagram of an exemplary power converter circuit 300 that is a specific implementation of the power converter circuit 200 of FIG. Figure 3 As shown, the power converter circuit 300 includes an input capacitor 305, an inductor 307, a HS transistor circuit 310hs, a LS transistor circuit 310ls, a switch node 317 (set between the HS transistor circuit 310hs and the LS transistor circuit 310ls), and an output impedance circuit 340. In this example, the input capacitor 305 may include the capacitance of the HS transistor circuit 310hs and the LS transistor circuit 310ls and the capacitance of the main power loop of the power converter circuit 300. In this example, the inductor 307 may include the stray inductance of the main power loop of the power converter circuit 300.

[0046] like Figure 3As shown, the HS transistor circuit 310hs includes a transistor 320hs (with a corresponding body diode shown) and a resonant clamp circuit 330hs, while the LS transistor circuit 310ls includes a transistor 320ls (with a corresponding body diode shown) and a resonant clamp circuit 330ls. In this example, transistor 320hs and transistor 320ls can be corresponding vertical trench gate MOSFETs. Also in this example, the resonant clamp circuit 330hs and the resonant clamp circuit 330ls can be corresponding LD circuits (e.g., a diode and an inductor coupled in series). In addition, in the power converter circuit 300, the output impedance circuit 340 includes an inductor 342 and a capacitor 344, which are configured to provide a desired DC-DC power conversion ratio, for example, to step down an input DC voltage to a desired output DC voltage.

[0047] Figure 4 When implemented as an HS transistor circuit in a power converter circuit (eg, power converter circuit 300), Figure 1 A transistor circuit such as Figure 3 Graph 400 comparing the operation of a specific implementation of the HS transistor circuit 310hs with a comparable transistor circuit having a non-resonant clamp circuit (eg, clamping diode only). Figure 4 In FIG. 1 , time is indicated on the x-axis (increasing from left to right), while the drain-to-source voltage V of the HS transistor is indicated on the y-axis. ds (increasing from bottom to top). The values ​​in graph 400 are normalized, and time and V ds The specific value of will depend on the specific implementation.

[0048] In graph 400, dashed line 435 indicates the BV of the corresponding clamping diode of the exemplary transistor circuit shown in graph 400. ka Trace 450 shows the V ds , trace 460 shows the V of a transistor circuit with a resonant clamp circuit (eg, HS transistor circuit 310hs of power converter circuit 300 with fixed clamp inductance). ds The value of the clamping inductance in this example will depend on the particular implementation. In some implementations, the clamping inductance of a HS transistor circuit, such as HS transistor circuit 310hs, can be in the range of 0.01 nanohenry (nH) to 1 nH.

[0049] As can be seen by comparing trace 450 to trace 460, for the transistor circuit with the non-resonant clamp circuit (trace 450), the associated clamp diode operates in avalanche during the time period from t0 to t1, as indicated by Vds (which corresponds to V ka and Ika ) is indicated. In contrast, the transistor circuit with the resonant clamp circuit (trace 460) has a ds The resonance caused by V ka and I ka This reduction in the amount of time that the transistor circuit associated with trace 460 is periodically avalanching (e.g., repeated over an operating cycle of the associated power converter circuit) can improve power conversion efficiency (e.g., the ratio of output power to input power), as well as reduce deleterious effects such as BV ka Offset, avalanche occurring in HS transistors, etc.

[0050] Figure 5 is shown for use as a high-side transistor circuit Figure 1 transistor circuits (such as for Figure 3 The peak value V of the specific implementation of the HS transistor circuit 310hs) of the power converter circuit 300 is shown. ds That is, in the graph 500, the value of the clamping inductance is indicated on the x-axis (increasing from left to right), and the corresponding peak value V is indicated on the y-axis. ds The values ​​in graph 500 are normalized, and the clamp inductance and peak V ds The exact value of will depend on the specific implementation. Figure 5 As shown, increasing the clamping inductance of the HS transistor circuit results in a peak V ds Therefore, the value of the clamping inductance of the HS transistor circuit (e.g., a synchronous buck converter such as power converter circuit 300) in this example should be tuned (configured, adjusted, etc.) so that the corresponding peak Vds value does not cause continuous avalanche (e.g., Figure 4 450 in FIG.

[0051] Figure 6 It is shown that Figure 1 A graph 600 of a change in power conversion efficiency (Δefficiency) versus HS clamp inductance for a power conversion circuit for a specific implementation of a transistor circuit (e.g., as an HS transistor circuit). In this example, the Δefficiency shown by graph 600 is compared to the power conversion efficiency of a comparable power conversion circuit having an HS transistor circuit with a non-resonant clamp circuit. That is, in graph 600, the values ​​of the clamp inductance are indicated on the x-axis (increasing from left to right), while the corresponding Δefficiency values ​​are indicated on the y-axis. The clamp inductance values ​​in graph 600 are normalized, and the specific value of the clamp inductance will depend on the specific implementation. The x-axis scale in graph 600 is normalized to correspond to Figure 5 As can be seen from graphs 500 and 600, increasing the clamping inductance of the HS transistor circuit in this example increases the peak V ds HS clamp inductance while providing a small increase in Δ efficiency (relative to using a non-resonant clamp circuit). Therefore, any efficiency benefit associated with the increased HS clamp inductance may be offset by the peak V ds exceeded by the corresponding increase in .

[0052] Figure 7 When implemented as an LS transistor circuit in a power converter circuit (eg, power converter circuit 300), Figure 1 A transistor circuit such as Figure 3 1 is a graph comparing the operation of a specific implementation of the LS transistor circuit 310ls with a comparable transistor circuit having a non-resonant clamp circuit (e.g., clamping diode only). Figure 7 In FIG. 1 , time is indicated on the x-axis (increasing from left to right), and the voltage V of the LS transistor is indicated on the y-axis. ds (Increasing from bottom to top). Figure 7 The values ​​in the graph are normalized, and the time and V ds The specific value of will depend on the specific implementation.

[0053] exist Figure 7 In the graph of FIG. 1 , the dashed line 735 indicates the BV of the corresponding clamping diode of the exemplary transistor circuit shown. ka Trace 750 shows the V ds , trace 760 shows the V of a transistor circuit with a resonant clamp circuit (eg, LS transistor circuit 310 ls of power converter circuit 300 with fixed clamp inductance). ds . The value of the clamping inductance in this example will depend on the particular implementation. In some implementations, the clamping inductance of an LS transistor circuit (such as LS transistor circuit 310ls) can be in the range of 0.01 nanohenry (nH) to 1 nH. That is, in some implementations, such as those described herein, the clamping inductance implemented for the LS transistor circuit can be larger (e.g., 4 to 5 times larger) than the clamping inductance implemented for the corresponding HS transistor circuit. This difference can be at least partially due to the different sizes of HS transistors and LS-side transistors in the power conversion circuit, for example, transistors used for the LS transistor circuit are larger (e.g., have a higher current capacity with an associated higher capacitance) than relatively smaller transistors used to implement the corresponding HS transistor circuit.

[0054] As can be seen by comparing trace 750 to trace 760, for the transistor circuit with the non-resonant clamp circuit (trace 750), the associated clamp diode operates in avalanche during the time period from t2 to t3, as indicated by Vds (which corresponds to V ka and I ka ) is indicated. In contrast, the transistor circuit with the resonant clamp circuit (trace 760) has a ds The resonance caused by V ka and I ka The induced resonance) is operated in avalanche in about half of the time period from t2 to t3. Figure 4 As discussed above, such a reduction in the amount of time that a periodic avalanche of the transistor circuit associated with trace 760 occurs (e.g., repeated over an operating cycle of the associated power converter circuit) can improve power conversion efficiency (e.g., the ratio of output power to input power), as well as reduce deleterious effects such as BV ka Offset, avalanche occurring in HS transistors, etc.

[0055] Figure 8 is shown for use as a LS transistor circuit Figure 1 transistor circuits (such as for Figure 3 The peak value V of the specific implementation of the LS transistor circuit 310 ls of the power converter circuit 300 is shown. ds That is, in Figure 8 In the graph of , the value of the clamping inductance is indicated on the x-axis (increasing from left to right), and the corresponding peak value V is indicated on the y-axis. ds value (increasing from bottom to top). Figure 8 The values ​​in are normalized and the clamp inductance and peak V ds The exact value of will depend on the specific implementation. Figure 8 As shown, increasing the clamping inductance of the LS transistor circuit initially causes a peak V ds The corresponding increase, and then in the approximation L cl_ls The peak voltage V ds Therefore, the value of the clamping inductance of the LS transistor circuit (e.g., a synchronous buck converter such as power converter circuit 300) in this example can be tuned (configured, adjusted, etc.) to benefit from this reduction in the corresponding peak Vds value. Figure 8 As shown, a peak value V ds Such changes may be due to the clamping diode, clamping inductor and MOSFET C ossThat is, when changing the value of the clamping inductor (Lcl), since such interference changes from constructive to destructive and vice versa, the peak value V ds May fluctuate.

[0056] Fig. 9 It is shown that Figure 1 A graph of power conversion efficiency (percent conversion efficiency) versus LS clamp inductance for a power conversion circuit of a specific implementation of a transistor circuit (eg, as an LS transistor circuit). In this example, Fig. 9 As shown in the graph in , the power conversion efficiency (in percent) does not change significantly with increasing LS clamp inductance. Fig. 9 As shown, a variation of approximately 0.2% is observed within the range shown, which covers more than three orders of magnitude variation in LS clamp inductance. Thus, the benefit of reduced peak Vds associated with increased LS clamp inductance does not result in a significant change (e.g., reduction) in the associated power conversion efficiency.

[0057] In addition to the considerations discussed above (e.g., efficiency and peak V ds ), the resonant period should also be considered when selecting the clamping inductance value for the resonant clamping circuit. For example, the clamping inductance value should be selected so that the resonant period (T RES ) is less than the avalanche time T of the corresponding clamping diode AVALANCHE .

[0058] refer to Figure 3 As an example, in some implementations, for example, the corresponding output capacitance of the clamping diodes of the HS transistor circuit 310hs and the LS transistor circuit 310ls is equal to the corresponding output capacitance C of the corresponding HS transistor 320hs and the corresponding LS transistor 320ls. OSS Compared with the negligible case, T RES It can be given by the following formula:

[0059]

[0060] For HS transistor circuit 310hs (where C OSS is the output capacitance of transistor 320hs) and LS transistor circuit 310ls (where C OSS is each of the output capacitances of transistor 320ls).

[0061] Furthermore, in this example, the calculation of the avalanche time for each of HS transistor circuit 310hs and LS transistor circuit 310ls is significantly different due to the size of HS transistor 320hs compared to the size of LS transistor 320ls, and their arrangement in power converter circuit 300. For example, the avalanche time for LS transistor circuit 310ls may be (approximately) given by:

[0062]

[0063] Where L STRAY is the inductance of the inductor 307, and C OSS LS is the output capacitance of transistor 320ls.

[0064] The avalanche time of the HS transistor circuit 310hs is given by:

[0065]

[0066] Where L STRAY is the inductance of the inductor 307, I LOAD is the output current of the power converter circuit 300, and α is an indication of I as an avalanche current. LOAD The percentage factor, BV KA is the breakdown (avalanche) voltage of the HS clamp diode, and V IN is the input voltage of the power converter circuit 300 (eg, the voltage being converted). Therefore, to achieve T RES To determine the desired value of the clamping inductor, different values ​​of the clamping inductor may be used, for example, based on the equation provided above.

[0067] Exemplary implementations of various transistor circuits with resonant clamp circuits (eg, implementations of transistor circuit 110) are described in detail in FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B Each of these respective implementations is shown as a circuit schematic ( Fig. 10A , Fig.11A , Fig. 12A , Fig.13A and Fig.14A ) and is shown as a hybrid diagram including circuit schematic elements combined with a cross-sectional semiconductor device view ( Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B). Each of the exemplary transistor circuits shown includes a MOSFET, a clamping diode, and at least one clamping inductor. Some of the exemplary implementations also include resistors and / or capacitors in their resonant clamping circuits. Various methods may be used to implement these elements. For example, in some implementations, the clamping inductor may include inductances from different metal structures (such as contacts, electrical interconnects), and / or other structures (such as metal spirals formed in semiconductor devices). In some implementations, resistors may be implemented using polysilicon structures, diffusion structures, metal structures, etc. In some implementations, capacitors may be implemented using polysilicon electrodes disposed in dielectric-lined trenches formed in highly doped semiconductor regions, or capacitors may be implemented using a dielectric (e.g., oxide) disposed between two conductive plates (e.g., metal plates and / or doped polysilicon plates). The foregoing is provided by way of example and is used to implement FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B Other approaches to elements of the exemplary transistor circuits are possible.

[0068] Likewise, for purposes of illustration and by way of example, Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B The same semiconductor device structures (clamping diode and trench gate MOSFET structures) are shown in the hybrid diagram of FIG. 1 . In some implementations, structures different from those shown can be used. In addition, certain aspects of the MOSFET (e.g., gate, source, and drain terminals) and clamping diode (anode and cathode) of the exemplary transistor circuit are shown in FIG. Fig. 10A and Fig. 10B However, for the sake of brevity and clarity, these elements may not be discussed in detail. FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B Specific reference and / or description is made with respect to other exemplary transistor circuit implementations.

[0069] Fig. 10A and Fig. 10B is a diagram showing an exemplary transistor circuit 1010 (such as Figure 3 FIG. 3 is a diagram of a transistor circuit (HS transistor circuit 310hs and LS transistor circuit 310ls)) of a power converter circuit 300. Fig. 10A and Fig. 10BAs shown, transistor circuit 1010 includes power MOSFET 1020 and resonant clamp circuit 1030. Power MOSFET 1020 includes gate terminal 1020g, drain terminal 1020d and source terminal 1020s, which are connected to each other at Fig. 10A and Fig. 10B As discussed herein, power MOSFET 1020 may be a vertical trench gate MOSFET, such as Fig. 10B As shown in the cross-sectional view of the semiconductor structure. Fig. 10A and Fig. 10B As further shown in FIG. 1 , the resonant clamp circuit 1030 includes a clamp diode 1032 and a clamp inductor 1034, which are coupled in series with each other. That is, a first terminal of the clamp inductor 1034 is coupled to the source terminal 1020s of the power MOSFET 1020, and a second terminal of the clamp inductor 1034 is coupled to the anode terminal 1032a of the clamp diode 1032.

[0070] Also like Fig. 10A and Fig. 10B As shown, the cathode terminal 1032c of the clamping diode 1032 is coupled to the drain terminal 1020d of the power MOSFET 1020. That is, the series-coupled clamping diode 1032 and the clamping inductor 1034 of the resonant clamping circuit 1030 are coupled in parallel with the power MOSFET 1020. Fig. 10B As shown, the clamping diode 1032 may be implemented with an anode terminal 1032a being a heavily doped p-type region disposed on a cathode terminal 1032c, which is implemented by an n-type region (e.g., a region formed by epitaxy). Fig. 10B (as well as Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B ), the cross-sectional views of the corresponding clamping diodes and MOSFETs are shown upside down. That is, in these figures, the backside (bottom side) of the corresponding semiconductor die (or separate die) is shown at the corresponding top of the structure in the shown view.

[0071] Fig.11A and Fig. 11B 1 is a diagram showing another exemplary transistor circuit 1110 with a resonant clamp. As with transistor circuit 1010, transistor circuit 1110 includes a power MOSFET 1120 and a resonant clamp circuit 1130, which includes a clamp diode 1132 and a clamp inductor 1134, the power MOSFET and the resonant clamp circuit being connected in the same arrangement as the corresponding elements of transistor circuit 1010. Therefore, for the sake of brevity, no further description will be given. Fig.11A and Fig. 11B Those similar elements are described in detail.

[0072] In addition to the above elements, transistor circuit 1110 also includes a resistor-capacitor (RC) circuit branch connected in parallel with power MOSFET 1120 (and in parallel with an LD circuit including clamping diode 1132 and clamping inductor 1134). Fig.11A and Fig. 11B As shown, the RC circuit branch may include a capacitor 1136 and a resistor 1138. Fig. 11B As shown, capacitor 1136 may be implemented by a polysilicon electrode disposed in a dielectric lined trench included at an edge of clamping diode 1132. Resistor 1138 may be implemented at least in part by the resistance of the polysilicon electrode of capacitor 1136. In this example, the RC circuit branch may modulate the resonance of resonant clamp circuit 1130.

[0073] Fig. 12A and Fig. 12B 1 is a diagram showing another exemplary transistor circuit 1210 with a resonant clamp. As with transistor circuits 1010 and 1110, transistor circuit 1210 includes a power MOSFET 1220 and a resonant clamp circuit 1230, which includes a clamping diode 1232 and a clamping inductor 1234, which are connected in the same arrangement as the corresponding elements of transistor circuits 1010 and 1110. Therefore, for the purpose of brevity, no further description will be given. Fig. 12A and Fig. 12B Those similar elements are described in detail.

[0074] In addition to the above elements, the transistor circuit 1210 also includes a resistor-capacitor (RC) circuit branch connected in parallel with the clamping diode 1232 and in series with the clamping inductor 1234. Fig. 12A and Fig. 12B As shown, the RC circuit branch may include a capacitor 1236 and a resistor 1238. Fig. 12B As shown, like capacitor 1136, capacitor 1236 may be implemented by a polysilicon electrode disposed in a dielectric lined trench included at an edge of clamping diode 1232. Like resistor 1138, resistor 1238 may be implemented at least in part by the resistance of the polysilicon electrode of capacitor 1236. In this example, like the RC circuit branch of transistor circuit 1110, the RC circuit branch of transistor circuit 1210 may modulate the resonance of resonant clamp circuit 1230.

[0075] Fig.13A and Fig. 13B1 is a diagram showing another exemplary transistor circuit 1310 with a resonant clamp. As with transistor circuits 1010, 1110, and 1210, transistor circuit 1310 includes a power MOSFET 1320 and a resonant clamp circuit 1330, which includes a clamping diode 1332 and a clamping inductor 1334, the power MOSFET and the resonant clamp circuit being connected in the same arrangement as the corresponding elements of transistor circuits 1010, 1110, and 1210. Therefore, for the sake of brevity, no further description will be given. Fig.13A and Fig. 13B Those similar elements are described in detail.

[0076] In addition to the above elements, transistor circuit 1210 also includes a frequency dependent resistor 1338 coupled in series with clamping diode 1332 and clamping inductor 1334. In this example, frequency dependent resistor 1338 can provide resonance damping for resonant clamp circuit 1330 of transistor circuit 1310. In some implementations, frequency dependent resistor 1338 can be implemented, for example, using metal vias having a thickness and width designed to enhance the skin effect and, therefore, the dependence of resistance on frequency.

[0077] Fig.14A and Fig. 14B 1 is a diagram showing another exemplary transistor circuit 1410 with a resonant clamp. Like transistor circuit 1010, transistor circuit 1110, transistor circuit 1210, and transistor circuit 1310, transistor circuit 1410 includes a power MOSFET 1420 and a resonant clamp circuit 1430, the resonant clamp circuit including a clamping diode 1432 and a clamping inductor 1434, the power MOSFET and the resonant clamp circuit being connected in the same arrangement as the corresponding elements of transistor circuit 1010, transistor circuit 1110, transistor circuit 1210, and transistor circuit 1310. Therefore, for the sake of brevity, no further description will be given of the power MOSFET 1420 and the resonant clamp circuit 1430. Fig.14A and Fig. 14B Those similar elements are described in detail.

[0078] In addition to the above elements, transistor circuit 1410 also includes a resistor-inductor-capacitor (RLC) circuit branch connected in parallel with power MOSFET 1420 (and in parallel with an LD circuit including clamping diode 1432 and clamping inductor 1434). Fig.14A and Fig. 14B As shown, the RLC circuit branch may include a capacitor 1436, a resistor 1438, and an inductor 1439. The elements of the RLC circuit branch of transistor circuit 1410 may be implemented, for example, using the methods described herein. Fig. 14BAs shown, capacitor 1436 can be implemented by a polysilicon electrode disposed in a dielectric lined trench included at the edge of clamping diode 1432. Resistor 1438 can be implemented at least in part by the resistance of the polysilicon electrode of capacitor 1136. Inductor 1439 can be implemented using, for example, the inductance of one or more metal structures such as using the methods described herein. In this example, the RLC circuit branch can provide resonant damping and / or resonant modulation for resonant clamp circuit 1430. In some implementations, inductor 1439 can have an inductance greater than the inductance of inductor 1434.

[0079] Fig.15A and Fig. 15B is shown for implementing in a transistor circuit (such as FIG. 10A to FIG. 10B , FIG. 11A to FIG. 11B , FIG. 12A to FIG. 12B , FIG. 13A to FIG. 13B and FIG. 14A to FIG. 14B Schematic diagram of an exemplary method of clamping inductance in a transistor circuit). Fig.15A Schematically illustrates a top view of a transistor circuit 1510 with a resonant clamp, which may be included in the exemplary implementations described herein. Fig.15A As shown, transistor circuit 1510 includes multiple strips of clamping diodes, such as strip 1532a and strip 1532b. In this example, strips 1532a and 1532b can be, for example, formed by an overlying metal layer ( Fig.15A and Fig. 15B 1510) (not shown) such as a source metal layer for a power MOSFET 1520 of transistor circuit 1510. In this example, power MOSFET 1520 also includes a plurality of strips indicated by gate trenches 1520s that can be interconnected (e.g., via an overlying source metal layer) to form a corresponding power MOSFET 1520.

[0080] like Fig. 15B As shown, it shows that the transistor circuit 1510 is composed of Fig.15A A side cross-sectional view of the semiconductor structure is shown of the portion indicated by the dashed line inset (eg, the strip 1532a including the clamping diode and a portion of the power MOSFET 1520). Fig. 15B The semiconductor structure shown is similar to that in Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B The semiconductor structures of transistor circuit 1010, transistor circuit 1110, transistor circuit 1210, transistor circuit 1310, and transistor circuit 1410 are shown. Fig. 15B of the views, those views are shown with Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B and Fig. 14B The view is reversed (e.g., the corresponding back side of the associated semiconductor die is in the Fig. 15B at the bottom of the structure in the view).

[0081] like Fig. 15B As shown, the clamping inductor 1534 of the resonant clamping circuit of the transistor circuit 1510 can be a distributed inductor including a plurality of L cl_v Inductor, multiple L cl_h inductor and at least one L cl_int inductors, which can be aggregated into a clamping inductor 1534 (L cl ). In some specific implementations, L cl_v The inductance may be the inductance associated with an electrical contact, such as the anode contact of the clamping diode and / or the contact with the source diffusion (and body region) of the power MOSFET 1520. cl_h The inductance may be the inductance associated with the electrical interconnections between the diode bars and / or the power MOSFET bars (eg, between the anode contacts and / or between the source contacts). Furthermore, at least one L cl_int The inductance may be the inductance associated with the electrical interconnect between the clamping diode (e.g., strip 1532a and / or strip 1532b) and the power MOSFET 1520. For example, such interconnect may be intra-die (e.g., within the same semiconductor) or inter-die (e.g., between separate dies in a common package or separate packages).

[0082] Fig.16 is a diagram showing an example of adjusting the clamp inductance of a transistor circuit. Fig.16 In the example of FIG. 1 , a portion of a transistor circuit 1610 is shown, where the transistor circuit 1610 is similar to Fig.15A and Fig. 15B The transistor circuit 1510. For example, in Fig.16 , the illustrated portion of transistor circuit 1610 includes a strip 1632 of clamping diodes and a portion of power MOSFET 1620 (eg, a plurality of MOSFET strips). Fig.16 Also shown is an overlying metal layer 1670 (e.g., a source metal layer of power MOSFET 1620) that can interconnect strip 1632 to power MOSFET 1620 and can have a similar Fig.15A and Fig. 15B At least one L of the transistor circuit 1510 cl_int The corresponding inductance. Fig.16As shown, the overlying metal layer 1670 may include a plurality of openings 1675 (eg, holes, slits, etc.), which may change the inductance (L) associated with the overlying metal layer 1670. cl_int ), for example, compared to a metal layer without such openings. Of course, other methods for adjusting (tuning, modifying, implementing, etc.) the clamping inductance of a resonant clamp circuit are possible.

[0083] The various devices and techniques described herein can be implemented using various semiconductor processing and / or packaging technologies. Some embodiments can be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0084] It should also be understood that when an element such as a layer, region, or substrate is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to another element, or one or more intermediate elements may be present. In contrast, when an element is referred to as being directly on, directly connected to, or directly coupled to another element or layer, there are no intermediate elements or layers. As used herein, "coupled to" or "coupled with" may refer to being electrically coupled to, electrically coupled to, physically coupled to, and / or physically coupled to.

[0085] Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to an element can be referred to in such a manner. The claims of the present application may be amended to recite exemplary relationships described in the specification or shown in the drawings.

[0086] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

[0087] Although certain features of the specific implementations described have been described as described herein, many modifications, alternatives, variations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any part of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A circuit comprising: A metal oxide semiconductor field effect transistor MOSFET, wherein the MOSFET comprises a gate, a source and a drain, and the MOSFET has a first breakdown voltage; and A clamping circuit, the clamping circuit being coupled between the drain and the source, the clamping circuit comprising: a diode having a second breakdown voltage less than the first breakdown voltage, a cathode of the diode coupled to the drain of the MOSFET; and An inductor has a first terminal coupled to the anode of the diode and a second terminal coupled to the source of the MOSFET. 2 . The circuit of claim 1 , wherein the clamp circuit is configured to resonate when a voltage applied to the drain of the MOSFET exceeds a breakdown voltage of the diode.

3. The circuit of claim 1 , wherein the clamping circuit further comprises: Capacitors; and A resistor is coupled in series with the capacitor.

4. The circuit of claim 3, wherein the capacitor and the resistor are coupled in parallel with the diode and the inductor.

5. The circuit of claim 3, wherein the resistor and the capacitor are coupled in parallel with the diode and in series with the inductor. 6 . The circuit of claim 1 , wherein the clamp circuit further comprises a frequency dependent resistor, the second terminal of the inductor being coupled to the source of the MOSFET via the frequency dependent resistor.

7. The circuit of claim 1, wherein the inductor is a first inductor, the clamping circuit further comprises a resistance-inductance-capacitance (RLC) circuit, the RLC circuit having: Capacitors; Resistors; and The capacitor, the resistor and the second inductor are coupled in series with each other, and the RLC circuit is coupled in parallel with the diode and the first inductor.

8. The circuit of claim 1, wherein: The MOSFET is included in a first semiconductor die; The diode is included in a second semiconductor die co-packaged with the first semiconductor die; and The inductor includes an inductance of an electrical interconnect between the first semiconductor die and the second semiconductor die.

9. The circuit of claim 1, wherein: The circuit is implemented in a semiconductor die; The diode comprises a plurality of interconnecting strips; The MOSFET comprises a plurality of interconnect strips; and The inductor comprises an inductance from at least one of: an electrical contact to the anode of the diode; an electrical contact to a source of the MOSFET; an electrical connection between a first and a second of the plurality of interconnect strips of the diode; an electrical connection between a first and a second of the plurality of interconnect strips of the MOSFET; or An electrical connection between the anode of the diode and the source of the MOSFET.

10. The circuit of claim 1, wherein: The circuit is implemented in a semiconductor die; and The semiconductor die includes a metal layer electrically coupling the source of the MOSFET with the anode of the diode, the metal layer having an inductance included in the inductor. 11 . The circuit of claim 10 , wherein the metal layer comprises a plurality of openings configured to adjust the inductance of the metal layer.

12. A half-bridge circuit, comprising: A high-side transistor circuit, the high-side transistor circuit comprising: A first metal oxide semiconductor field effect transistor MOSFET, the first MOSFET comprising a gate, a source and a drain, the first MOSFET having a first breakdown voltage; and A first clamping circuit, wherein the first clamping circuit comprises: a first diode having a second breakdown voltage less than the first breakdown voltage, a cathode of the first diode coupled to the drain of the first MOSFET; and a first inductor having a first terminal coupled to an anode of the first diode and a second terminal coupled to the source of the first MOSFET; and A low-side transistor circuit, the low-side transistor circuit comprising: a second MOSFET including a gate, a source, and a drain, the second MOSFET having a third breakdown voltage, the drain of the second MOSFET being coupled to the source of the first MOSFET; and A second clamping circuit, wherein the second clamping circuit comprises: a second diode having a fourth breakdown voltage less than the third breakdown voltage, a cathode of the second diode coupled to the drain of the second MOSFET; and A second inductor having a first terminal coupled to the anode of the second diode and a second terminal coupled to the source of the second MOSFET.

13. The half-bridge circuit according to claim 12, wherein: The first clamp circuit is configured to resonate when a voltage applied to the drain of the first MOSFET exceeds a breakdown voltage of the first diode; and The second clamp circuit is configured to resonate when a voltage applied to the drain of the second MOSFET exceeds a breakdown voltage of the second diode.

14. The half-bridge circuit according to claim 12, wherein: The high-side transistor circuit is implemented in a semiconductor die; The first diode comprises a plurality of interconnecting strips; The first MOSFET comprises a plurality of interconnect strips; and The first inductor comprises an inductance from at least one of: an electrical contact to the anode of the first diode; an electrical contact to a source of the first MOSFET; an electrical connection between a first and a second of the plurality of interconnect strips of the first diode; An electrical connection between a first and a second of the plurality of interconnect strips of the first MOSFET; or An electrical connection between the anode of the first diode and the source of the first MOSFET.

15. The half-bridge circuit according to claim 12, wherein: The low-side transistor circuit is implemented in a semiconductor die; The second diode comprises a plurality of interconnecting strips; The second MOSFET comprises a plurality of interconnect strips; and The second inductor comprises an inductance from at least one of: an electrical contact to the anode of the second diode; an electrical contact to a source of the second MOSFET; an electrical connection between a first and a second of the plurality of interconnect strips of the second diode; An electrical connection between a first and a second of the plurality of interconnect strips of the second MOSFET; or An electrical connection between the anode of the second diode and the source of the second MOSFET.

16. A power converter circuit, the power converter circuit comprising: Output impedance circuit; and A half-bridge circuit, the half-bridge circuit is coupled to the output impedance circuit, the half-bridge circuit comprising: A high-side transistor circuit, the high-side transistor circuit comprising: A first metal oxide semiconductor field effect transistor MOSFET, the first MOSFET comprising a gate, a source and a drain, the first MOSFET having a first breakdown voltage; and A first clamping circuit, wherein the first clamping circuit comprises: a first diode having a second breakdown voltage less than the first breakdown voltage, a cathode of the first diode coupled to the drain of the first MOSFET; and a first inductor having a first terminal coupled to an anode of the first diode and a second terminal coupled to the source of the first MOSFET; and A low-side transistor circuit, the low-side transistor circuit comprising: a second MOSFET including a gate, a source, and a drain, the second MOSFET having a third breakdown voltage, the drain of the second MOSFET being coupled to the source of the first MOSFET; and A second clamping circuit, wherein the second clamping circuit comprises: a second diode having a fourth breakdown voltage less than the third breakdown voltage, a cathode of the second diode coupled to the drain of the second MOSFET; and A second inductor having a first terminal coupled to the anode of the second diode and a second terminal coupled to the source of the second MOSFET.

17. The power converter circuit of claim 16, wherein: The power converter circuit is a buck converter circuit; and The output impedance circuit comprises: an output inductor having a first terminal coupled to a switch node of the half-bridge circuit and a second terminal coupled to an output node of the power converter circuit; and An output capacitor has a first terminal coupled to the output node of the power converter circuit and a second terminal coupled to the source of the second MOSFET.

18. The power converter circuit of claim 16, wherein: The first clamp circuit is configured to resonate when a voltage applied to the drain of the first MOSFET exceeds a breakdown voltage of the first diode; and The second clamp circuit is configured to resonate when a voltage applied to the drain of the second MOSFET exceeds a breakdown voltage of the second diode.

19. The power converter circuit of claim 16, wherein: The first inductor is configured such that a resonant period of the first clamp circuit is less than an avalanche time of the first diode during operation of the power converter circuit; and The second inductor is configured such that a resonant period of the second clamp circuit is less than an avalanche time of the second diode during operation of the power converter circuit.

20. The power converter circuit of claim 16, wherein: The first inductor has a first inductance; and The second inductor has a second inductance greater than the first inductance.

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