Control circuit, flyback converter and control method thereof

Abstract

The invention relates to a control circuit, a flyback converter and a control method thereof. The flyback converter comprises: a transformer (T) comprising a primary side adapted to be connected to a power supply (Vin) and a secondary side adapted to be connected to a load (Ro); a switch (M1) connected in series with the primary side at a node; the control circuit includes: a first control circuit (10) configured to control on or off of the switch (M1) based on a control voltage (Vcomp) generated based on a primary side voltage (Vsw) sensed at the node SW when the switch (M1) is off; and a second control circuit (20) configured to output a signal for entering a low power mode (LowPowerSD) based on the control voltage being below a predetermined threshold, the signal for entering the low power mode being output to one or more power consuming components in the first control circuit (10) such that the one or more power consuming components are deactivated in response to the signal for entering the low power mode.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the field of switching power supplies, and more particularly to a control circuit for a flyback converter, a flyback converter, and a control method thereof. Background Art

[0002] Isolation converters (hereinafter referred to as "converters") are widely used in industrial, automotive and household power supply systems due to their excellent safety performance. Isolation converters include transformers, which isolate the power supply end and the load end to provide good safety performance, and thus are more widely used.

[0003] The converter dynamically adjusts the power provided by controlling the switching frequency of switches (such as transistors) to adapt to the power requirements of the load. However, the energy efficiency of traditional converters is not satisfactory, especially in light load or no-load scenarios. In high-load application scenarios, the converter typically operates in quasi-resonant mode (Qusia-Resonate QR) to improve the energy efficiency of the converter; when the load power decreases, the switching frequency will increase, which will deteriorate the energy efficiency of the converter. The converter typically operates in a fixed-frequency intermittent operation DCM mode; but if the load power is further reduced, the fixed-frequency DCM mode will seriously increase the loss and deteriorate the energy efficiency of the converter. Although the converter can further reduce the switching frequency or operate in a light-load burst mode, the light-load or no-load energy consumption of the converter is still high. It is expected that the energy efficiency of the converter can be further improved. Summary of the invention

[0004] Embodiments of the present disclosure provide a control circuit for a flyback converter, a flyback converter and a control method thereof, aiming to solve one or more of the above-mentioned problems and other potential problems.

[0005] According to a first aspect of the present disclosure, a control circuit is provided for a flyback converter, the flyback converter comprising: a transformer comprising a primary side suitable for being connected to a power supply and a secondary side suitable for being connected to a load; a switch connected in series with the primary side at a node; the control circuit comprising: a first control circuit configured to control the on or off state of the switch based on a control voltage, wherein the control voltage is generated based on a primary side voltage sensed at the node when the switch is cut off; and a second control circuit configured to: output a signal to enter a low power consumption mode based on the control voltage being lower than a predetermined threshold, the signal to enter a low power consumption mode being output to one or more power consumption components in the first control circuit, so that the one or more power consumption components are disabled in response to the signal to enter a low power consumption mode.

[0006] According to the present disclosure, by setting a second control circuit to control one or more power consumption components in the first control circuit, the power consumption of the system can be further reduced, thereby further improving the light load or no-load energy efficiency of the system.

[0007] In some embodiments, the first control circuit also includes a ringing detection circuit, which is configured to output a ringing signal in response to detecting a ringing period of the primary voltage; and the second control circuit also includes a first comparator, which is configured to compare the control voltage with the predetermined threshold and output a first comparator signal when the control voltage is lower than the predetermined threshold; the second control circuit outputs the low power consumption mode entry signal based at least on the first comparison signal and the ringing signal.

[0008] In some embodiments, the first control circuit includes: an oscillation circuit configured to output a switching clock signal based on the control voltage; and a logic circuit configured to generate a switching signal that turns on or off the switch based at least on the switching clock signal.

[0009] In some embodiments, the second control circuit includes: an entry and exit low power consumption logic circuit, the entry and exit low power consumption logic circuit includes a timer, the timer is configured to: time the duration of the first comparator signal, and output a first signal in response to the timing time exceeding a first predetermined time length, the entry and exit low power consumption logic circuit outputs the entry low power consumption mode signal based at least on the first signal and the switching clock signal.

[0010] In some embodiments, the low power mode exit logic circuit is configured to output an exit low power mode signal in response to detecting a ringing signal in a next switching clock signal cycle, and the one or more power consumption components are enabled in response to the exit low power mode signal.

[0011] In some embodiments, the second control circuit further includes a wake-up circuit, which is configured to output a wake-up signal based on the switch clock signal; the wake-up circuit includes a delay circuit, which is configured to: output the wake-up signal in response to receiving the switch clock signal delayed by a second predetermined time; wherein the logic circuit is configured to: generate a switch signal that turns on the switch based at least on the wake-up signal after the second predetermined time period after the one or more power consumption components are enabled.

[0012] In some embodiments, the first control circuit further includes at least one of the following: a sampling circuit configured to sample the primary voltage; a second comparator configured to compare the current derived from the control voltage with the primary current sensed when the switch is turned on; and a ringing detection circuit configured to detect ringing of the primary voltage and output a ringing signal.

[0013] In some embodiments, the low power mode entry signal is output to at least one of the sampling circuit, the second comparator, and the ringing detection circuit.

[0014] According to a second aspect of the present disclosure, a control method for a flyback converter is provided, comprising: outputting a low power mode entry signal based on a control voltage of the flyback converter being lower than a predetermined threshold, wherein the control voltage is generated based on a primary voltage sensed at a node in series with the primary side when the switch of the flyback converter is turned off; and outputting the low power mode entry signal to one or more power consumption components in a first control circuit of the flyback converter, so that the one or more power consumption components are disabled in response to the low power mode entry signal, wherein the first control circuit is disposed on the primary side of the transformer and is configured to control the on or off of the switch of the flyback converter based on the control voltage.

[0015] In some embodiments, the method also includes: detecting a ringing period of the primary voltage; outputting a ringing signal in response to the ringing period of the primary voltage; comparing the control voltage with the predetermined threshold and outputting a first comparator signal when the control voltage is lower than the predetermined threshold; and outputting the low power consumption mode entry signal based at least on the first comparator signal and the ringing signal.

[0016] In some embodiments, the method further includes: outputting a switch clock signal based on the control voltage; and generating a switch signal that turns on or off the switch based at least on the switch clock signal.

[0017] In some embodiments, the method further includes: timing the duration of the first comparator signal; outputting a first signal when the timing time exceeds a first predetermined time length; and outputting the low power mode entry signal based at least on the first signal and a switching clock signal.

[0018] In some embodiments, the method further includes: outputting an exit low power mode signal based on the switch clock signal, the one or more power consumption components being enabled in response to the exit low power mode signal.

[0019] In some embodiments, the method also includes: outputting a wake-up signal based on the switching clock signal; outputting the wake-up signal in response to receiving the switching clock signal delayed by a second predetermined time; and generating a switching signal to turn on the switch based at least on the wake-up signal after the second predetermined time period after the one or more power consumption components are enabled.

[0020] In some embodiments, the method further includes: delaying a second predetermined time in response to receiving the switching clock signal; and outputting the wake-up signal after the delay of the second predetermined time.

[0021] According to a third aspect of the present disclosure, a flyback converter is provided, comprising a control circuit according to any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by referring to the accompanying drawings and reading the following detailed description. In the accompanying drawings, several embodiments of the present disclosure are shown by way of example and not limitation.

[0023] Figure 1 A schematic circuit diagram of a flyback converter according to a first embodiment of the present disclosure is shown.

[0024] Figure 2 A schematic circuit diagram of a flyback converter according to a second embodiment of the present disclosure is shown.

[0025] Figure 3 The waveform diagram of main signals according to the first embodiment of the present disclosure is shown.

[0026] Figure 4 A flow chart of a method for operating a flyback converter according to an embodiment of the present disclosure is shown.

[0027] In the various drawings, the same or corresponding reference numerals represent the same or corresponding parts. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0029] As mentioned above, in a light load or no-load mode, a traditional converter operates at a low switching frequency (e.g., the lowest switching frequency); however, even if the converter operates at a low frequency, the internal energy-consuming components of the converter itself continue to operate, which will reduce the energy efficiency of the system. In some solutions, a synchronous rectification circuit is provided on the secondary side of the transformer, and after the synchronous rectification circuit detects that the load voltage is lower than a certain value, information is sent from the secondary side of the transformer to the primary side of the transformer to instruct the primary side to shut down the working module to reduce standby power consumption. This solution can reduce the standby power consumption of the system without sacrificing the dynamic adjustment of the load output voltage, but it significantly increases the complexity of the system structure, resulting in high system cost and complex control.

[0030] According to the present disclosure, a converter is provided, which can realize light load or no-load control of the converter with a simple structure, which reduces the cost of the system and improves the energy efficiency of the system. The converter according to the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0031] Figure 1 FIG. 2 shows a schematic circuit diagram of a flyback converter according to a first embodiment of the present disclosure. Figure 1 As shown, the flyback converter 1 includes a transformer T, a switch M1 and a first control circuit 10. The transformer T includes a primary side suitable for connecting to a power source Vin and a secondary side suitable for connecting to a load Ro. The switch M1 is connected in series with the primary side of the transformer T. In the illustrated embodiment, the switch M1 is a transistor, and the switch M1 may also be other types of switches. The first control circuit 10 is arranged on the primary side and is configured to control the on or off of the switch M1 based on the control voltage Vcomp.

[0032] In some embodiments, the first control circuit 10 may include a resistor RFB, which may be set in the base loop of the switch M1 and obtain the primary voltage Vsw of the transformer T when the switch M1 is turned off. Since the primary voltage Vsw is proportional to the load voltage Vout, the load voltage Vout can be determined based on the primary voltage Vsw. The first control circuit 10 may also include a sampling circuit 11, which is configured to sample the primary voltage Vsw and convert the primary voltage Vsw into a digital signal VFB. Compensation may be performed by an error amplifier (EA) to determine the control voltage Vcomp.

[0033] The first control circuit 10 may include an oscillating circuit 18. The oscillating circuit 18 may output a switching clock signal Clock based on the control voltage Vcomp. The switching clock signal Clock may be output to the logic circuit 14. The control voltage Vcomp determines the peak current and the switching frequency. The logic circuit 14 is configured to generate a switching signal that turns the switch M1 on or off based at least on the switching clock signal Clock.

[0034] In some embodiments, Figure 1 As shown, the first control circuit 10 further includes a current sensing unit and a second comparator 16. The current sensing unit can sense the current flowing through the primary side when the switch M1 is turned on. The second comparator 16 can compare the current flowing through the primary side of the transformer T obtained when the switch M1 is turned off with the primary current sensed when the switch M1 is turned on. In some embodiments, the current flowing through the primary side of the transformer T obtained when the switch M1 is turned off can be derived from the primary voltage Vsw. The comparison result can be output to the logic circuit 14.

[0035] In some embodiments, Figure 1 As shown, the first control circuit 10 further includes a ringing detection circuit 12. The ringing detection circuit 12 is configured to detect the ringing of the primary voltage Vsw. The logic circuit 14 is configured to generate a switching signal that turns on or off the switch M1 based on the comparison result of the second comparator 16 and / or the ringing of Vsw. Thus, the first control circuit 10 can dynamically adjust the switching frequency of the switch M1 based on the power change of the load.

[0036] In some embodiments, Figure 1 As shown, the flyback converter 1 further includes a second control circuit 20. The second control circuit 20 is arranged on the primary side and is configured to output a low power mode entry signal Low_Power_SD based on the control voltage Vcomp being lower than a predetermined threshold.

[0037] The low power mode entry signal Low_Power_SD is output to one or more power consumption components in the first control circuit 10, so that the one or more power consumption components are disabled in response to the low power mode entry signal Low_Power_SD. In the illustrated embodiment, the low power mode entry signal Low_Power_SD is output to the sampling circuit 11, the second comparator 16, and the ringing detection circuit 12. It should be understood that this is merely exemplary, and the low power mode entry signal Low_Power_SD can be output to one of the above power consumption components or other power consumption components of the first control circuit 10, such as the current comparator, sampling circuit, and partial power consumption buffer of the first control circuit 10.

[0038] In some embodiments, Figure 1 As shown, the second control circuit 20 may include a first comparator 22 and an entry and exit low power consumption logic circuit 24. The first comparator 22 is configured to compare the control voltage Vcomp with a predetermined threshold and output a first comparator signal when the control voltage Vcomp is lower than the predetermined threshold. The entry and exit low power consumption logic circuit 24 is configured to output a low power consumption mode entry signal Low_Power_SD based at least on the switching clock signal Clock and the first comparator signal.

[0039] The in-out low power logic circuit 24 can work periodically based on the switch clock signal Clock. In some embodiments, for each switch clock signal Clock, the in-out low power logic circuit 24 can judge the output from the first comparator 22; in response to the signal from the first comparator 22 indicating that the load power is lower than the predetermined threshold, the low power mode signal Low_Power_SD is output, so that the power consumption components of the first control circuit 10 stop working. When the next switch clock signal Clock arrives, the in-out low power logic circuit 24 re-judges to determine whether to output the low power mode signal Low_Power_SD.

[0040] In some embodiments, Figure 1 As shown, the entry and exit low power logic circuit 24 may also include a timer 242, which is configured to: time the duration of the comparator signal from the first comparator 22, and output a first signal in response to the timing time exceeding a first predetermined time length, and the first signal allows the entry and exit low power logic circuit 24 to output an entry low power mode signal Low_Power_SD.

[0041] According to the present disclosure, when the Vcomp value reflecting the load information is lower than a certain set threshold value Vref, the comparator 22 outputs a comparator signal. The timer 242 counts the comparator signal. If Vcomp is lower than Vref for multiple consecutive counting cycles, it is determined to enter the low power mode, thereby allowing the output of the low power mode entry signal Low_Power_SD. In some embodiments, the timer 242 is also configured to output a second signal in response to the timing time not exceeding the first predetermined time length, and the second signal prevents the entry and exit low power logic circuit 24 from outputting the low power mode entry signal Low_Power_SD. By setting a waiting time for multiple counting cycles, it is avoided that the low power mode is mistakenly entered during the normal high load operation by fast load switching.

[0042] Figure 2 A schematic circuit diagram of a flyback converter according to a second embodiment of the present disclosure is shown. Figure 2 The structure of the flyback converter shown in Figure 1 The structure of the flyback converter shown is similar and like components are denoted by like reference numerals.

[0043] The low power logic circuit 24 is configured to output a low power mode exit signal based on the switch clock signal Clock. As an example, the low power logic circuit 24 can output a low power mode exit signal based on the next switch clock signal Clock. One or more power consumption components of the first control circuit 10 are enabled in response to the exit low power mode signal. During the next switch clock signal Clock, since the power consumption components of the first control circuit 10 that were originally turned off are awakened and restarted, and by turning on the switch M1, the operation of the converter is not affected in any way. In some embodiments, when the low power mode signal Low_Power_SD is at a high level, the exit low power mode signal can be achieved by resetting Low_Power_SD to a low level signal, and vice versa.

[0044] In some embodiments, Figure 2 As shown, the second control circuit 20 may further include a wake-up circuit 26. The wake-up circuit 26 is configured to operate based on the switch clock signal Clock. In some embodiments, the wake-up circuit 26 is configured to receive the switch clock signal Clock and output a wake-up signal Wake_up. Figure 2 As shown, the wake-up circuit 26 may further include a delay circuit 262. The delay circuit 262 is configured to output a wake-up signal Wake_up after a second predetermined time delay in response to receiving the switch clock signal Clock. Through the delay circuit 262, it can be coordinated with the switch clock signal Clock to allow enough time for the power consumption components of the first control circuit 10 that were originally turned off to restore their working state. The logic circuit 14 can be configured to further output an M1 turn-on signal based on the wake-up signal Wake_up. Through the delay circuit, the converter can maintain normal operation when the next switch clock signal Clock arrives, ensuring that the switch M1 can be turned on normally.

[0045] Figure 3 The waveform diagram of the main signals according to the first embodiment of the present disclosure shows the timing diagram of the low power mode signal relative to other signals during the operation of entering and exiting the low power logic circuit 24.

[0046] like Figure 3As shown, in response to the first switch clock signal Clock, the switch M1 is turned on, and the converter works normally. This stage corresponds to the transformer excitation stage and the transformer demagnetization stage, and the energy-consuming components of the first control circuit remain in normal operation. During the period when the switch M1 is turned off, the comparator 22 detects that the Vcomp value is lower than the set threshold Vref and outputs a comparator signal. When the Vsw voltage ringing is detected, the low-power logic circuit 24 outputs a low-power mode entry signal Low_Power_SD. The power-consuming components of the first control circuit 10 are turned off in response to the low-power mode entry signal Low_Power_SD. During the time period when the low-power mode entry signal Low_Power_SD maintains a high level, the power-consuming components of the first control circuit 10 remain turned off. According to the present disclosure, only when the switch M1 is turned off, part of the circuit is turned off; it will not affect the operation of the converter when the switch M1 is turned on.

[0047] When the next switch clock signal Clock arrives, the low power consumption logic circuit 24 outputs a signal to exit the low power consumption mode in response to the switch clock signal Clock. As a result, the power consumption components of the first control circuit 10 that were originally turned off are awakened and restarted, and the operation of the converter is not affected in any way. In some embodiments, the wake-up circuit 26 outputs a wake-up signal Wake_up based on the next switch clock signal Clock. The logic circuit 14 can generate a switch signal that turns on the switch M1 in response to the wake-up signal Wake_up, so that the switch M1 is turned on normally. In some embodiments, the wake-up signal Wake_up can be sent after a predetermined time delay, so that the switch M1 is turned on after a certain time delay after one or more power consumption components are enabled.

[0048] When the switch M1 is turned off, the operation of the second control circuit 20 is similar to that during the aforementioned first switch clock signal Clock. In particular, the comparator 22 detects that the Vcomp value is lower than the set threshold Vref and outputs a comparator signal, and when the Vsw voltage ringing is detected, the low power logic circuit 24 outputs a low power mode signal Low_Power_SD, so that the power consumption components of the first control circuit 10 are turned off, thereby significantly reducing energy consumption.

[0049] According to the present disclosure, during heavy loads, the converter operates in QR mode; when the load drops below a predetermined threshold, it enters a low power mode. In low power mode, during the transformer excitation and demagnetization stages, all modules of the converter operate normally, and during the Vsw ringing period, some power-consuming module circuits that do not affect the normal operation of the converter are selectively turned off to achieve the purpose of reducing the quiescent current. When the load exceeds the predetermined threshold, the low power mode is exited to ensure normal QR mode operation. Since during the cut-off period of switch M1, by selectively turning off some power-consuming module circuits that do not affect the normal operation of the converter, the quiescent current in the converter can be greatly reduced, the energy efficiency of the system can be greatly improved. In particular, when the converter operates at a lower frequency and a longer ringing period, the quiescent current of the converter will be reduced more significantly.

[0050] Figure 4 FIG. 1 is a flow chart showing a method 100 for operating a flyback converter according to an embodiment of the present disclosure. Figure 4 As shown, further combined Figure 1 and 2 At box 102, a low power mode entry signal Low_Power_SD is output based on that the control voltage Vcomp of the flyback converter 1 is lower than a predetermined threshold. The control voltage Vcomp is generated based on the primary voltage Vsw of the transformer T of the flyback converter 1 sensed when the switch M1 of the flyback converter 1 is turned off. At box 104, the low power mode entry signal Low_Power_SD is output to one or more power consumption components in the first control circuit 10 of the flyback converter 1, so that the one or more power consumption components are disabled in response to the low power mode entry signal Low_Power_SD. The first control circuit 10 is set at the primary side of the transformer T and is configured to control the conduction or cut-off of the switch M1 of the flyback converter 1 based on the control voltage Vcomp.

[0051] In some embodiments, the method may further include: comparing the control voltage Vcomp with a predetermined threshold; outputting a first comparator signal in response to the control voltage Vcomp being lower than the predetermined threshold; and outputting a low power mode entry signal Low_Power_SD based at least on the switching clock signal Clock and the first comparator signal, wherein the first control circuit 10 includes an oscillation circuit 18 configured to output a switching clock signal Clock based on the control voltage Vcomp.

[0052] In some embodiments, the method may further include: timing a duration of the first comparator signal; and outputting a first signal in response to the timing time exceeding a first predetermined time length, the first signal allowing output of a low power mode entry signal Low_Power_SD.

[0053] In some embodiments, the method may further include: detecting ringing of the primary voltage Vsw; outputting a ringing signal Ring in response to the ringing of the primary voltage Vsw; and outputting a low power mode entry signal Low_Power_SD based at least on the ringing signal Ring.

[0054] In some embodiments, the method may further include: outputting a wake-up signal Wake_up in response to the switching clock signal Clock of the next cycle; and outputting an exit low power mode signal based on the wake-up signal Wake_up, wherein one or more power consumption components are enabled in response to the exit low power mode signal.

[0055] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0056] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0057] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A control circuit for a flyback converter (1), the flyback converter comprising: A transformer (T) comprising a primary side adapted to be connected to a power source (Vin) and a secondary side adapted to be connected to a load (Ro); a switch (M1) connected in series with the primary side at a node; The control circuit comprises: A first control circuit (10) configured to control the switch (M1) to be turned on or off based on a control voltage (Vcomp), wherein the control voltage (Vcomp) is generated based on a primary voltage (Vsw) sensed at the node when the switch (M1) is turned off; The second control circuit (20) is configured to output a low power mode entry signal (Low_Power_SD) based on the control voltage (Vcomp) being lower than a predetermined threshold, wherein the low power mode entry signal (Low_Power_SD) is output to one or more power consumption components in the first control circuit (10), so that the one or more power consumption components are disabled in response to the low power mode entry signal (Low_Power_SD).

2. The control circuit according to claim 1, wherein The first control circuit (10) further comprises a ringing detection circuit (12) configured to output a ringing signal (Ring) in response to detecting a ringing period of the primary voltage (Vsw); and The second control circuit (20) further comprises a first comparator (22), wherein the first comparator (22) is configured to compare the control voltage (Vcomp) with the predetermined threshold value and output a first comparator signal when the control voltage (Vcomp) is lower than the predetermined threshold value; the second control circuit outputs the low power mode entry signal (Low_Power_SD) based at least on the first comparison signal and the ringing signal (Ring).

3. The control circuit according to claim 1 or 2, wherein the first control circuit (10) comprises: an oscillator circuit (18) configured to output a switching clock signal (Clock) based on the control voltage (Vcomp); as well as The logic circuit (14) is configured to generate a switch signal for turning on or off the switch (M1) based at least on the switch clock signal (Clock).

4. The control circuit according to claim 3, wherein the second control circuit (20) comprises: An entry and exit low power consumption logic circuit (24), the entry and exit low power consumption logic circuit (24) comprising a timer (242), the timer (242) being configured to: time the duration of the first comparator signal, and output a first signal in response to the timed duration exceeding a first predetermined time length, the entry and exit low power consumption logic circuit (24) outputting the entry low power consumption mode signal (Low_Power_SD) based at least on the first signal and a switch clock signal.

5. The control circuit according to claim 4, wherein The low power consumption entry and exit logic circuit (24) is configured to output an exit low power consumption mode signal based on the switch clock signal, and the one or more power consumption components are enabled in response to the exit low power consumption mode signal.

6. The control circuit according to claim 5, wherein the second control circuit (20) further comprises a wake-up circuit (26), wherein the wake-up circuit (26) is configured to output a wake-up signal (Wake_up) based on the switching clock signal (Clock); The wake-up circuit (26) comprises a delay circuit (262), wherein the delay circuit (262) is configured to: output the wake-up signal (Wake_up) in response to receiving the switching clock signal (Clock) after a delay of a second predetermined time; The logic circuit (14) is configured to generate a switch signal for turning on the switch (M1) based at least on the wake-up signal (Wake_up) after the second predetermined period of time after the one or more power consumption components are enabled.

7. The control circuit according to any one of claims 1-2, 4-6, wherein the first control circuit (10) further comprises at least one of the following: A sampling circuit (11) is configured to sample the primary voltage (Vsw); a second comparator (16) configured to compare a current derived from the control voltage (Vcomp) with a primary current sensed when the switch (M1) is turned on; The ringing detection circuit (12) is configured to detect the ringing of the primary voltage (Vsw) and output a ringing signal.

8. The control circuit according to claim 7, wherein the low power mode entry signal (Low_Power_SD) is output to at least one of the sampling circuit (11), the second comparator (16) and the ringing detection circuit (12).

9. A control method for a flyback converter (1), comprising: Outputting a low power mode entry signal (Low_Power_SD) based on a control voltage (Vcomp) of the flyback converter (1) being lower than a predetermined threshold, wherein the control voltage (Vcomp) is generated based on a primary voltage (Vsw) sensed at a node connected in series with the primary side of the switch (M1) when the switch (M1) of the flyback converter (1) is turned off; and The low power mode entry signal (Low_Power_SD) is output to one or more power consumption components in a first control circuit (10) of the flyback converter (1), so that the one or more power consumption components are disabled in response to the low power mode entry signal (Low_Power_SD), wherein the first control circuit (10) is arranged on the primary side of the transformer (T) and is configured to control the on or off state of a switch (M1) of the flyback converter (1) based on the control voltage (Vcomp).

10. The method according to claim 9, further comprising: Detecting a ringing period of the primary voltage (Vsw); In response to the ringing period of the primary voltage (Vsw), output a ringing signal (Ring); comparing the control voltage (Vcomp) with the predetermined threshold and outputting a first comparator signal when the control voltage (Vcomp) is lower than the predetermined threshold; as well as The low power mode entry signal (Low_Power_SD) is output based on at least the first comparator signal and the ringing signal (Ring).

11. The method according to claim 9 or 10, further comprising: Outputting a switching clock signal (Clock) based on the control voltage (Vcomp); as well as A switch signal for turning on or off the switch (M1) is generated based at least on the switch clock signal (Clock).

12. The method according to claim 11, further comprising: timing the duration of the first comparator signal; outputting a first signal in response to the timing time exceeding a first predetermined time length; as well as The low power mode entry signal (Low_Power_SD) is output based on at least the first signal and a switching clock signal.

13. The method according to any one of claims 9, 10, and 12, further comprising: Based on outputting an exit low power mode signal at the switching clock signal, the one or more power consumption components are enabled in response to the exit low power mode signal.

14. The method according to claim 13, further comprising: Outputting a wake-up signal (Wake_up) based on the switching clock signal (Clock); In response to receiving the switching clock signal (Clock) delayed by a second predetermined time, outputting the wake-up signal (Wake_up); After the second predetermined period of time after the one or more power consumption components are enabled, a switch signal is generated to turn on the switch (M1) based at least on the wake-up signal (Wake_up).

15. A flyback converter, comprising the control circuit according to any one of claims 1 to 8.

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