Decimal frequency multiplication delay phase-locked loop based on sigma-delta modulator

Abstract

The invention discloses a decimal frequency multiplication delay phase-locked loop based on a sigma-delta modulator, and the decimal frequency multiplication delay phase-locked loop is characterized in that a logic selection signal generation module provides a logic selection signal sel to control the opening and closing of a voltage-controlled oscillator (VCO) loop so as to control the periodic switching of the decimal frequency multiplication delay phase-locked loop between a Fractional-N PLL mode and a DLL mode; a Fractional-N PLL mode is periodically switched to a DLL mode, so that a clean reference clock rising edge is periodically introduced, and the rising edge of an output clock is replaced by the clean reference clock rising edge, so that the jitter of the output clock is reduced, and meanwhile, the frequency resolution of the output clock is improved; and fractional frequency multiplication is realized by introducing a programmable frequency divider based on a sigma-delta modulator. Furthermore, the logic selection signal generation module provided by the invention has a logic self-recovery function, and can solve the problem that normal locking cannot be realized in a decimal frequency multiplication process.

Description

Technical Field

[0001] The invention belongs to the field of laser radar applications, and in particular relates to a fractional frequency delay phase-locked loop based on a Σ-Δ modulator. Background Art

[0002] The continuous progress of laser technology has promoted the development of LiDAR systems. In LiDAR, TDC (Time-to-Digital Converter) chips are the core devices for high-precision ranging and object detection. LiDAR detects the distance and position of an object by emitting laser pulses and measuring the time difference between them reflected from the target object. The TDC chip plays a key role in accurately measuring the time difference in this process. The main function of the TDC chip is to convert the time delay of the laser pulse signal into a digital signal, thereby providing a basis for measuring the distance between the object and the LiDAR. Modern LiDAR systems require a time resolution of picoseconds, which requires the TDC chip to have extremely high precision. The current third-generation vernier TDC has high-precision performance, but its accuracy depends on the clock frequency resolution, so a clock generation circuit that can generate a clock signal with low jitter and high frequency resolution indicators is required.

[0003] The existing MDLL (multiplier delay phase-locked loop) has two working modes, one is PLL (phase-locked loop) mode, and the other is DLL (delay locked loop) mode. MDLL can introduce a clean reference clock rising edge to eliminate clock jitter by switching the working mode. The working mode of MDLL can be switched by controlling the closing and opening of the loop of the ring voltage-controlled oscillator in MDLL. When the loop is closed, MDLL works in PLL mode, the ring voltage-controlled oscillator works normally, and the output clock jitter accumulates continuously. When the loop is disconnected, MDLL works in DLL mode, the output clock rising edge is replaced by the introduced clean reference clock rising edge, and the clock jitter accumulated in PLL mode is cleared.

[0004] For the existing frequency multiplication delay phase-locked loop, since it switches to DLL mode to introduce a clean reference clock rising edge when each reference clock rising edge comes, each reference clock cycle corresponds to an integer number of output clock cycles, so that the existing frequency multiplication delay phase-locked loop can only achieve integer frequency multiplication and cannot achieve fractional frequency multiplication. The clock signal after integer frequency multiplication has a lower output clock frequency resolution and cannot meet more flexible and diversified applications. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a fractional frequency delay phase-locked loop based on a Σ-Δ modulator. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0006] The present invention provides a fractional frequency delay phase-locked loop based on a Σ-Δ modulator, comprising:

[0007] Logic selection signal generating module, phase frequency detector PFD, charge pump CP, filter LPF, voltage controlled oscillator VCO, first single-ended to differential module, second single-ended to differential module, first PN+S counter, second PN+S counter, programmable frequency divider based on Σ-Δ modulator, selector MUX1, selector MUX2; wherein,

[0008] The logic selection signal generating module has a logic self-recovery function, and is used to control the fractional frequency delay phase-locked loop to work periodically; within a cycle, the fractional frequency delay phase-locked loop works in the Fractional-NPLL mode or the DLL mode in turn;

[0009] In the Fractional-N PLL mode, the logic selection signal generating module outputs a high-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential module converts the logic selection signal sel into a signal sel+ and a signal sel-; the selector MUX1 outputs the reference clock CLKREF as the input signal CLK_IN under the control of the signal sel+; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF, under the control of the signal sel+ and the signal sel-, acts as a low-pass filter to filter out the high-frequency noise signal in the charge and discharge current, and outputs the control voltage Vctrl; the voltage-controlled oscillator VCO, under the control of the signal sel+ and the signal sel-, closes the VCO loop, and generates the output clock CLKOUT according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the programmable frequency divider based on the Σ-Δ modulator outputs the feedback signal CLK_O according to the output clock CLKOUT; the selector MUX2, under the control of the signal sel+, transmits the feedback signal CLK_O to the phase frequency detector PFD;

[0010] In the DLL mode, the logic selection signal generating module outputs a low-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential conversion module converts the logic selection signal sel into a signal sel+ and a signal sel-; the first PN+S counter obtains a first counting signal according to the reference clock CLKREF, and the selector MUX1 outputs the first counting signal as the input signal CLK_IN under the control of the signal sel+, thereby completing the introduction of a clean reference clock to eliminate the problem of the Fractional-N Jitter in PLL mode; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF acts as a single capacitor filter under the control of the signal sel+ and the signal sel-, and outputs a control voltage Vctrl according to the charge and discharge current; the voltage-controlled oscillator VCO is disconnected from the VCO loop under the control of the signal sel+ and the signal sel-, and generates a clean reference clock as the output clock CLKOUT according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the second PN+S counter outputs a feedback signal CLK_O according to the output clock CLKOUT; the selector MUX2 transmits the feedback signal CLK_O to the phase frequency detector PFD under the control of the signal sel+.

[0011] In one embodiment of the present invention, within a cycle, the fractional delay locked loop operates in the Fractional-N PLL mode or the DLL mode in sequence, including:

[0012] The fractional delay phase-locked loop first operates in the Fractional-N PLL mode. When the output clock CLKOUT passes the Nth falling edge and the output clock CLKOUT becomes a low level, the fractional delay phase-locked loop switches to the DLL mode. When the reference clock CLKREF passes the Mth clock rising edge and the output clock CLKOUT is a high level, the fractional delay phase-locked loop switches to the Fractional-N PLL mode and enters the next cycle.

[0013] In one embodiment of the present invention, the logic selection signal generating module includes:

[0014] A third single-ended to differential conversion module, a buffer unit BUFFER, a D flip-flop DFF1, a D flip-flop DFF2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an XOR gate XOR, a PN+S counter 1, a PN+S counter 2, a MOS tube M01, a MOS tube M02, a MOS tube M03, a MOS tube M04 and a MOS tube M05; wherein,

[0015] The input end of the third single-ended to differential module is connected to the output end of the PN+S counter 2, the first output end is connected to the input end of the buffer unit BUFFER, and the second output end is connected to the CKN end of the D flip-flop DFF2;

[0016] The output end of the buffer unit BUFFER is connected to the CLK end of the D flip-flop DFF1;

[0017] The D terminal of the D flip-flop DFF1 is connected to its own QN terminal, and the Q terminal is connected to the first input terminal of the XOR gate XOR;

[0018] The D terminal of the D flip-flop DFF2 is connected to its own QN terminal, and the QN terminal is connected to the second input terminal of the XOR gate XOR;

[0019] The input end of the inverter INV1 is connected to the output clock CLKOUT, and the output end is connected to the input end of the PN+S counter 1;

[0020] The input end of the inverter INV2 is connected to the output end of the PN+S counter 1, and the output end is connected to the gate of the MOS tube M01;

[0021] The input end of the inverter INV3 is connected to the external reset signal rst_n, and the output end is connected to the rstn reset end of the PN+S counter 2;

[0022] The input end of the inverter INV4 is connected to the output end of the inverter INV5, and the output end is connected to the input end of the inverter INV5;

[0023] The input end of the inverter INV5 is connected to the drain of the MOS tube M02, and the output end serves as the output end of the logic selection signal generating module;

[0024] The output end of the XOR gate is connected to the rstn reset end of the PN+S counter 1;

[0025] The input end of the PN+S counter 2 is connected to the reference clock CLKREF, and the output end is connected to the gate of the MOS tube M04;

[0026] The source of the MOS tube M01 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M02;

[0027] The gate of the MOS tube M02 is connected to the output clock CLKOUT, and the drain is connected to the input end of the inverter INV5;

[0028] The source of the MOS tube M03 is connected to the drain of the MOS tube M04, the gate is connected to the gate of the MOS tube M02, and the drain is connected to the drain of the MOS tube M02;

[0029] The source of the MOS tube M04 is grounded, and the gate is connected to the output end of the PN+S counter 2;

[0030] The source of the MOS tube M05 is grounded, the gate is connected to the input end of the inverter INV3, and the drain is connected to the output end of the XOR gate XOR.

[0031] In one embodiment of the present invention, MOS transistor M01, MOS transistor M02, MOS transistor M03 and MOS transistor M04 constitute a tri-state gate; wherein,

[0032] The gate of the MOS tube M01 serves as the first input terminal of the tri-state gate;

[0033] The gate of the MOS tube M02 serves as the second input terminal of the tri-state gate, and the drain serves as the output terminal of the tri-state gate;

[0034] The gate of the MOS transistor M04 serves as the third input terminal of the tri-state gate.

[0035] In one embodiment of the present invention, a phase frequency detector (PFD) comprises:

[0036] A first D flip-flop, a second D flip-flop, a buffer, an AND gate, and a NOT gate; wherein,

[0037] The CLK terminal of the first D flip-flop is connected to the input signal CLK_IN, the D terminal is connected to the power supply voltage, the Q terminal is connected to the first input terminal of the AND gate, and the R terminal is connected to the R terminal of the second D flip-flop;

[0038] The CLK terminal of the second D flip-flop is connected to the feedback signal CLK_O, the D terminal is connected to the power supply voltage, the Q terminal is connected to the second input terminal of the AND gate, and the R terminal is connected to the output terminal of the buffer;

[0039] The input end of the buffer is connected to the output end of the AND gate;

[0040] The input end of the NOT gate is connected to the first input end of the AND gate, and the output end serves as the first output end of the PFD;

[0041] The second input terminal of the AND gate serves as the second output terminal of the phase frequency detector PFD.

[0042] In one embodiment of the present invention, the charge pump CP comprises:

[0043] A first current source I1, a second current source I2, a first switch and a second switch; wherein,

[0044] The input end of the first current source I1 is connected to the power supply voltage, and the output end is connected to the first end of the first switch;

[0045] The input end of the second current source I2 is connected to the second end of the second switch, and the output end is grounded;

[0046] The second end of the first switch is connected to the first end of the second switch, and the control end is connected to the first output end of the phase frequency detector PFD;

[0047] The first end of the second switch serves as the output end of the charge pump CP, and the control end is connected to the second output end of the phase frequency detector PFD.

[0048] In one embodiment of the present invention, the filter LPF comprises:

[0049] Resistor R1, resistor R2, capacitor C1, capacitor C2, capacitor C3 and transmission gate switch sw; wherein,

[0050] The first end of the resistor R1 is connected to the output end of the charge pump CP, and the second end is connected to the first end of the capacitor C1;

[0051] The first end of the resistor R2 is connected to the first end of the capacitor C2, and the second end is connected to the first end of the capacitor C3;

[0052] The second end of the capacitor C1 is grounded;

[0053] The first end of the capacitor C2 is connected to the first end of the resistor R1, and the second end is grounded;

[0054] The first end of the capacitor C3 serves as the output end of the filter LPF, and the second end is grounded;

[0055] The input end of the transmission gate switch sw is connected to the first end of the resistor R1, the output end is connected to the resistor R2, the first control end is connected to the signal sel+, and the second control end is connected to the signal sel-.

[0056] In one embodiment of the present invention, any single-ended to differential conversion module includes:

[0057] Buffer unit BUFFER1, buffer unit BUFFER2, buffer unit BUFFER3 and inverter INV; wherein,

[0058] The input end of the buffer unit BUFFER1 is connected to the input end of the inverter INV, and the output end is connected to the input end of the buffer unit BUFFER2;

[0059] The output end of the buffer unit BUFFER2 serves as the first output end of the single-ended to differential conversion module;

[0060] The input end of the inverter INV is used as the input end of the single-ended to differential module, and the output end is connected to the input end of the buffer unit BUFFER3;

[0061] The output end of the buffer unit BUFFER3 serves as the second output end of the single-ended to differential conversion module.

[0062] In one embodiment of the present invention, a voltage controlled oscillator VCO comprises:

[0063] Voltage-controlled delay unit 1, voltage-controlled delay unit 2, voltage-controlled delay unit 3 and voltage-controlled delay unit 4; wherein,

[0064] The input port inp1 of the voltage-controlled delay unit 1 is connected to the output port von of the voltage-controlled delay unit 4, the input port inn1 is connected to the output port vop of the voltage-controlled delay unit 4, the input port inp2 is connected to the signal CLK_IN+, the input port inn2 is connected to the signal CLK_IN-, the input port s is connected to the signal sel+, the input port sd is connected to the signal sel-, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 2, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 2;

[0065] The input port inp2 of the voltage-controlled delay unit 2 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 3, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 3;

[0066] The input port inp2 of the voltage-controlled delay unit 3 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 4, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 4;

[0067] The input port inp2 of the voltage-controlled delay unit 4 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, and the input port vt is connected to the external signal vt.

[0068] In one embodiment of the present invention, any one of the voltage-controlled delay unit 1, the voltage-controlled delay unit 2, the voltage-controlled delay unit 3 and the voltage-controlled delay unit 4 includes:

[0069] MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18; wherein,

[0070] The source of the MOS tube M1 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M5;

[0071] The source of the MOS tube M2 is connected to the source of the MOS tube M1, and the drain is connected to the source of the MOS tube M6;

[0072] The source of the MOS tube M3 is connected to the source of the MOS tube M2, and the drain is connected to the source of the MOS tube M7;

[0073] The source of the MOS tube M4 is connected to the source of the MOS tube M3, and the drain is connected to the source of the MOS tube M8;

[0074] The drain of the MOS tube M5 is connected to the drain of the MOS tube M9;

[0075] The drain of the MOS tube M6 is connected to the drain of the MOS tube M10;

[0076] The drain of the MOS tube M7 is connected to the drain of the MOS tube M11;

[0077] The drain of the MOS tube M8 is connected to the drain of the MOS tube M12;

[0078] The drain of the MOS tube M5 and the drain of the MOS tube M7 serve as the output port von of the voltage-controlled delay unit;

[0079] The drain of the MOS tube M6 and the drain of the MOS tube M8 serve as the output port vop of the voltage-controlled delay unit;

[0080] The source of the MOS tube M9 is connected to the drain of the MOS tube M13;

[0081] The source of the MOS tube M10 is connected to the drain of the MOS tube M14;

[0082] The source of the MOS tube M11 is connected to the drain of the MOS tube M15;

[0083] The source of the MOS tube M12 is connected to the drain of the MOS tube M16;

[0084] The source of the MOS tube M13 is connected to the drain of the MOS tube M17;

[0085] The source of the MOS tube M14 is connected to the source of the MOS tube M13;

[0086] The source of the MOS tube M15 is connected to the source of the MOS tube M14;

[0087] The source of the MOS tube M16 is connected to the source of the MOS tube M15;

[0088] The source of the MOS tube M17 is grounded;

[0089] The source of the MOS tube M18 is grounded, and the drain is connected to the source of the MOS tube M16;

[0090] The gate of the MOS tube M1 and the gate of the MOS tube M13 serve as the input port inp1 of the voltage-controlled delay unit;

[0091] The gate of the MOS tube M2 and the gate of the MOS tube M14 serve as the input port inn1 of the voltage-controlled delay unit;

[0092] The gate of the MOS tube M3 and the gate of the MOS tube M15 serve as the input port inp2 of the voltage-controlled delay unit;

[0093] The gate of the MOS tube M4 and the gate of the MOS tube M16 serve as the input port inn2 of the voltage-controlled delay unit;

[0094] The gate of the MOS tube M5, the gate of the MOS tube M6, the gate of the MOS tube M11 and the gate of the MOS tube M12 serve as the input port sn of the voltage-controlled delay unit;

[0095] The gate of the MOS transistor M7 , the gate of the MOS transistor M8 , the gate of the MOS transistor M9 and the gate of the MOS transistor M10 serve as the input port s of the voltage-controlled delay unit.

[0096] Beneficial effects of the present invention:

[0097] In the solution provided by the present invention, a logic selection signal generating module is used to provide a logic selection signal sel, and after the first single-ended to differential conversion module, a signal sel+ and a signal sel- are output to control the opening and closing of the voltage-controlled oscillator VCO loop, so as to realize the periodic switching of the fractional frequency delay phase-locked loop between the Fractional-N PLL mode and the DLL mode; by periodically switching from the Fractional-N PLL mode to the DLL mode, a clean reference clock rising edge is periodically introduced, and the rising edge of the output clock is replaced with a clean reference clock rising edge, thereby reducing the jitter of the output clock and improving the frequency resolution of the output clock; fractional frequency multiplication is realized by introducing a programmable frequency divider based on a Σ-Δ modulator. Furthermore, the logic selection signal generating module proposed by the present invention has a logic self-recovery function, which can solve the problem of failure to lock normally during the fractional frequency multiplication process. BRIEF DESCRIPTION OF THE DRAWINGS

[0098] Figure 1 A schematic diagram of the system structure of a fractional frequency delay phase-locked loop provided by an embodiment of the present invention;

[0099] Figure 2 A schematic diagram of the circuit structure of a logic selection signal generating module provided in an embodiment of the present invention;

[0100] Figure 3 A schematic diagram of the circuit structure of a Σ-Δ modulator provided in an embodiment of the present invention;

[0101] Figure 4 A schematic diagram of the circuit structure of a voltage-controlled oscillator VCO provided in an embodiment of the present invention;

[0102] Figure 5 A schematic diagram of the circuit structure of a voltage-controlled delay unit provided in an embodiment of the present invention;

[0103] Figure 6 A schematic diagram of the circuit structure of a single-ended to differential module provided in an embodiment of the present invention;

[0104] Figure 7A schematic diagram of a system equivalent circuit structure of a fractional delay locked loop in DLL mode provided by an embodiment of the present invention;

[0105] Figure 8 A schematic diagram of a system equivalent circuit structure of a fractional delay phase-locked loop in a Fractional-N PLL mode provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0106] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0107] The embodiment of the present invention provides a fractional frequency delay phase locked loop based on a Σ-Δ modulator, such as Figure 1 As shown, it may include:

[0108] Logic selection signal generating module, phase frequency detector PFD, charge pump CP, filter LPF, voltage controlled oscillator VCO, first single-ended to differential module, second single-ended to differential module, first PN+S counter, second PN+S counter, programmable frequency divider based on Σ-Δ modulator, selector MUX1, selector MUX2; wherein,

[0109] The logic selection signal generating module has a logic self-recovery function, and is used to control the fractional frequency delay phase-locked loop to work periodically; within one cycle, the fractional frequency delay phase-locked loop works in the Fractional-N PLL mode or the DLL mode in turn;

[0110] In the Fractional-N PLL mode, the logic selection signal generating module outputs a high-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential module converts the logic selection signal sel into a signal sel+ and a signal sel-; the selector MUX1 outputs the reference clock CLKREF as the input signal CLK_IN under the control of the signal sel+; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; under the control of the signal sel+ and the signal sel-, the filter LPF acts as a low-pass filter to filter out the high-frequency noise signal in the charge and discharge current and outputs the control voltage Vctrl; under the control of the signal sel+ and the signal sel-, the voltage-controlled oscillator VCO loop is closed, and the output clock CLKOUT is generated according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the programmable divider based on the Σ-Δ modulator outputs the feedback signal CLK_O according to the output clock CLKOUT; under the control of the signal sel+, the selector MUX2 transmits the feedback signal CLK_O to the phase frequency detector PFD.

[0111] In DLL mode, the logic selection signal generating module outputs a low-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential conversion module converts the logic selection signal sel into a signal sel+ and a signal sel-; the first PN+S counter obtains a first counting signal according to the reference clock CLKREF, and the selector MUX1 outputs the first counting signal as the input signal CLK_IN under the control of the signal sel+, thereby completing the introduction of a clean reference clock to eliminate the problem of the Fractional-N Jitter in PLL mode; the second single-ended to differential module converts the input signal CLK_IN into signals CLK_IN+ and CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF acts as a single capacitor filter under the control of the signal sel+ and the signal sel-, and outputs the control voltage Vctrl according to the charge and discharge current; the voltage-controlled oscillator VCO is disconnected from the VCO loop under the control of the signal sel+ and the signal sel-, and a clean reference clock is introduced as the output clock CLKOUT according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the second PN+S counter outputs the feedback signal CLK_O according to the output clock CLKOUT; the selector MUX2 transmits the feedback signal CLK_O to the phase frequency detector PFD under the control of the signal sel+.

[0112] It can be understood that in the Fractional-N PLL mode, in the first cycle, the output clock CLKOUT is at a low level and the feedback signal CLK_O is at a low level.

[0113] The embodiment of the present invention provides a fractional frequency delay phase-locked loop, which can output a low-jitter fractional frequency clock. Specifically, the phase frequency detector PFD can be used to detect the frequency difference and phase difference between the reference signal and the feedback signal, and can convert the frequency difference and phase difference of the two input signals into a pulse signal; the charge pump CP can convert the pulse signal output by the phase frequency detector PFD into a charge and discharge current; the filter LPF can convert the charge and discharge current output by the charge pump CP into a control voltage Vctrl and filter out the high-frequency noise signal therein. The logic selection signal generated by the logic selection signal generating module can control the opening and closing of the voltage-controlled oscillator VCO loop. When the loop is disconnected, the voltage-controlled oscillator VCO operates in the voltage-controlled delay chain mode VCDL, and when the loop is closed, the voltage-controlled oscillator VCO operates in the VCO mode. Each single-ended to differential module can convert the signal into two differential signals with a phase difference of 180 degrees. It can be understood that the PN+S counter proposed in the embodiment of the present invention can also be replaced by a programmable counter. Specifically, the corresponding counter can be selected according to the output frequency required by the fractional frequency delay phase-locked loop. When the output frequency range is high, such as the output frequency range is greater than 1GHz, the PN+S counter can be selected. When the output frequency range is low, such as the output frequency range is several hundred MHz, a simple programmable counter can be used to replace the PN+S counter. The signal sel+ can control the gating of the two-choice selectors MUX1 and MUX2. The transmission gate switch sw can switch the type of the filter LPF. The two-choice selectors MUX1 and MUX2 can change the transmission route of the reference clock CLKREF and the output clock CLKOUT. The signal sel+ and the signal sel- are generated by the logic selection signal sel through the first single-ended differential conversion module. When the signal sel+ is low level and the signal sel- is high level, the filter LPF is a low-pass filter composed of a single capacitor, and the reference clock CLKREF passes through the first PN+S counter to obtain the input signal CLK_IN, and the output clock CLKOUT passes through the second PN+S counter to obtain the feedback signal CLK_O. When the signal sel+ is high level and the signal sel- is low level, the filter LPF is a third-order low-pass filter composed of resistor R1, capacitor C1, capacitor C2, resistor R2 and capacitor C3. The reference clock CLKREF is directly used as the input signal CLK_IN, and the output clock CLKOUT passes through a programmable divider based on a Σ-Δ modulator to obtain the feedback signal CLK_O. In order to output a low-jitter clock, it is necessary to periodically introduce a clean reference clock rising edge and replace the rising edge of the output clock with a clean reference clock rising edge. In order to achieve fractional frequency multiplication, it is necessary to design a programmable divider based on a Σ-Δ modulator.The circuit structure adopted by the present invention not only periodically introduces a clean reference clock rising edge during operation, but also adopts a programmable frequency divider based on a Σ-Δ modulator, so that the circuit structure has two working modes, one is a fractional-frequency phase-locked loop mode Fractional-N PLL, and the other is a delay-locked loop mode DLL. The circuit structure can output a low-jitter fractional frequency clock by periodically switching the working mode.

[0114] For ease of understanding, the circuit structures of the main components of the fractional delay locked loop provided by the embodiment of the present invention are first introduced below.

[0115] Logic selection signal generation module

[0116] Logic selection signal generation module, such as Figure 2 As shown, it may include:

[0117] A third single-ended to differential conversion module, a buffer unit BUFFER, a D flip-flop DFF1, a D flip-flop DFF2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an XOR gate XOR, a PN+S counter 1, a PN+S counter 2, a MOS tube M01, a MOS tube M02, a MOS tube M03, a MOS tube M04 and a MOS tube M05; wherein,

[0118] The input end of the third single-ended to differential module is connected to the output end of the PN+S counter 2, the first output end is connected to the input end of the buffer unit BUFFER, and the second output end is connected to the CKN end of the D flip-flop DFF2;

[0119] The output end of the buffer unit BUFFER is connected to the CLK end of the D flip-flop DFF1;

[0120] The D terminal of the D flip-flop DFF1 is connected to its own QN terminal, and the Q terminal is connected to the first input terminal of the XOR gate XOR;

[0121] The D terminal of the D flip-flop DFF2 is connected to its own QN terminal, and the QN terminal is connected to the second input terminal of the XOR gate XOR;

[0122] The input end of the inverter INV1 is connected to the output clock CLKOUT, and the output end is connected to the input end of the PN+S counter 1;

[0123] The input end of the inverter INV2 is connected to the output end of the PN+S counter 1, and the output end is connected to the gate of the MOS tube M01;

[0124] The input end of the inverter INV3 is connected to the external reset signal rst_n, and the output end is connected to the rstn reset end of the PN+S counter 2;

[0125] The input end of the inverter INV4 is connected to the output end of the inverter INV5, and the output end is connected to the input end of the inverter INV5;

[0126] The input end of the inverter INV5 is connected to the drain of the MOS tube M02, and the output end serves as the output end of the logic selection signal generating module;

[0127] The output terminal of the XOR gate is connected to the rstn reset terminal of the PN+S counter 1;

[0128] The input end of the PN+S counter 2 is connected to the reference clock CLKREF, and the output end is connected to the gate of the MOS tube M04;

[0129] The source of the MOS tube M01 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M02;

[0130] The gate of the MOS tube M02 is connected to the output clock CLKOUT, and the drain is connected to the input end of the inverter INV5;

[0131] The source of the MOS tube M03 is connected to the drain of the MOS tube M04, the gate is connected to the gate of the MOS tube M02, and the drain is connected to the drain of the MOS tube M02;

[0132] The source of the MOS tube M04 is grounded, and the gate is connected to the output end of the PN+S counter 2;

[0133] The source of the MOS tube M05 is grounded, the gate is connected to the input end of the inverter INV3, and the drain is connected to the output end of the XOR gate XOR.

[0134] Among them, MOS tube M01, MOS tube M02, MOS tube M03 and MOS tube M04 constitute a three-state gate; among them,

[0135] The gate of the MOS tube M01 serves as the first input terminal of the tri-state gate;

[0136] The gate of the MOS tube M02 serves as the second input terminal of the tri-state gate, and the drain serves as the output terminal of the tri-state gate;

[0137] The gate of the MOS tube M04 serves as the third input terminal of the tri-state gate.

[0138] Specifically, the logic selection signal generating module has a logic self-recovery function, and can generate a logic selection signal sel to switch the working mode of the fractional frequency delay phase-locked loop, thereby controlling the fractional frequency delay phase-locked loop to cycle periodically. First, the logic selection signal generating module needs to be reset. Since the PN+S counter 1 and the PN+S counter 2 are both reset at a low level, the width-to-length ratio of the MOS tube M05 can be made much larger than the width-to-length ratio of the PMOS tube in the XOR gate XOR; wherein, the MOS tube M01 and the MOS tube M02 are PMOS tubes, and the MOS tube M03, the MOS tube M04 and the MOS tube M05 are NMOS tubes. When the reset signal rst_n is at a high level, the output terminals Q of the D flip-flops DFF1 and DFF2 are at a low level, the output terminals QN are at a high level, one input terminal of the XOR gate XOR is at a low level, and the other input terminal is at a high level. At this time, the width-to-length ratio of the MOS tube M05 is much greater than the width-to-length ratio of the PMOS tube in the XOR gate XOR, and the voltage at the reset terminal rstn of the PN+S counter 1 is discharged to a low level. The reset signal rst_n is at a high level and becomes a low level after passing through the inverter INV3. At this time, the reset terminal of the PN+S counter 1 and the reset terminal of the PN+S counter 2 are at a low level. Therefore, both the PN+S counter 1 and the PN+S counter 2 are in a reset state. When the reset signal rst_n is at a low level, the MOS tube M05 is disconnected, the output terminal of the inverter INV3 is at a high level, and the voltage at the reset terminal of the PN+S counter 1 is pulled up to a high level by the XOR gate XOR. Therefore, the reset terminal signals of PN+S counter 1 and PN+S counter 2 are both high level, and PN+S counter 1 and PN+S counter 2 are both in working state. At this time, the logic selection signal generating module is in working mode. When setting specifically, the count values ​​M and N of PN+S counter 1 and PN+S counter 2 can be set according to the required output clock resolution and fractional multiple number, and M and N can be positive integers; wherein, the fractional multiple number Zf, the count value M and the count value N need to satisfy f / 10=N / M. When the reference clock CLKREF passes through M clock rising edges and the output clock CLKOUT becomes high level, the gate voltage of MOS tube M04 changes from low level to high level, MOS tube M04 and MOS tube M03 are turned on, and the voltage at the output end of the logic selection signal generating module is discharged to low level, and the fractional multiple delay phase-locked loop is controlled to switch to DLL mode. When the output clock CLKOUT passes through the Nth falling edge, the output clock CLKOUT changes from a high level to a low level, the gate voltage of the MOS tube M01 changes from a high level to a low level, the MOS tube M01 and the MOS tube M02 are turned on, and the voltage at the output end of the logic selection signal generating module is charged to a high level, controlling the fractional frequency delay phase-locked loop to switch to the Fractional-N PLL mode.

[0139] Furthermore, the logic selection signal generating module proposed in the embodiment of the present invention has a logic self-recovery function, by which the generated logic selection signal can be prevented from having logic errors. The correct logic should be that when the Mth reference clock rising edge arrives, the output end logic selection signal sel is discharged to a low level, and when the Nth output signal falling edge arrives, the output end logic selection signal sel is charged to a high level. The fluctuation on the control voltage Vctrl may cause the actual output frequency to be less than the ideal output frequency, so that the Nth CLKOUT rising edge phase lags behind the Mth reference clock rising edge. In this case, when the Nth CLKOUT rising edge arrives, if the reference clock CLKREF is at a high level, the output end logic selection signal sel is always at a low level; if the reference clock CLKREF is at a low level, the 2Mth reference clock rising edge will replace the Mth reference clock rising edge to complete the phase discrimination. This erroneous logic will greatly increase the locking time, and may even cause the entire system to fail to lock normally. When the Mth reference clock rising edge of the reference clock CLKREF arrives, the gate signal of the MOS tube M04 rises from a low level to a high level. At this time, the same direction end and the reverse direction end of the third single-ended to differential module output a rising edge signal and a falling edge signal respectively. Due to the existence of BUFFER, there is a phase difference between the rising edge and the falling edge received by the clock input end of the D flip-flop DFF1 and the D flip-flop DFF2. This phase difference causes a phase difference to exist at the output end of DFF1 and DFF2. Within this phase difference, the output of the XOR gate XOR is a low level. Since the output end of the XOR gate XOR is connected to the reset end rstn of the PN+S counter 1, when the output of the XOR gate XOR is a low level, the PN+S counter 1 is reset. Therefore, as long as the Mth reference clock rising edge of the reference clock CLKREF arrives, the PN+S counter 1 will be reset to restore the logic function to normal. During the recovery of the logic function, the working state of the logic selection signal generating module will not be affected. PN+S counter 2 is always in working state. When PN+S counter 2 outputs a rising edge signal, it will output a falling edge after a period of time. At this time, the same direction end of the third single-ended to differential module outputs a falling edge signal, and the reverse direction end outputs a rising edge signal. Since D flip-flop DFF1 is a rising edge trigger, and D flip-flop DFF2 is a falling edge trigger, these two D flip-flops will not respond to the output clock signal of the third single-ended to differential module. When PN+S counter 2 outputs a rising edge signal, the reset end rstn of PN+S counter 1 will briefly become a low level, and the rest of the time, the reset end rstn is a high level. Therefore, the logic selection signal generating module can realize the function of logic self-recovery.

[0140] Sigma-Delta Modulator in Programmable Frequency Divider

[0141] See the schematic diagram of the Σ-Δ modulator for details. Figure 3 ,from Figure 3 It can be seen that the Σ-Δ modulator can output a series of values ​​according to the input fractional value, and the average of the series of values ​​is equal to the integer part of the input fractional value. It can be understood that the frequency divider can be divided accordingly by the integer output by the Σ-Δ modulator.

[0142] Phase Frequency Detector (PFD)

[0143] Phase frequency detector PFD, such as Figure 1 As shown, it may include:

[0144] A first D flip-flop, a second D flip-flop, a buffer, an AND gate, and a NOT gate; wherein,

[0145] The CLK terminal of the first D flip-flop is connected to the input signal CLK_IN, the D terminal is connected to the power supply voltage, the Q terminal is connected to the first input terminal of the AND gate, and the R terminal is connected to the R terminal of the second D flip-flop;

[0146] The CLK terminal of the second D flip-flop is connected to the feedback signal CLK_O, the D terminal is connected to the power supply voltage, the Q terminal is connected to the second input terminal of the AND gate, and the R terminal is connected to the output terminal of the buffer;

[0147] The input terminal of the buffer is connected to the output terminal of the AND gate;

[0148] The input end of the NOT gate is connected to the first input end of the AND gate, and the output end serves as the first output end of the phase frequency detector PFD;

[0149] The second input terminal of the AND gate serves as the second output terminal of the phase frequency detector PFD.

[0150] The phase frequency detector PFD can be used to detect the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and output a pulse signal.

[0151] Charge Pump CP

[0152] Charge pump CP, such as Figure 1 As shown, it may include:

[0153] A first current source I1, a second current source I2, a first switch and a second switch; wherein,

[0154] An input end of the first current source I1 is connected to a power supply voltage, and an output end is connected to a first end of the first switch;

[0155] An input terminal of the second current source I2 is connected to the second terminal of the second switch, and an output terminal thereof is grounded;

[0156] The second end of the first switch is connected to the first end of the second switch, and the control end is connected to the first output end of the phase frequency detector PFD;

[0157] The first end of the second switch serves as the output end of the charge pump CP, and the control end is connected to the second output end of the phase frequency detector PFD.

[0158] The charge pump CP can be used to convert the pulse signal into a charge and discharge current output.

[0159] Filter LPF

[0160] Filter LPF, such as Figure 1 As shown, it may include:

[0161] Resistor R1, resistor R2, capacitor C1, capacitor C2, capacitor C3 and transmission gate switch sw; wherein,

[0162] A first end of the resistor R1 is connected to the output end of the charge pump CP, and a second end of the resistor R1 is connected to a first end of the capacitor C1;

[0163] The first end of the resistor R2 is connected to the first end of the capacitor C2, and the second end is connected to the first end of the capacitor C3;

[0164] The second end of the capacitor C1 is grounded;

[0165] A first end of the capacitor C2 is connected to a first end of the resistor R1, and a second end thereof is grounded;

[0166] A first end of the capacitor C3 is used as an output end of the filter LPF, and a second end thereof is grounded;

[0167] The input end of the transmission gate switch sw is connected to the first end of the resistor R1, the output end is connected to the resistor R2, the first control end is connected to the signal sel+, and the second control end is connected to the signal sel-.

[0168] The filter LPF can convert the charge and discharge current output by the charge pump CP into a control voltage Vctrl and filter out high-frequency noise signals therein.

[0169] Specifically, when the signal sel+ is a low level and the signal sel- is a high level, the filter LPF can be a low-pass filter composed of a single capacitor; when the signal sel+ is a high level and the signal sel- is a low level, the filter LPF can be a third-order low-pass filter composed of a resistor R1, a capacitor C1, a capacitor C2, a resistor R2 and a capacitor C3.

[0170] Voltage Controlled Oscillator VCO

[0171] Voltage controlled oscillator VCO, such as Figure 4 As shown, it may include:

[0172] Voltage-controlled delay unit 1, voltage-controlled delay unit 2, voltage-controlled delay unit 3 and voltage-controlled delay unit 4; wherein,

[0173] The input port inp1 of the voltage-controlled delay unit 1 is connected to the output port von of the voltage-controlled delay unit 4, the input port inn1 is connected to the output port vop of the voltage-controlled delay unit 4, the input port inp2 is connected to the signal CLK_IN+, the input port inn2 is connected to the signal CLK_IN-, the input port s is connected to the signal sel+, the input port sd is connected to the signal sel-, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 2, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 2;

[0174] The input port inp2 of the voltage-controlled delay unit 2 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 3, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 3;

[0175] The input port inp2 of the voltage-controlled delay unit 3 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 4, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 4;

[0176] The input port inp2 of the voltage-controlled delay unit 4 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, and the input port vt is connected to the external signal vt.

[0177] Specifically, the voltage controlled oscillator VCO is composed of a plurality of voltage controlled delay units, and the voltage controlled oscillator VCO can output a clock signal of a corresponding frequency according to the control voltage Vctrl. Under the control of the logic selection signal sel generated by the logic selection signal generating module, the voltage controlled oscillator VCO controls the opening and closing of its own VCO loop. When the loop is disconnected, the voltage controlled oscillator VCO operates in the voltage controlled delay chain VCDL mode, and when the loop is closed, the voltage controlled oscillator VCO operates in the VCO mode.

[0178] Any one of the voltage-controlled delay unit 1, the voltage-controlled delay unit 2, the voltage-controlled delay unit 3 and the voltage-controlled delay unit 4, such as Figure 5 As shown, all include:

[0179] MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18; wherein,

[0180] The source of the MOS tube M1 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M5;

[0181] The source of the MOS tube M2 is connected to the source of the MOS tube M1, and the drain is connected to the source of the MOS tube M6;

[0182] The source of the MOS tube M3 is connected to the source of the MOS tube M2, and the drain is connected to the source of the MOS tube M7;

[0183] The source of the MOS tube M4 is connected to the source of the MOS tube M3, and the drain is connected to the source of the MOS tube M8;

[0184] The drain of the MOS tube M5 is connected to the drain of the MOS tube M9;

[0185] The drain of the MOS tube M6 is connected to the drain of the MOS tube M10;

[0186] The drain of the MOS tube M7 is connected to the drain of the MOS tube M11;

[0187] The drain of the MOS tube M8 is connected to the drain of the MOS tube M12;

[0188] The drain of the MOS tube M5 and the drain of the MOS tube M7 serve as the output port von of the voltage-controlled delay unit;

[0189] The drain of the MOS tube M6 and the drain of the MOS tube M8 serve as the output port vop of the voltage-controlled delay unit;

[0190] The source of the MOS tube M9 is connected to the drain of the MOS tube M13;

[0191] The source of the MOS tube M10 is connected to the drain of the MOS tube M14;

[0192] The source of the MOS tube M11 is connected to the drain of the MOS tube M15;

[0193] The source of the MOS tube M12 is connected to the drain of the MOS tube M16;

[0194] The source of the MOS tube M13 is connected to the drain of the MOS tube M17;

[0195] The source of the MOS tube M14 is connected to the source of the MOS tube M13;

[0196] The source of the MOS tube M15 is connected to the source of the MOS tube M14;

[0197] The source of the MOS tube M16 is connected to the source of the MOS tube M15;

[0198] The source of the MOS tube M17 is grounded;

[0199] The source of the MOS tube M18 is grounded, and the drain is connected to the source of the MOS tube M16;

[0200] The gate of the MOS tube M1 and the gate of the MOS tube M13 serve as the input port inp1 of the voltage-controlled delay unit;

[0201] The gate of the MOS tube M2 and the gate of the MOS tube M14 serve as the input port inn1 of the voltage-controlled delay unit;

[0202] The gate of the MOS tube M3 and the gate of the MOS tube M15 serve as the input port inp2 of the voltage-controlled delay unit;

[0203] The gate of the MOS tube M4 and the gate of the MOS tube M16 serve as the input port inn2 of the voltage-controlled delay unit;

[0204] The gate of the MOS tube M5, the gate of the MOS tube M6, the gate of the MOS tube M11 and the gate of the MOS tube M12 serve as the input port sn of the voltage-controlled delay unit;

[0205] The gate of the MOS tube M7 , the gate of the MOS tube M8 , the gate of the MOS tube M9 and the gate of the MOS tube M10 serve as the input port s of the voltage-controlled delay unit.

[0206] Specifically, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7 and MOS tube M8 are all PMOS tubes; MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18 are all NMOS tubes. The signal received by the input port sn of the voltage-controlled delay unit controls the opening and closing of MOS tube M5, MOS tube M6, MOS tube M11 and MOS tube M12, and the signal received by the input port s of the voltage-controlled delay unit controls the opening and closing of MOS tube M7, MOS tube M8, MOS tube M9 and MOS tube M10. When the MOS tube M5, MOS tube M6, MOS tube M9 and MOS tube M10 are turned on, and the MOS tube M7, MOS tube M8, MOS tube M11 and MOS tube M12 are turned off, the MOS tube M1, MOS tube M13 and MOS tube M17 form an inverter delay unit controlled by the external voltage signal vt, and the MOS tube M2, MOS tube M14 and MOS tube M17 form an inverter delay unit controlled by the external voltage signal vt. When the MOS tube M7, MOS tube M8, MOS tube M11 and MOS tube M12 are turned on, and the MOS tube M5, MOS tube M6, MOS tube M9 and MOS tube M10 are turned off, the MOS tube M3, MOS tube M15 and MOS tube M18 form an inverter delay unit controlled by the external voltage signal vt, and the MOS tube M2, MOS tube M14 and MOS tube M18 form an inverter delay unit controlled by the external voltage signal vt. When the signal received at the input port s is at a high level and the signal received at the input port sn is at a low level, the signal received at the input port inp1 is transmitted to the output terminal von through the inverter delay unit composed of the MOS tube M1, the MOS tube M13 and the MOS tube M17, and the signal received at the input port inn1 is transmitted to the output terminal vop through the inverter delay unit composed of the MOS tube M2, the MOS tube M14 and the MOS tube M17. When the signal received at the input port s is at a low level and the signal received at the input port sn is at a high level, the signal received at the input port inp2 is transmitted to the output terminal von through the inverter delay unit composed of the MOS tube M3, the MOS tube M15 and the MOS tube M18, and the signal received at the input port inn2 is transmitted to the output terminal vop through the inverter delay unit composed of the PMOS tube M4, the NMOS tube M16 and the NMOS tube M18. The MOS tube M5 , MOS tube M6 , MOS tube M9 , MOS tube M10 , MOS tube M7 , MOS tube M8 , MOS tube M11 and MOS tube M12 inside the voltage-controlled delay unit play a role of logic selection.

[0207] Single-ended to differential module

[0208] Any single-ended to differential conversion module in the embodiments of the present invention, such as Figure 6 As shown, it may include:

[0209] Buffer unit BUFFER1, buffer unit BUFFER2, buffer unit BUFFER3 and inverter INV; wherein,

[0210] The input end of the buffer unit BUFFER1 is connected to the input end of the inverter INV, and the output end is connected to the input end of the buffer unit BUFFER2;

[0211] The output end of the buffer unit BUFFER2 serves as the first output end of the single-ended to differential conversion module;

[0212] The input end of the inverter INV is used as the input end of the single-ended to differential module, and the output end is connected to the input end of the buffer unit BUFFER3;

[0213] The output end of the buffer unit BUFFER3 serves as the second output end of the single-ended to differential conversion module.

[0214] It can be understood that the single-ended to differential module can be composed of three buffer units and an inverter, and the module can convert the input signal into a pair of differential signals with a phase difference of 180 degrees.

[0215] In order to more clearly illustrate the working process of the fractional frequency delay phase-locked loop provided by the embodiment of the present invention, the working principle of the fractional frequency delay phase-locked loop is specifically introduced below.

[0216] The fractional delay locked loop operates periodically under the control of the logic selection signal generating module. In one cycle, the fractional delay locked loop operates in the Fractional-N PLL mode or the DLL mode in turn, which may include:

[0217] The fractional delay phase-locked loop first works in the Fractional-N PLL mode. When the output clock CLKOUT passes the Nth falling edge and the output clock CLKOUT becomes low, the fractional delay phase-locked loop switches to the DLL mode. When the reference clock CLKREF passes the Mth clock rising edge and the output clock CLKOUT is high, the fractional delay phase-locked loop switches to the Fractional-N PLL mode and enters the next cycle. In this way, it works in two modes periodically.

[0218] DLL Mode

[0219] When the logic selection signal sel output by the logic selection signal generating module is at a low level, the fractional delay phase-locked loop operates in the DLL mode. For a schematic diagram of the system equivalent circuit structure of the fractional delay phase-locked loop in the DLL mode, see Figure 7 , at this time, the circuit can be equivalent to a DLL. The filter LPF can be regarded as a low-pass filter composed of a single capacitor under the control of the signal sel+ and the signal sel- obtained after the differential processing of the logic selection signal sel. The logic selection signal generating module outputs a low-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential module converts the logic selection signal sel into a signal sel+ and a signal sel-; the first PN+S counter obtains a first counting signal according to the reference clock CLKREF, and the selector MUX1 outputs the first counting signal as the input signal CLK_IN under the control of the signal sel+; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF acts as a single capacitor filter under the control of the signal sel+ and the signal sel-, and outputs a control voltage Vctrl according to the charge and discharge current; the voltage-controlled oscillator VCO is disconnected under the control of the signal sel+ and the signal sel-, and generates a clean reference clock as the output clock CLKOUT according to the control voltage Vctrl; the second PN+S counter outputs a feedback signal CLK_O according to the output clock CLKOUT; the selector MUX1, under the control of the signal sel+, transmits the reference clock signal CLKREF to the phase frequency detector PFD, and completes the introduction of a clean reference clock to eliminate the jitter accumulated in the Fractional-N PLL mode. It can be understood that by periodically introducing a clean reference clock rising edge, the rising edge of the output clock is replaced with a clean reference clock rising edge, thereby reducing the jitter of the output clock.

[0220] Fractional-N PLL Mode

[0221] When the logic selection signal sel output by the logic selection signal generating module is at a high level, the fractional delay phase-locked loop operates in the Fractional-N PLL mode. For a schematic diagram of the system equivalent circuit structure of the fractional delay phase-locked loop in the Fractional-N PLL mode, see Figure 8, at this time, the circuit can be equivalent to a fractional frequency phase-locked loop. Under the control of the signal sel+ and the signal sel- obtained after the differential processing of the logic selection signal sel, the filter LPF can be regarded as a third-order low-pass filter. The third-order low-pass filter can eliminate the ripple generated on the control voltage Vctrl as much as possible. The transfer function formula of the third-order low-pass filter is as follows:

[0222]

[0223] The third-order low-pass filter introduces three poles. If C1>>C2+C3 and R1>R3 are satisfied, the three poles ω p1 ,ω p2 and ω p3 They are as follows:

[0224] ω p1 =0;

[0225]

[0226] Compared with the low-order filter, the third-order filter further suppresses the high-frequency signal and reduces the ripple on the control voltage Vctrl.

[0227] When the logic selection signal sel is at a high level, the signal sel+ is at a high level and the signal sel- is at a low level. The logic selection signal generating module outputs a high-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential module converts the logic selection signal sel into a signal sel+ and a signal sel-; the selector MUX1 outputs the reference clock CLKREF as the input signal CLK_IN under the control of the signal sel+; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts The pulse signal is converted into a charge and discharge current output; under the control of the signal sel+ and the signal sel-, the filter LPF acts as a low-pass filter to filter out the high-frequency noise signal in the charge and discharge current, and outputs the control voltage Vctrl; under the control of the signal sel+ and the signal sel-, the voltage-controlled oscillator VCO loop is closed, and the output clock CLKOUT is generated according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the programmable divider based on the Σ-Δ modulator outputs a feedback signal CLK_O according to the output clock CLKOUT; under the control of the signal sel+, the selector MUX2 transmits the feedback signal CLK_O to the phase frequency detector PFD.

[0228] The embodiment of the present invention adopts a logic selection signal generating module to provide a logic selection signal sel, and after the first single-ended to differential conversion module, outputs a signal sel+ and a signal sel-, controls the opening and closing of the voltage-controlled oscillator VCO loop, so as to control the periodic switching of the fractional frequency delay locked loop between the Fractional-N PLL mode and the DLL mode; by periodically switching from the Fractional-N PLL mode to the DLL mode, a clean reference clock rising edge is periodically introduced, and the rising edge of the output clock is replaced with a clean reference clock rising edge, thereby reducing the jitter of the output clock and improving the frequency resolution of the output clock; fractional frequency multiplication is achieved by introducing a programmable frequency divider based on a Σ-Δ modulator. Furthermore, the logic selection signal generating module proposed in the present invention has a logic self-recovery function, which can solve the problem of failure to lock normally during the fractional frequency multiplication process.

[0229] It should be noted that in the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0230] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A fractional frequency delay phase-locked loop based on a Σ-Δ modulator, characterized in that: include: Logic selection signal generating module, phase frequency detector PFD, charge pump CP, filter LPF, voltage controlled oscillator VCO, first single-ended to differential module, second single-ended to differential module, first PN+S counter, second PN+S counter, programmable frequency divider based on Σ-Δ modulator, selector MUX1, selector MUX2; wherein, The logic selection signal generating module has a logic self-recovery function, and is used to control the fractional frequency delay phase-locked loop to work periodically; within one cycle, the fractional frequency delay phase-locked loop works in the Fractional-N PLL mode or the DLL mode in turn; In the Fractional-N PLL mode, the logic selection signal generating module outputs a high-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential module converts the logic selection signal sel into a signal sel+ and a signal sel-; the selector MUX1 outputs the reference clock CLKREF as the input signal CLK_IN under the control of the signal sel+; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF, under the control of the signal sel+ and the signal sel-, acts as a low-pass filter to filter out the high-frequency noise signal in the charge and discharge current, and outputs the control voltage Vctrl; the voltage-controlled oscillator VCO, under the control of the signal sel+ and the signal sel-, closes the VCO loop, and generates the output clock CLKOUT according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the programmable frequency divider based on the Σ-Δ modulator outputs the feedback signal CLK_O according to the output clock CLKOUT; the selector MUX2, under the control of the signal sel+, transmits the feedback signal CLK_O to the phase frequency detector PFD; In the DLL mode, the logic selection signal generating module outputs a low-level logic selection signal sel according to the reference clock CLKREF and the output clock CLKOUT of the voltage-controlled oscillator VCO; the first single-ended to differential conversion module converts the logic selection signal sel into a signal sel+ and a signal sel-; the first PN+S counter obtains a first counting signal according to the reference clock CLKREF, and the selector MUX1 outputs the first counting signal as the input signal CLK_IN under the control of the signal sel+, thereby completing the introduction of a clean reference clock to eliminate the problem of the Fractional-N Jitter in PLL mode; the second single-ended to differential module converts the input signal CLK_IN into a signal CLK_IN+ and a signal CLK_IN-; the phase frequency detector PFD detects the frequency difference and phase difference between the input signal CLK_IN and the feedback signal CLK_O, and outputs a pulse signal; the charge pump CP converts the pulse signal into a charge and discharge current output; the filter LPF acts as a single capacitor filter under the control of the signal sel+ and the signal sel-, and outputs a control voltage Vctrl according to the charge and discharge current; the voltage-controlled oscillator VCO is disconnected from the VCO loop under the control of the signal sel+ and the signal sel-, and introduces a clean reference clock as the output clock CLKOUT according to the signal CLK_IN+, the signal CLK_IN- and the control voltage Vctrl; the second PN+S counter outputs a feedback signal CLK_O according to the output clock CLKOUT; the selector MUX2 transmits the feedback signal CLK_O to the phase frequency detector PFD under the control of the signal sel+.

2. The fractional frequency delay phase-locked loop based on Σ-Δ modulator according to claim 1, characterized in that: In one cycle, the fractional delay phase-locked loop operates in the Fractional-NPLL mode or the DLL mode in sequence, including: The fractional delay phase-locked loop first operates in the Fractional-N PLL mode. When the output clock CLKOUT passes the Nth falling edge and the output clock CLKOUT becomes a low level, the fractional delay phase-locked loop switches to the DLL mode. When the reference clock CLKREF passes the Mth clock rising edge and the output clock CLKOUT is a high level, the fractional delay phase-locked loop switches to the Fractional-NPLL mode and enters the next cycle.

3. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: The logic selection signal generating module comprises: A third single-ended to differential conversion module, a buffer unit BUFFER, a D flip-flop DFF1, a D flip-flop DFF2, an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, an XOR gate XOR, a PN+S counter 1, a PN+S counter 2, a MOS tube M01, a MOS tube M02, a MOS tube M03, a MOS tube M04 and a MOS tube M05; wherein, The input end of the third single-ended to differential module is connected to the output end of the PN+S counter 2, the first output end is connected to the input end of the buffer unit BUFFER, and the second output end is connected to the CKN end of the D flip-flop DFF2; The output end of the buffer unit BUFFER is connected to the CLK end of the D flip-flop DFF1; The D terminal of the D flip-flop DFF1 is connected to its own QN terminal, and the Q terminal is connected to the first input terminal of the XOR gate XOR; The D terminal of the D flip-flop DFF2 is connected to its own QN terminal, and the QN terminal is connected to the second input terminal of the XOR gate XOR; The input end of the inverter INV1 is connected to the output clock CLKOUT, and the output end is connected to the input end of the PN+S counter 1; The input end of the inverter INV2 is connected to the output end of the PN+S counter 1, and the output end is connected to the gate of the MOS tube M01; The input end of the inverter INV3 is connected to the external reset signal rst_n, and the output end is connected to the rstn reset end of the PN+S counter 2; The input end of the inverter INV4 is connected to the output end of the inverter INV5, and the output end is connected to the input end of the inverter INV5; The input end of the inverter INV5 is connected to the drain of the MOS tube M02, and the output end serves as the output end of the logic selection signal generating module; The output end of the XOR gate is connected to the rstn reset end of the PN+S counter 1; The input end of the PN+S counter 2 is connected to the reference clock CLKREF, and the output end is connected to the gate of the MOS tube M04; The source of the MOS tube M01 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M02; The gate of the MOS tube M02 is connected to the output clock CLKOUT, and the drain is connected to the input end of the inverter INV5; The source of the MOS tube M03 is connected to the drain of the MOS tube M04, the gate is connected to the gate of the MOS tube M02, and the drain is connected to the drain of the MOS tube M02; The source of the MOS tube M04 is grounded, and the gate is connected to the output end of the PN+S counter 2; The source of the MOS tube M05 is grounded, the gate is connected to the input end of the inverter INV3, and the drain is connected to the output end of the XOR gate XOR.

4. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 3, characterized in that: The MOS transistor M01, MOS transistor M02, MOS transistor M03 and MOS transistor M04 constitute a three-state gate; wherein, The gate of the MOS tube M01 serves as the first input terminal of the tri-state gate; The gate of the MOS tube M02 serves as the second input terminal of the tri-state gate, and the drain serves as the output terminal of the tri-state gate; The gate of the MOS transistor M04 serves as the third input terminal of the tri-state gate.

5. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: The phase frequency detector (PFD) comprises: A first D flip-flop, a second D flip-flop, a buffer, an AND gate, and a NOT gate; wherein, The CLK terminal of the first D flip-flop is connected to the input signal CLK_IN, the D terminal is connected to the power supply voltage, the Q terminal is connected to the first input terminal of the AND gate, and the R terminal is connected to the R terminal of the second D flip-flop; The CLK terminal of the second D flip-flop is connected to the feedback signal CLK_O, the D terminal is connected to the power supply voltage, the Q terminal is connected to the second input terminal of the AND gate, and the R terminal is connected to the output terminal of the buffer; The input end of the buffer is connected to the output end of the AND gate; The input end of the NOT gate is connected to the first input end of the AND gate, and the output end serves as the first output end of the PFD; The second input terminal of the AND gate serves as the second output terminal of the phase frequency detector PFD.

6. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: The charge pump CP comprises: A first current source I1, a second current source I2, a first switch and a second switch; wherein, The input end of the first current source I1 is connected to the power supply voltage, and the output end is connected to the first end of the first switch; The input end of the second current source I2 is connected to the second end of the second switch, and the output end is grounded; The second end of the first switch is connected to the first end of the second switch, and the control end is connected to the first output end of the phase frequency detector PFD; The first end of the second switch serves as the output end of the charge pump CP, and the control end is connected to the second output end of the phase frequency detector PFD.

7. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: The filter LPF comprises: Resistor R1, resistor R2, capacitor C1, capacitor C2, capacitor C3 and transmission gate switch sw; wherein, The first end of the resistor R1 is connected to the output end of the charge pump CP, and the second end is connected to the first end of the capacitor C1; The first end of the resistor R2 is connected to the first end of the capacitor C2, and the second end is connected to the first end of the capacitor C3; The second end of the capacitor C1 is grounded; The first end of the capacitor C2 is connected to the first end of the resistor R1, and the second end is grounded; The first end of the capacitor C3 serves as the output end of the filter LPF, and the second end is grounded; The input end of the transmission gate switch sw is connected to the first end of the resistor R1, the output end is connected to the resistor R2, the first control end is connected to the signal sel+, and the second control end is connected to the signal sel-.

8. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: Any single-ended to differential module, including: Buffer unit BUFFER1, buffer unit BUFFER2, buffer unit BUFFER3 and inverter INV; wherein, The input end of the buffer unit BUFFER1 is connected to the input end of the inverter INV, and the output end is connected to the input end of the buffer unit BUFFER2; The output end of the buffer unit BUFFER2 serves as the first output end of the single-ended to differential conversion module; The input end of the inverter INV is used as the input end of the single-ended to differential module, and the output end is connected to the input end of the buffer unit BUFFER3; The output end of the buffer unit BUFFER3 serves as the second output end of the single-ended to differential conversion module.

9. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 1, characterized in that: The voltage controlled oscillator VCO comprises: Voltage-controlled delay unit 1, voltage-controlled delay unit 2, voltage-controlled delay unit 3 and voltage-controlled delay unit 4; wherein, The input port inp1 of the voltage-controlled delay unit 1 is connected to the output port von of the voltage-controlled delay unit 4, the input port inn1 is connected to the output port vop of the voltage-controlled delay unit 4, the input port inp2 is connected to the signal CLK_IN+, the input port inn2 is connected to the signal CLK_IN-, the input port s is connected to the signal sel+, the input port sd is connected to the signal sel-, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 2, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 2; The input port inp2 of the voltage-controlled delay unit 2 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 3, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 3; The input port inp2 of the voltage-controlled delay unit 3 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, the input port vt is connected to the external signal vt, the output port vop is connected to the input port inp1 of the voltage-controlled delay unit 4, and the output port von is connected to the input port inn1 of the voltage-controlled delay unit 4; The input port inp2 of the voltage-controlled delay unit 4 is connected to the external signal VSS, the input port inn2 is connected to the external signal VSS, the input port s is connected to the external signal VDD, the input port sn is connected to the external signal VSS, and the input port vt is connected to the external signal vt.

10. The fractional frequency delay phase locked loop based on Σ-Δ modulator according to claim 9, characterized in that: Any one of the voltage-controlled delay unit 1, the voltage-controlled delay unit 2, the voltage-controlled delay unit 3 and the voltage-controlled delay unit 4 includes: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17 and MOS tube M18; wherein, The source of the MOS tube M1 is connected to the power supply voltage, and the drain is connected to the source of the MOS tube M5; The source of the MOS tube M2 is connected to the source of the MOS tube M1, and the drain is connected to the source of the MOS tube M6; The source of the MOS tube M3 is connected to the source of the MOS tube M2, and the drain is connected to the source of the MOS tube M7; The source of the MOS tube M4 is connected to the source of the MOS tube M3, and the drain is connected to the source of the MOS tube M8; The drain of the MOS tube M5 is connected to the drain of the MOS tube M9; The drain of the MOS tube M6 is connected to the drain of the MOS tube M10; The drain of the MOS tube M7 is connected to the drain of the MOS tube M11; The drain of the MOS tube M8 is connected to the drain of the MOS tube M12; The drain of the MOS tube M5 and the drain of the MOS tube M7 serve as the output port von of the voltage-controlled delay unit; The drain of the MOS tube M6 and the drain of the MOS tube M8 serve as the output port vop of the voltage-controlled delay unit; The source of the MOS tube M9 is connected to the drain of the MOS tube M13; The source of the MOS tube M10 is connected to the drain of the MOS tube M14; The source of the MOS tube M11 is connected to the drain of the MOS tube M15; The source of the MOS tube M12 is connected to the drain of the MOS tube M16; The source of the MOS tube M13 is connected to the drain of the MOS tube M17; The source of the MOS tube M14 is connected to the source of the MOS tube M13; The source of the MOS tube M15 is connected to the source of the MOS tube M14; The source of the MOS tube M16 is connected to the source of the MOS tube M15; The source of the MOS tube M17 is grounded; The source of the MOS tube M18 is grounded, and the drain is connected to the source of the MOS tube M16; The gate of the MOS tube M1 and the gate of the MOS tube M13 serve as the input port inp1 of the voltage-controlled delay unit; The gate of the MOS tube M2 and the gate of the MOS tube M14 serve as the input port inn1 of the voltage-controlled delay unit; The gate of the MOS tube M3 and the gate of the MOS tube M15 serve as the input port inp2 of the voltage-controlled delay unit; The gate of the MOS tube M4 and the gate of the MOS tube M16 serve as the input port inn2 of the voltage-controlled delay unit; The gate of the MOS tube M5, the gate of the MOS tube M6, the gate of the MOS tube M11 and the gate of the MOS tube M12 serve as the input port sn of the voltage-controlled delay unit; The gate of the MOS transistor M7 , the gate of the MOS transistor M8 , the gate of the MOS transistor M9 and the gate of the MOS transistor M10 serve as the input port s of the voltage-controlled delay unit.

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