Satellite-borne radar measurement data timestamp synchronous timing method and system

Abstract

The invention discloses a satellite-borne radar measurement data timestamp synchronous timing method and system. The method comprises the steps that a satellite time timer is designed through an FPGA logic circuit for timing; according to the second pulse signal, second synchronous timing is carried out on the star time timer through an FPGA logic circuit; according to an irregular satellite time broadcast signal and the second pulse signal, world coordinated time correction is carried out on the satellite time timer through an FPGA logic circuit; and performing timestamp synchronous timing on the spaceborne radar measurement data. Through the design of the FPGA logic circuit, second synchronous time calibration and world coordinated time calibration are carried out on the satellite time timer, high-precision synchronous time calibration of spaceborne radar time is achieved, the high-precision synchronization requirement of spaceborne radar of a GNC control system is met, the time stamp synchronous time calibration design is further added to output measurement data of the spaceborne radar, and the time calibration precision of the spaceborne radar is improved. And the measurement precision of spaceborne radar measurement data is effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of timestamp synchronization, and in particular to a method and system for synchronizing timestamps of satellite-borne radar measurement data. Background Art

[0002] The satellite time synchronization system can improve the time coordination efficiency of each single machine in the satellite by providing standard time signals and standard frequency signals to each terminal user of the satellite. The existing technology generally achieves time synchronization with general accuracy through GPS time calibration, satellite time bus broadcast, hardware second pulse output, etc. However, with the continuous improvement of satellite payload functions and performance, the satellite control system has higher and higher requirements for the time synchronization accuracy and stability of payload equipment. When the GNC (Guidance, Navigation and Control) control system provides hardware second pulse input and irregular satellite time broadcast to the satellite-borne microwave radar subsystem, in order to meet the high-precision time synchronization requirements (≤10μs) of the GNC control system and the satellite-borne microwave radar and improve the measurement accuracy of the satellite-borne radar ranging information, it is necessary to perform on-board time synchronization calibration on the satellite-borne radar subsystem.

[0003] However, the existing technology has problems such as low synchronization accuracy, inability to support the UTC time that is not an integral second, and occupying CPU time for the second pulse input and irregular satellite time broadcast signal provided by the GNC control system to the satellite-borne radar subsystem, and fails to provide a time synchronization solution that meets the high-precision time synchronization requirements of the GNC control system and the satellite-borne radar.

[0004] In addition, since there is a time difference in the process of the measurement data output by the satellite-borne radar being transmitted from the measurement target to the microwave radar antenna array, there will be errors in the timestamp of the measurement data recorded by the satellite-borne radar, which further affects the time synchronization between the GNC control system and the satellite-borne radar. Summary of the invention

[0005] The purpose of the present invention is to provide a method and system for synchronizing and calibrating the time stamp of satellite-borne radar measurement data, which is used for performing second synchronization and world coordinated time synchronization on the satellite time timer according to the second pulse input and irregular satellite time broadcast signal provided by the GNC control system to the satellite-borne microwave radar subsystem through FPGA (Field Programmable Gate Array) logic circuit design, so as to realize high-precision synchronization and calibrating the satellite-borne radar time, meet the high-precision synchronization requirements of the GNC control system for the satellite-borne radar time, and further add a time stamp synchronization and calibrating design to the satellite-borne radar measurement data, so as to effectively improve the measurement accuracy of the satellite-borne radar measurement data.

[0006] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:

[0007] A first aspect of the present invention provides a method for synchronizing and correcting timestamps of satellite-borne radar measurement data, comprising:

[0008] Design a star timer through FPGA logic circuit to measure time;

[0009] According to the second pulse signal, the star timer is synchronized and timed by the FPGA logic circuit;

[0010] According to the irregular star time broadcast signal and the second pulse signal, the star time timer is calibrated to the world coordinated time through the FPGA logic circuit;

[0011] Perform time stamp synchronization on the satellite-borne radar measurement data.

[0012] Optionally, the timing time T of the star timer now Including the whole second part of the timing T integer_now and the non-integer second part timing T decimal_now .

[0013] Optionally, the step of performing the second synchronization time adjustment on the star timer through an FPGA logic circuit according to the second pulse signal comprises:

[0014] The falling edge of the second pulse signal is timed and latched twice, the difference between the two is recorded, and whether the second pulse signal is valid is determined based on the size of the difference. When the second pulse signal is determined to be valid, the second synchronization calibration is performed on the star timer.

[0015] Optionally, the performing the second synchronization time adjustment on the star timer through an FPGA logic circuit includes:

[0016] The comparator compares the non-integer second timing T decimal_now ;

[0017] When the non-integer second part is timed T decimal_now When it is greater than or equal to 500ms, the timing time T is calculated by the following formula: now To perform a calibration:

[0018] T now =T integer_now +α pps +1;

[0019] When the non-integer second part is timed When it is less than 500ms, the timing time T is calculated by the following formula: now To perform a calibration:

[0020] T now =T integer_now +α pps;

[0021] Among them, α pps is the delay time in the process of receiving the second pulse signal.

[0022] Optionally, the step of calibrating the star time timer to the UTC time using an FPGA logic circuit according to the irregular star time broadcast signal and the second pulse signal comprises:

[0023] The UTC is received by the irregular star time broadcast signal utc , and latch the current timing time T now , recorded as broadcast time lock time;

[0024] Calculate the difference δ between the broadcast time lock time and the falling edge lock time of the previous second pulse signal pps_utc , and calculate the whole second time of the second pulse signal according to the following formula

[0025]

[0026] The whole second time is calculated according to the second pulse signal Perform the UTC time calibration.

[0027] Optionally, the performing the UTC time calibration on the star timer through an FPGA logic circuit comprises:

[0028] The second pulse signal is converted into a whole second time Decomposed into whole seconds, Coordinated Time T integer_utc and the non-integer second portion of the coordinated time T decimal_err ;

[0029] The non-integer second partial coordinated time T is compared by a comparator decimal_err ;

[0030] When the non-integer second part is coordinated, T decimal_err When it is greater than or equal to 500ms, the whole second part is timed by the following formula T integer_now To perform a calibration:

[0031] T integer_now =T integer_utc +1;

[0032] When the non-integer second part is coordinated, T decimal_err When it is less than 500ms, the whole second part is timed by the following formula T integer_now To perform a calibration:

[0033] T integer_now =T integer_utc ;

[0034] The timing time T is calculated by the following formula now To perform a calibration:

[0035] T now =T integer_now +T decimal_now +α pps ;

[0036] Among them, α pps is the delay time in the process of receiving the second pulse signal.

[0037] Optionally, the second pulse signal is rounded to a second by a subtractor and a shifter. Decomposed into the whole second parts of the coordinated time T integer_utc and the non-integer second part coordinated time T decimal_err .

[0038] Optionally, a FIFO (First In First Out) IP (Intellectual Property) core in an FPGA logic circuit is used to receive and send the irregular satellite time broadcast signal via RS422 serial port communication.

[0039] Optionally, the timestamp synchronization includes:

[0040] Calculate the ranging time error T according to the following formula target_err :

[0041] T target_err =D target / c;

[0042] Among them, D target is the distance between the satellite-borne radar and the measurement target, and c is the speed of light;

[0043] According to the ranging time error T target_err , the satellite-borne radar measurement data timestamp T is calculated by the following formula target To make a correction:

[0044] T target =T target_now -T target_err ;

[0045] Among them, T target_now It is the timing time of the star timer when the electromagnetic wave returns from the measurement target.

[0046] A second aspect of the present invention provides a satellite-borne radar measurement data timestamp synchronization and timing system, which is used to implement the satellite-borne radar measurement data timestamp synchronization and timing method described in any one of the first aspects above, including:

[0047] A star timer, which is designed by an FPGA logic circuit and is used for timing;

[0048] A second synchronization time adjustment module, used for receiving the second pulse signal, and performing second synchronization time adjustment on the star timer through an FPGA logic circuit according to the second pulse signal;

[0049] A UTC time calibration module, used for receiving an irregular star time broadcast signal, and calibrating the star time timer to the UTC time through an FPGA logic circuit according to the irregular star time broadcast signal and the second pulse signal;

[0050] A timestamp synchronization module, used for performing timestamp synchronization on the satellite-borne radar measurement data; and

[0051] The clock generator is a local high-stability crystal oscillator, which is used as the system clock for the second synchronization time setting and the world coordinated time setting, and simultaneously generates timing pulses for the star timer to perform timing.

[0052] The present invention has at least one of the following technical effects:

[0053] Through FPGA logic circuit design, the satellite time counter is synchronized in seconds and the world coordinated time is synchronized, achieving high-precision synchronization of satellite-borne radar time and meeting the high-precision synchronization requirements of the GNC control system for satellite-borne radar time.

[0054] By further adding a time stamp synchronization design to the satellite-borne radar measurement data, the measurement accuracy of the satellite-borne radar measurement data is effectively improved. At the same time, the GNC control system can accurately match the time information of the satellite-borne radar measurement data.

[0055] By automatically completing the second synchronization time calibration and the UTC time calibration process through the FPGA logic circuit, the processing complexity is low, the resource usage is small, and no CPU participation is required, freeing the CPU from tedious time calibration and time maintenance operations, greatly saving CPU time, improving time calibration efficiency and on-board time reliability, and easy to implement in engineering. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A flowchart of a method for synchronizing and correcting timestamps of satellite-borne radar measurement data provided by an embodiment of the present invention;

[0057] Figure 2 A principle block diagram of a method for synchronizing and correcting timestamps of satellite-borne radar measurement data provided by an embodiment of the present invention;

[0058] Figure 3A schematic diagram of the UTC time synchronization method for the timestamp synchronization of satellite-borne radar measurement data provided by an embodiment of the present invention;

[0059] Figure 4 The whole second time of the second pulse signal of the satellite-borne radar measurement data timestamp synchronization time calibration method provided by an embodiment of the present invention Schematic diagram of the decomposition. DETAILED DESCRIPTION

[0060] The following is a further detailed description of a satellite-borne radar measurement data timestamp synchronization method and system proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the accompanying drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0061] As described in the background technology, with the continuous improvement of satellite payload functions and performance, the satellite control system has higher and higher requirements for the time synchronization accuracy and stability of payload equipment. When the GNC control system provides hardware second pulse input and irregular satellite time broadcast to the satellite-borne microwave radar subsystem, in order to meet the high-precision time synchronization requirements of the GNC control system and the satellite-borne microwave radar and improve the measurement accuracy of the satellite-borne radar ranging information, it is necessary to perform on-board time synchronization calibration of the satellite-borne radar subsystem.

[0062] The patent name is the invention patent of the patented small satellite high-precision time synchronization method. It generates the corresponding time mark according to the received GPS (Global Positioning System) second pulse signal and the corresponding whole second time synchronization broadcast data to achieve time synchronization. This method requires the on-board CAN (Controller Area Network) bus to adopt a limited multi-master communication working mode to ensure that the receiver outputs the corresponding whole second time synchronization broadcast data within 50ms after the second pulse signal is generated. At the same time, it is required that the software set the receiver to send the whole second time synchronization broadcast data corresponding to the second pulse signal as the highest priority, occupying the CPU (Central Processing Unit) machine time.

[0063] The patent name is an invention patent for a high-precision time synchronization method on a satellite, which is used to design the satellite service center computer. It achieves high-precision time synchronization of satellite time users between subsystems of the entire satellite by outputting high-precision second pulses on the 422 bus and sending time broadcast information on the CAN bus to the satellite time users. This method is only for the design of the satellite service center computer and does not involve the time synchronization design of the satellite time users.

[0064] The patent name is an invention patent for a satellite time synchronization system, which uses the received second pulse signal as the trigger point for timing to start through the time receiving terminal, and uses the clock signal provided by the crystal oscillator to count and calculate the accurate current time. This method also requires providing the whole second moment information to the time receiving terminal.

[0065] The paper "An Improved Method for Time Synchronization of Satellite-borne CAN Bus" (Journal of Northwestern Polytechnical University, No. 38, 2020) removes the delay of the bus transmission process through two-way time comparison, and eliminates the bus uncertainty error through smoothing filtering, thereby improving the accuracy of intra-satellite time synchronization to 160μs. This method is aimed at the time synchronization of the satellite-borne CAN bus network, which requires the satellite service host to actively calculate the time difference for the satellite single machine, and lacks system independence.

[0066] The document "Design of HXMT Satellite Time Synchronization System" ("Computer Measurement and Control", No. 26, 2018) introduces the satellite time synchronization system in detail, and uses hardware second pulses and the whole second time broadcast by the 1533B bus as a high-precision time synchronization solution. However, this method requires the GPS receiver to periodically provide whole second time codes to broadcast to each user terminal, and requires that the interval between the hardware second pulse signal and the broadcast whole second time is no more than 0.5s. This solution is not applicable when the world coordinated time UTC (Universal Time Coordinated) broadcast to the satellite time bus is non-whole second time.

[0067] The document "High-precision Timekeeping Method for Star Cameras" ("Spacecraft Engineering", No. 28, 2019) achieves high-precision time synchronization by calibrating the time scale of its own equipment (1Hz second pulse) and strictly aligning it with the satellite time standard, so that the on-board clock, the control synchronizer equipment clock and the equipment clock of each star camera are always coincident. This method also requires the GPS receiver to periodically provide a whole second time code broadcast.

[0068] In summary, for the pulse-per-second input and irregular satellite time broadcast signal provided by the GNC control system to the satellite-borne radar subsystem, the existing technology has problems such as low synchronization accuracy, inability to support the UTC time that is not an integral second, and occupying CPU time, and fails to provide a time calibration solution that meets the high-precision synchronization requirements of the GNC control system and the satellite-borne radar.

[0069] In view of this, if Figure 1 As shown, this embodiment provides a method for timestamp synchronization and timing of satellite-borne radar measurement data, comprising the following steps: step S1, designing a satellite time timer through an FPGA logic circuit to perform timing; step S2, receiving a second pulse signal, and performing second synchronization and timing of the satellite time timer through an FPGA logic circuit according to the second pulse signal; step S3, receiving an irregular satellite time broadcast signal, and performing world coordinated time timing of the satellite time timer through an FPGA logic circuit according to the irregular satellite time broadcast signal and the second pulse signal; and step S4, performing timestamp synchronization and timing of the satellite-borne radar measurement data.

[0070] Specifically, in step S1, Figure 2 As shown, this embodiment adopts FPGA logic circuit, that is, field programmable gate array logic circuit to design the star time timer. A local high-stability crystal oscillator is used as a clock generator, which is used as the system clock for the second synchronization time calibration and the world coordinated time calibration, and simultaneously generates a timing pulse for the star time timer to perform timing. The vibration frequency of the high-stability crystal oscillator is, for example, 40MHz, and the timing pulse used for the star time timer to perform timing has a period of, for example, 100ns. As a high-precision and high-stability oscillator, the high-stable crystal oscillator can provide a highly stable frequency and an accurate clock signal to ensure the stable operation of the system.

[0071] When the timing pulse has a period of 100 ns, the number of bits of the counting result of the satellite timer can be determined as 52 bits according to the 8-year on-orbit life. now Divided into whole second parts of timing T interger_now and the non-integer second part timing T decimal_now When the non-integer second part is timed T decimal_now When the timing reaches 1s, the whole second part is timed T integer_now Add 1s, and time the non-integer second part T decimal_now Clear to zero to achieve basic timing function.

[0072] like Figure 2 As shown, in step S2, in order to prevent the second pulse signal from being submerged by interference signals and causing missed calibration, the designed hardware interface of the satellite-borne radar can receive the second pulse signal sent by the GNC control system in the form of RS422 differential voltage signal, and further detect the second pulse signal through the satellite time second pulse detector. Thus, the second pulse signal can be further used as a hardware constraint condition to design the trigger condition of the second synchronization time calibration.

[0073] like Figure 1As shown, in the step S2, in order to avoid the interference of pseudo pulses and cause incorrect calibration, after the satellite-borne radar receives the second pulse signal, it is necessary to perform two-beat timing latching on the falling edge of the second pulse signal, record the difference between the two, and judge whether the second pulse signal is valid based on the size of the difference. When it is judged that the second pulse signal is valid, the second synchronization calibration is performed on the satellite timer through a comparator.

[0074] Specifically, under the system clock, the falling edge of the second pulse signal is timed and latched twice, which are recorded as T pps_latch1 and T pps_latch2 Calculate T pps_latch1 and T pps_latch2 The difference between pps , if and only if 1s-ε pps ≤δ pps ≤1s+ε pps When , the second pulse signal is determined to be valid, where ε pps The value of needs to be determined by comprehensively considering the system error of the high-stability crystal oscillator, the error value of the 1pps second pulse signal, and the synchronization time accuracy required by the GNC control system. pps The value of can be, for example, 10 ms.

[0075] In view of the interference of pseudo pulses on the recognition of the second pulse signal, the present invention designs an FPGA logic circuit to perform two-beat timing latching and difference judgment on the falling edge of the second pulse signal, thereby effectively avoiding the interference of pseudo pulses and saving software and hardware resources. The implementation method of the hardware constraint design is simple and reliable.

[0076] like Figure 2 As shown, under the premise of judging that the second pulse signal is valid, the second synchronization calibration can be further performed on the star timer, that is, the current timing time T of the star timer is calibrated by a comparator. now The fractional second time T decimal_now The second synchronization time calibration is completed by rounding off to the nearest integer. The second synchronization time calibration can effectively eliminate the accumulated error generated by the high-stability crystal oscillator in the long-term frequency output process.

[0077] Specifically, in the second synchronization time setting, the non-integer second part timing T can be compared by a comparator. decimal_now .

[0078] When the non-integer second part is timed T decimal_now When it is greater than or equal to 500ms, the timing time T is calculated by the following formula: now To perform a calibration:

[0079] T now =Tinteger_now +α pps +1;

[0080] When the non-integer second part is timed When it is less than 500ms, the timing time T is calculated by the following formula: now To perform a calibration:

[0081] T now =T integer_now +α pps .

[0082] Among them, α pps is the delay time in the process of receiving the second pulse signal, that is, the delay time in the process of transmitting the second pulse signal from the output port of the GNC control system to the input port of the satellite-borne radar in the form of RS422 differential voltage signal, α pps The specific value can be tested and calibrated during the satellite ground testing.

[0083] like Figure 2 As shown, in step S3, the subsystem of the satellite-borne radar also receives irregular star time broadcast signals sent from the GNC control system irregularly through RS422 serial communication. By receiving the irregular star time broadcast signals, the star time timer can be further calibrated with the world coordinated time through a comparator according to the irregular star time broadcast signals and the second pulse signal.

[0084] In the past, serial ports usually use CPU software interrupt mode when sending and receiving data. However, the above-mentioned CPU software interrupt mode not only needs to occupy CPU machine time, but the size of the communication delay is also related to the setting of the serial port interrupt priority of both parties. Therefore, the present invention selects to use the FIFO (First In First Out) IP (Intellectual Property) core in the FPGA logic circuit to receive and send the irregular star time broadcast signal through RS422 serial port communication. The autonomous completion of the irregular star time broadcast signal communication and reception is achieved, which not only saves CPU machine time, but also improves the reliability of the system at the same time.

[0085] Specifically, in step S3, the satellite-borne radar subsystem receives the world coordinated time T sent by the irregular satellite time broadcast signal through the RS422 serial communication mode. utc , the Universal Time Coordinated T utc The dimension of is consistent with that of the star timer, for example, 100ns.

[0086] Further, when receiving the world coordination T utc After that, the current timing time T is latchednow , and record it as the broadcast time lock time T utc_latch ,like Figure 3 As shown, when the broadcast time is locked, the lock time T utc_latch Then, the broadcast time lock time T is calculated. utc_latch The latching time T of the falling edge of the last second pulse signal pps_latch The difference between pps_utc After calculating the difference δ pps_utc After that, the whole second time of the second pulse signal at the falling edge of the previous second pulse signal can be estimated according to the following formula:

[0087]

[0088] In estimating the whole second time of the second pulse signal After that, the second time can be calculated according to the second pulse signal. Specifically, the second pulse signal can be converted into a whole second time by using a broadcast time correction whole second resolver. Decomposed into whole seconds, Coordinated Time T integer_utc and the non-integer second portion of the coordinated time T decimal_err .

[0089] Furthermore, the non-integer second partial coordinated time T decimal_err ;

[0090] When the non-integer second part is coordinated, T decimal_err When it is greater than or equal to 500ms, the whole second part is timed by the following formula T integer_now To perform a calibration:

[0091] T integer_now =T integer_utc +1.

[0092] When the non-integer second part is coordinated, T decimal_err When it is less than 500ms, the whole second part is timed by the following formula T interger_now To perform a calibration:

[0093] T integer_now =T integet_utc .

[0094] When timing the whole second portion T integer_now After calibration, the timing time T can be calculated by the following formula: now To perform a calibration:

[0095] T now =T integer_now +T decimal_now +αpps .

[0096] In step S3, in order to avoid the high resource occupancy caused by directly using the division and modulus operators, the present invention chooses to design a subtractor and a shifter to convert the second pulse signal into a whole second time. Decomposed into the whole second parts of the coordinated time T integer_utc and the non-integer second part coordinated time T decimal_err , and the non-integer second part of the coordinated time T decimal_err The result is sent to the comparator for rounding, thereby completing the UTC time calibration. Figure 4 As shown, the second pulse signal with a dimension of 100ns is converted into a whole second time. Convert to binary value, expand the digit k of the binary value to 2k, and shift to the left in sequence. Each time it is shifted, compare the value of the expanded digit (2k-1, k) with 1s. When the value of the expanded digit (2k-1, k) is greater than the binary value obtained by 1s conversion, subtract and add 1; otherwise, continue to shift until the shift is completed. At this time, the value of the digit (2k-1, k) is an integer multiple of 1s, and the value of the digit (k-1, 0) is a non-integer second timing value, thereby completing the whole second time of the second pulse signal. decomposition.

[0097] The present invention calculates the estimated second pulse signal second time Rounding off can effectively eliminate the time delay generated during RS422 serial communication receiving and sending, program execution and other operations, and improve the timing accuracy of the star timer.

[0098] Through the second synchronization time setting and the world coordinated time setting, the timing time T of the star timer now The only error that exists is the timing error of the high-stable crystal oscillator at the sub-second level, with an accuracy better than 1μs, which far meets the high-precision synchronization requirements of the GNC control system for satellite-borne microwave radar time. In addition, by designing comparators, subtractors, and shifters, the entire time calibration process is automatically completed by the FPGA logic circuit, freeing the CPU from tedious time calibration operations and time maintenance operations, greatly saving CPU machine time, helping to save costs, improve time calibration efficiency and on-board time reliability, and easy engineering implementation.

[0099] like Figure 4 As shown, after the star timer is timed by the second synchronization and the UTC, in step S4, the present invention further designs a timestamp synchronization for synchronizing the timestamp of the satellite-borne radar measurement data.

[0100] Specifically, since the measurement data of the spaceborne radar is determined by the time difference of the electromagnetic wave propagating from the measurement target to the antenna array of the spaceborne radar, the timestamp of the measurement data should be marked at the moment when the electromagnetic wave returns from the measurement target.

[0101] In step S4, the ranging time error T is calculated according to the following formula: target_err :

[0102] T target_err =D target / c;

[0103] Among them, D target is the distance between the satellite-borne radar and the measurement target, and c is the speed of light.

[0104] According to the ranging time error T target_err The satellite-borne radar measurement data timestamp T can be further calculated by the following formula: target To make a correction:

[0105] T target =T target_now -T target_err ;

[0106] Among them, T target_now It is the timing time of the star timer when the electromagnetic wave returns from the measurement target.

[0107] By calculating the ranging time error T target_err , and adding the timestamp synchronization time calibration to the measurement data obtained by the CPU, can effectively improve the measurement accuracy of the measurement data of the satellite-borne radar. At the same time, the GNC control system can also accurately match the time information of the measurement data of the satellite-borne radar.

[0108] In order to implement the above method, the second aspect of this embodiment also provides a satellite-borne radar measurement data timestamp synchronization timing system, including a clock generator, a star time timer, a second synchronization timing module, a world coordinated time timing module, and a timestamp synchronization timing module.

[0109] As described above, the clock generator is a local high-stability crystal oscillator, which is used as the system clock for the second synchronization time setting and the world coordinated time setting, and simultaneously generates timing pulses for the star timer to perform timing.

[0110] The star timer is designed by FPGA logic circuit for timing. Through the design of FPGA logic circuit, the timing time T of the star timer can be now Divided into whole second parts of timing T integer_now and the non-integer second part timing T decimal_now When the non-integer second part is timed T decimal_nowWhen the timing reaches 1s, the whole second part is timed T interger_now Add 1s, and time the non-integer second part T decimal_now Clear to zero to achieve basic timing function.

[0111] The second synchronization timing module is used to receive the second pulse signal, and according to the second pulse signal, perform second synchronization timing on the star time timer through the FPGA logic circuit. The second synchronization timing module can receive the second pulse signal through the RS422 differential voltage signal, and detect the second pulse signal through the star time second pulse detector.

[0112] The UTC time synchronization module is used to receive the irregular star time broadcast signal, and according to the irregular star time broadcast signal and the second pulse signal, the UTC time synchronization of the star time timer is performed through the FPGA logic circuit. The UTC time synchronization module can use the FIFO IP core in the FPGA logic circuit to receive and send the irregular star time broadcast signal through RS422 serial port communication, and decompose the second pulse signal whole second time through the broadcast time synchronization whole second decomposer The broadcast time correction whole second resolver may include a subtractor and a divider.

[0113] The timestamp synchronization and timing module is used to perform timestamp synchronization and timing on the satellite-borne radar measurement data. The timestamp synchronization and timing module can correct the timestamp of the satellite-borne radar measurement data obtained by the CPU through a divider and a subtractor.

[0114] The present invention provides a high-precision synchronization time solution for satellite-borne microwave radar time, targeting the hardware pulse-per-second input and irregular satellite-time broadcast time synchronization mode provided by the GNC control system to the satellite-borne radar subsystem. Through the FPGA logic circuit design, the pulse-per-second synchronization time synchronization and irregular satellite-time broadcast time synchronization are realized, and the satellite-time synchronization accuracy is better than 1μs. In addition, the time stamp synchronization time synchronization design is further added to the satellite-borne radar measurement data, thereby improving the measurement accuracy of the detection data. Compared with the prior art, it has significant beneficial effects.

[0115] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0116] It should be noted that the devices and methods disclosed in the embodiments of this article can also be implemented in other ways. The device implementation described above is only schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of this article. In this regard, each box in the flowchart or block diagram can represent a part of a module, program or code, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function, and the module, program segment or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented by a dedicated hardware-based system for performing a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0117] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0118] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for synchronizing and correcting timestamps of satellite-borne radar measurement data, characterized in that: include: Design a star timer through FPGA logic circuit to measure time; According to the second pulse signal, the star timer is synchronized and timed by the FPGA logic circuit; According to the irregular star time broadcast signal and the second pulse signal, the star time timer is calibrated to the world coordinated time through the FPGA logic circuit; Perform time stamp synchronization on the satellite-borne radar measurement data.

2. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 1, characterized in that: The timing time T of the star timer now Including the whole second part of the timing T integer_now and the non-integer second part timing T decimal_now .

3. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 2, characterized in that: The step of performing the second synchronization time adjustment on the star timer through an FPGA logic circuit according to the second pulse signal comprises: The falling edge of the second pulse signal is timed and latched twice, the difference between the two is recorded, and whether the second pulse signal is valid is determined based on the size of the difference. When the second pulse signal is determined to be valid, the second synchronization calibration is performed on the star timer.

4. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 2, characterized in that: The second synchronization time adjustment of the star timer by using an FPGA logic circuit comprises: The comparator compares the non-integer second timing T decimal_now ; When the non-integer second part is timed T decimal_now When it is greater than or equal to 500ms, the timing time T is calculated by the following formula: now To perform a calibration: T now =T integer_now +α pps +1; When the non-integer second part is timed When it is less than 500ms, the timing time T is calculated by the following formula: now To perform a calibration: T now =T integer_now +α pps ; Among them, α pps is the delay time in the process of receiving the second pulse signal.

5. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 3, characterized in that: The step of performing the UTC time calibration on the star time timer through an FPGA logic circuit according to the irregular star time broadcast signal and the second pulse signal comprises: Receiving the Universal Coordinated Time T by means of the irregular star time broadcast signal utc , and latch the current timing time T now , recorded as broadcast time lock time; Calculate the difference δ between the broadcast time lock time and the falling edge lock time of the previous second pulse signal pps_utc , and calculate the whole second time of the second pulse signal according to the following formula The whole second time is calculated according to the second pulse signal Perform the UTC time calibration.

6. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 5, characterized in that: The performing the UTC time calibration on the star timer by using the FPGA logic circuit comprises: The second pulse signal is converted into a whole second time Decomposed into whole seconds, Coordinated Time T integer_utc and the non-integer second portion of the coordinated time T decimal_err ; The non-integer second partial coordinated time T is compared by a comparator decimal_err ; When the non-integer second part is coordinated, T decimal_err When it is greater than or equal to 500ms, the whole second part is timed by the following formula T integer_now To perform a calibration: T integer_now =T integer_utc +1; When the non-integer second part is coordinated, T decimal_err When it is less than 500ms, the whole second part is timed by the following formula T integer_now To perform a calibration: T integer_now =T integer_utc ; The timing time T is calculated by the following formula now To perform a calibration: T now =T integer_now +T decimal_now +α pps ; Among them, α pps is the delay time in the process of receiving the second pulse signal.

7. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 6, characterized in that: The second pulse signal is converted into a whole second by a subtractor and a shifter Decomposed into the whole second parts of the coordinated time T integer_utc and the non-integer second part coordinated time T decimal_err .

8. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 1, characterized in that: The FIFOIP core in the FPGA logic circuit is used to receive and send the irregular satellite time broadcast signal through RS422 serial port communication.

9. The method for synchronizing and correcting the time stamp of satellite-borne radar measurement data according to claim 1, characterized in that: The timestamp synchronization includes: Calculate the ranging time error T according to the following formula target_err : T target_err =D target / c; Among them, D target is the distance between the satellite-borne radar and the measurement target, and c is the speed of light; According to the ranging time error T target_err , the satellite-borne radar measurement data timestamp T is calculated by the following formula target To make a correction: T target =T target_now -T target_err ; Among them, T target_now It is the timing time of the star timer when the electromagnetic wave returns from the measurement target.

10. A satellite-borne radar measurement data timestamp synchronization and timing system, used to implement the satellite-borne radar measurement data timestamp synchronization and timing method as claimed in any one of claims 1 to 9, characterized in that: include: A star timer, which is designed by an FPGA logic circuit and is used for timing; A second synchronization time adjustment module, used for receiving the second pulse signal, and performing second synchronization time adjustment on the star timer through an FPGA logic circuit according to the second pulse signal; A UTC time calibration module, used for receiving an irregular star time broadcast signal, and calibrating the star time timer to the UTC time through an FPGA logic circuit according to the irregular star time broadcast signal and the second pulse signal; A timestamp synchronization module is used to perform timestamp synchronization on the satellite-borne radar measurement data; and The clock generator is a local high-stability crystal oscillator, which is used as the system clock for the second synchronization time setting and the world coordinated time setting, and simultaneously generates timing pulses for the star timer to perform timing.

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