Decision feedback equalizer (DFE), receiver and chip

Abstract

The invention discloses a DFE, which is used for solving the problem of signal distortion caused by intersymbol interference in a high-speed signal data transmission process. The DFE comprises a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D trigger and a configuration circuit, the input end of the reference voltage generator is connected with the configuration circuit, and the output end of the reference voltage generator is connected with the first-stage feedback filter circuit; the first-stage feedback filter circuit is respectively connected with the reference voltage generator, the second-stage feedback filter circuit and the configuration circuit; the second-stage feedback filter circuit is respectively connected with the first-stage feedback filter circuit, the D trigger and the configuration circuit; the D trigger is connected with the second-stage feedback filter circuit and the configuration circuit; the configuration circuit is connected with the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit and the D trigger.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a decision feedback equalizer DFE, a receiver and a chip. Background Art

[0002] Digital communication occurs between a transmitting device and a receiving device through an intermediate communication medium or "channel" (e.g., a fiber optic cable or insulated copper wire). Each transmitting device typically sends symbols at a fixed symbol rate, while each receiving device detects a sequence of symbols and attempts to reconstruct the data being sent. A "symbol" is a state or valid condition of a channel that lasts for a fixed period of time, which is called a "symbol interval." A symbol can be, for example, a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent one or more binary bits of data, and data can be represented by a symbol transition or by a sequence of two or more symbols.

[0003] However, due to channel non-idealities, each symbol usually disrupts the dispersion of its adjacent symbols, an effect known as intersymbol interference (ISI). ISI may make it difficult for the receiving device to determine which symbols were sent in each interval, especially when this ISI is combined with additive noise. Due to the existence of intersymbol interference, it is very easy to cause inaccurate sampling results, signal distortion and other problems.

[0004] It can be seen that how to solve the signal distortion caused by inter-symbol interference during high-speed signal data transmission has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The embodiment of the present application provides a decision feedback equalizer DFE, which is used to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0006] The embodiment of the present application also provides a receiver to solve the problem of signal distortion caused by inter-symbol interference during high-speed signal data transmission.

[0007] The embodiment of the present application also provides a chip for solving the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0008] The present application embodiment adopts the following technical solutions: In a first aspect, a decision feedback equalizer DFE comprises: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop and a configuration circuit; the input end of the reference voltage generator is connected to the configuration circuit, and the output end of the reference voltage generator is connected to the first-stage feedback filter circuit, for providing reference voltages of different sizes to the first-stage feedback filter circuit according to a reference voltage control signal generated by the configuration circuit; the first-stage feedback filter circuit is respectively connected to the reference voltage generator, the second-stage feedback filter circuit and the configuration circuit, for receiving an input signal at time T sent by the configuration circuit and a reference voltage generated by the reference voltage generator, and determining the difference between the input signal at time T and the reference voltage. The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D-type flip-flop and the configuration circuit respectively, and is used to input different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock; the D-type flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the adopted control signal sent by the configuration circuit; the configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit and the D-type flip-flop respectively, and is used to determine the two-dimensional signal eye diagram according to the input signal at time T, the reference voltage and the output voltage.

[0009] In a second aspect, an embodiment of the present application provides a receiver, which includes the decision feedback equalizer DFE described in the first aspect.

[0010] In a third aspect, an embodiment of the present application provides a chip, which includes the decision feedback equalizer DFE described in the first aspect.

[0011] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: The decision feedback equalizer DFE provided in the embodiment of the present application includes: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D trigger and a configuration circuit; wherein the input end of the reference voltage generator is connected to the configuration circuit, and the output end of the reference voltage generator is connected to the first-stage feedback filter circuit, and is used to provide reference voltages of different sizes to the first-stage feedback filter circuit according to a reference voltage control signal generated by the configuration circuit; the first-stage feedback filter circuit is respectively connected to the reference voltage generator, the second-stage feedback filter circuit and the configuration circuit, and is used to receive an input signal at time T sent by the configuration circuit and a reference voltage generated by the reference voltage generator. The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D-type flip-flop and the configuration circuit respectively, and is used to input different sampling delays; the D-type flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the control signal sent by the configuration circuit; the configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit and the D-type flip-flop respectively, and is used to determine the two-dimensional signal eye diagram according to the input signal, the reference voltage and the output voltage at the time T. The decision feedback equalizer DFE provided in the embodiment of the present application, its feedback filter circuit is composed of two stages of circuits (comparator circuit and signal delay circuit) that can be independently set. Through these two stages of feedback filter circuits, the configuration of the two dimensions of signal sampling reference voltage and signal delay relative to the sampling clock can be independently adjusted, so as to better eliminate the inter-symbol interference from the past signal on the current signal, and improve the reliability of the sampled data. Secondly, since the first two stages of the feedback filter circuit are configured relatively independently, in actual working scenarios, the area of ​​the feedback filter circuit can be reduced while eliminating inter-symbol interference by eliminating the comparator circuit or the signal delay circuit according to the degree to which the signal sampling reference voltage and the signal slew rate are affected by inter-symbol interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a structural diagram of a second-order decision feedback equalizer DFE in the prior art; Figure 2 A schematic diagram of signal waveform changes when inter-symbol interference is eliminated based on an existing second-order decision feedback equalizer DFE; Figure 3A schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a second-order decision feedback equalizer DFE provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a simplified second-order decision feedback equalizer DFE provided in an embodiment of the present application; Figure 6 A schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of another simplified second-order decision feedback equalizer DFE provided in an embodiment of the present application; Figure 8 A schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0014] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0015] A decision feedback equalizer DFE provided in an embodiment of the present application is used to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0016] At present, decision feedback equalizer (DFE) is often used in the receiving module RX in the I / O interface to eliminate inter-symbol interference and avoid signal distortion, thereby effectively improving the receiving performance of the receiving module. The common second-order decision feedback equalizer (DFE) structure is as follows: Figure 1As shown, it mainly includes a feedback filter and a decision device. The feedback part of the second-order decision feedback equalizer DFE can use the information of the first two symbols d1 / d2 of the current symbol d0 that have been determined to determine the output of the feedback filter and determine the value of the current symbol d0. One of the working principles of the decision feedback equalizer DFE can be simply understood as adjusting the voltage value of the reference voltage to avoid sampling errors in the data receiving circuit. Since the change of the level in the data receiving circuit caused by the change of the external input data is not instantaneous (it takes a certain amount of time for the change of the level in the data receiving circuit to reach the change of the data), the increase in the data transmission rate or the increase in the frequency of the clock signal will result in a decrease in the change time of the level in the data receiving circuit. For example, when the external input data jumps from "0" to "1", due to the reduction in the change time of the level in the data receiving circuit, the level in the data receiving circuit needs to be pulled up to 0.8 under ideal conditions, but can only be pulled up to 0.6 in reality. At this time, by reducing the reference voltage to ensure that the actual level 0.6 is still greater than the reference voltage, the data receiving circuit can sample and obtain high-level input data; for another example, when the external input data jumps from "1" to "0", due to the reduction in the change time of the level in the data receiving circuit, the level in the data receiving circuit needs to be pulled down to 0.1 under ideal conditions, but can only be pulled down to 0.3 in reality. At this time, by increasing the reference voltage to ensure that the actual level 0.3 is still less than the reference voltage, the data receiving circuit can sample and obtain low-level input data.

[0017] Based on the above principle, the decision feedback equalizer DFE can reduce all subsequent effects of the current symbol in the time domain according to the decision result of the current symbol, so as to minimize the inter-symbol interference effect of the current symbol or even completely eliminate it. In circuit implementation, the decision feedback equalizer DFE can be implemented by a digital high-frequency filter. For example, for continuous input data, the input data sampled after a T-cycle delay is weighted, and then added to the current input data and output, so as to reduce or completely eliminate the inter-symbol interference of the input data.

[0018] To use Figure 1 Taking the existing second-order decision feedback equalizer DFE shown in the figure as an example to eliminate inter-symbol interference, it is assumed that data B0, B1, B2, and B3 are transmitted in sequence on the transmission line. Due to the existence of inter-symbol interference, the values ​​of B0 and B1 will affect the signal level of B2 data. Figure 2 As shown, it means that when the values ​​of B0 and B1 are 11, 01, 00, and 10 respectively, the waveform on the signal line changes. Figure 2 The shaded area in the middle represents the eye size where B2 can be correctly sampled.

[0019] According to the waveform changes on the signal line, under different combinations of B0 and B1 values, the two-dimensional signal eye diagram corresponding to the B2 data can be obtained, such as Figure 3 As shown in FIG. 1 , the center point of the two-dimensional signal eye diagram corresponds to the optimal sampling identification voltage and sampling clock delay configuration of the B2 data. It can be seen that the optimal sampling configuration of the B2 data is affected by the values ​​of B0 and B1.

[0020] Through the above analysis, it can be seen that the embodiment of the present application designs a decision feedback equalizer DFE, such as Figure 4 As shown, based on the decision feedback equalizer DFE, the values ​​of the two dimensions of the sampling reference voltage and the delay of the signal relative to the sampling clock can be adjusted in the front-stage feedback filter circuit, and then the coordinates of the X-axis (i.e., the delay of the signal relative to the sampling clock) and the Y-axis (i.e., the comparator reference voltage) in the two-dimensional signal eye diagram can be adjusted, so that the sampling point of the B2 data falls as much as possible at the center of the two-dimensional signal eye diagram, and the reliability of the sampling data can be guaranteed to the greatest extent.

[0021] like Figure 4 As shown, the decision feedback equalizer DFE provided in the embodiment of the present application is mainly composed of the following parts: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D trigger and a configuration circuit.

[0022] The input end of the reference voltage generator is connected to the configuration circuit, and the output end of the reference voltage generator is connected to the first-stage feedback filter circuit, which is used to provide reference voltages Vref of different sizes to the first-stage feedback filter circuit according to the reference voltage control signal generated by the configuration circuit.

[0023] The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit and the configuration circuit respectively, such as Figure 4 As shown, in an embodiment of the present application, the first-stage feedback filter circuit is composed of four comparator circuits, which are used to receive the input signal at time T (hereinafter referred to as d0 for the sake of convenience of description) sent by the configuration circuit and the reference voltage generated by the reference voltage generator, determine the voltage difference between the input signal at time T and the reference voltage, and output the voltage difference to the second-stage signal comparator.

[0024] In one embodiment, the four comparator circuits in the first-stage feedback filter circuit can be used to input different reference voltages when the feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values. For the sake of ease of description, the feedback signal at time T-1 is referred to as d1 feedback signal, and the feedback signal at time T-2 is referred to as d2 feedback signal.

[0025] In one implementation, the d1 feedback signal and the d2 feedback signal correspond to four different values, which may include: 11, 01, 00, 10. Figure 4 Where Vref_dfe0~Vref_dfe3 respectively indicate that when the d1 feedback signal and the d2 feedback signal are 11, 01, 00, and 10, different reference voltages are input to the comparator circuit that samples the d0 data.

[0026] It should be noted here that the first-stage feedback filter circuit consisting of four comparator circuits is only an exemplary description. In one embodiment, the first-stage feedback filter circuit can be composed of multiple comparator circuits, wherein the multiple comparator circuits include: the 0th comparator circuit to the Nth comparator circuit numbered in ascending order of natural numbers, wherein N≤3.

[0027] The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop and the configuration circuit respectively, such as Figure 4 As shown, in an embodiment of the present application, the second-stage feedback filter circuit is composed of four signal delay circuits for inputting different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock.

[0028] In one implementation, the four signal delay circuits in the second-stage feedback filter circuit can be used to input different sampling delays when the d1 feedback signal and the d2 feedback signal correspond to four different values.

[0029] In one implementation, the d1 feedback signal and the d2 feedback signal correspond to four different values, which may include: 11, 01, 00, 10. Figure 4 Where Td_delay0~Td_delay3 represent the phase delay configuration of d0 data relative to clock when d1 feedback signal and d2 feedback signal are 11, 01, 00, 10 respectively.

[0030] It should be noted here that the second-stage feedback filter circuit consisting of four signal delay circuits is only an exemplary description. In one embodiment, the second-stage feedback filter circuit can be composed of multiple signal delay circuits, wherein the multiple signal delay circuits include: the 0th signal delay circuit to the Mth signal delay circuit numbered in ascending order of natural numbers, wherein M≤3.

[0031] In the embodiment of the present application, a D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the control signal sent by the configuration circuit. The D flip-flop in the decision feedback equalizer DFE is mainly used to provide data synchronization, delay, feedback, and holding and blocking functions. For example, in the decision feedback equalizer DFE, the D flip-flop can be used to store the output data of the sampler (Slicer), which are digital signals transmitted through the channel and quantized by the sampler. The D flip-flop can store these data synchronously under the control of the clock signal to ensure that the data is processed synchronously in the decision feedback equalizer DFE; in addition, in the feedback path of the DFE circuit, the D flip-flop can provide a delay function to ensure that the feedback signal is aligned with the current signal in time. It should be noted here that the implementation of the above functions in the decision feedback equalizer DFE based on the D flip-flop belongs to the conventional technical means in the field, so the specific working principle of the D flip-flop is not described in detail in the embodiment of the present application.

[0032] The configuration circuit is respectively connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit and the D trigger, and is used to determine a two-dimensional signal eye diagram according to the input signal, the reference voltage and the output voltage at time T.

[0033] The configuration circuit in the decision feedback equalizer DFE is mainly used to implement functions such as decision feedback, correcting ISI, and adaptively adjusting tap coefficients to improve the performance and quality of the received signal. For example, the configuration circuit can correct ISI through the forward path and the feedback path. The forward path may include a CTLE or other type of equalizer, while the feedback path estimates and cancels the ISI of the current signal based on the decoded signal. It should be noted here that the implementation of the above functions in the decision feedback equalizer DFE based on the configuration circuit is a common technical means in the field, so in the embodiment of the present application, the specific working principle of the configuration circuit is not described in detail.

[0034] In addition, it should be noted that a pulse amplitude detector (PAD) is generally provided in the decision feedback equalizer DFE. The main function of the PAD is to detect and quantify the amplitude of the input signal. It is equivalent to a 1-bit analog to digital converter (ADC). In the decision feedback equalizer DFE, the PAD is usually used to convert continuous analog signals into discrete digital signals for subsequent digital signal processing.

[0035] It should be noted here that in actual scenarios, when the values ​​of the D1 feedback signal and the D2 feedback signal are 10 and 00, the reference voltage value of the comparator circuit is relatively close; and when the values ​​of the D1 feedback signal and the D2 feedback signal are 11 and 01, the reference voltage value of the comparator circuit is relatively close. In this case, when the values ​​of the D1 feedback signal and the D2 feedback signal are 10 and 00, a comparator circuit can be used to input the reference voltage; and when the values ​​of the D1 feedback signal and the D2 feedback signal are 11 and 01, a comparator circuit can be used to input the reference voltage, and then Figure 4 The decision feedback equalizer DFE shown in the figure is simplified to Figure 4 The four comparator circuits in the first-stage feedback filter circuit are reduced to two comparator circuits, and the following is obtained: Figure 5 The first simplified decision feedback equalizer DFE is shown. Figure 5 The first simplified decision feedback equalizer DFE shown can provide feedback and select different delay paths respectively by setting different permutations and combinations of the values ​​of the d1 feedback signal and the d2 feedback signal.

[0036] Specifically, using the first simplified decision feedback equalizer DFE, when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are: 10 and 00, a comparator circuit input reference voltage can be shared; and when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are: 11 and 01, another comparator circuit input reference voltage can be shared.

[0037] Assume that the data B0, B1, B2, and B3 are transmitted sequentially on the transmission line as an example. In the embodiment of the present application, Figure 5 The first simplified decision feedback equalizer DFE shown in FIG. 1 can obtain a two-dimensional signal eye diagram corresponding to the B2 data under different combinations of B0 and B1 values ​​as shown in FIG. Figure 6 shown.

[0038] In addition, it should be noted that in actual scenarios, when the values ​​of the D1 feedback signal and the D2 feedback signal are 11 and 00, the voltage conversion rate (slew rate) of the subsequent signal is greatly affected, so the optimal point of the signal sampling clock requires more delay. When the values ​​of the D1 feedback signal and the D2 feedback signal are 10 and 01, the slew rate of the subsequent signal is less affected, so the delay required for the optimal point of the signal sampling clock is smaller. In this case, when the values ​​of the D1 feedback signal and the D2 feedback signal are 11 and 00, a signal delay circuit can be shared to set the sampling delay; and when the values ​​of the D1 feedback signal and the D2 feedback signal are 10 and 01, a signal delay circuit can be shared to set the sampling delay. In this way, it can be targeted Figure 5The first simplified decision feedback equalizer DFE shown in FIG. 1 is further simplified by Figure 5 The four signal delay circuits in the first simplified decision feedback equalizer DFE shown in FIG. 1 are reduced to two signal delay circuits, and the following is obtained: Figure 7 The second simplified decision feedback equalizer DFE is shown. Figure 7 The second simplified decision feedback equalizer DFE shown can select different delay paths by feeding back the operation results (eg, XOR calculation) of the d1 feedback signal and the d2 feedback signal.

[0039] Specifically, using the second simplified decision feedback equalizer DFE, when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are: 11 and 00, a signal delay circuit input sampling delay can be shared; and when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are: 10 and 01, another signal delay circuit input sampling delay can be shared.

[0040] Assume that the data B0, B1, B2, and B3 are transmitted sequentially on the transmission line as an example. In the embodiment of the present application, Figure 7 The first simplified decision feedback equalizer DFE shown in FIG. 1 can obtain a two-dimensional signal eye diagram corresponding to the B2 data under different combinations of B0 and B1 values ​​as shown in FIG. Figure 8 shown.

[0041] The decision feedback equalizer DFE provided in the embodiment of the present application has a feedback filter circuit composed of two stages of circuits (comparator circuit and signal delay circuit) that can be independently set. Through these two stages of feedback filter circuits, the configuration of the two dimensions of signal sampling reference voltage and signal delay relative to the sampling clock can be independently adjusted, so as to better eliminate the inter-code interference from the past signal on the current signal, thereby improving the reliability of the sampled data. Secondly, since the first two stages of the feedback filter circuit of the feedback filter circuit are relatively independent in configuration, in actual working scenarios, according to the degree to which the signal sampling reference voltage and the signal slew rate are affected by the inter-code interference, by deleting the comparator circuit or the signal delay circuit, while eliminating the inter-code interference, the area of ​​the feedback filter circuit can be reduced.

[0042] In one embodiment, the present application also provides a receiver, which includes the decision feedback equalizer DFE provided by any of the above embodiments, so as to solve the problem that the second-order decision feedback equalizer DFE in the prior art can only eliminate the inter-symbol interference of a single dimension, thereby causing inaccurate sampling results and signal distortion.

[0043] In one embodiment, the present application also provides a chip, which includes the decision feedback equalizer provided by any of the above embodiments, so as to solve the problem that the second-order decision feedback equalizer DFE in the prior art can only eliminate the inter-symbol interference of a single dimension, thereby causing inaccurate sampling results and signal distortion.

[0044] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0045] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0046] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above specific implementations, which are merely illustrative and not restrictive. Any modification, equivalent substitution, improvement, etc. made by a person skilled in the art under the inspiration of the present application without departing from the purpose of the present application and the scope of protection of the claims shall be included in the scope of the claims of the present application. Many forms can also be made, all of which are within the protection of the present application.

Claims

1. A decision feedback equalizer DFE, characterized in that: include: A reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop, and a configuration circuit; The input end of the reference voltage generator is connected to the configuration circuit, and the output end of the reference voltage generator is connected to the first-stage feedback filter circuit, for providing reference voltages of different magnitudes to the first-stage feedback filter circuit according to the reference voltage control signal generated by the configuration circuit; The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit and the configuration circuit respectively, and is used to receive the input signal at time T sent by the configuration circuit and the reference voltage generated by the reference voltage generator, determine the voltage difference between the input signal at time T and the reference voltage, and output the voltage difference to the second-stage signal comparator; The second-stage feedback filter circuit is respectively connected to the first-stage feedback filter circuit, the D flip-flop and the configuration circuit, and is used to input different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock; The D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the adoption control signal sent by the configuration circuit; The configuration circuit is respectively connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit and the D trigger, and is used to determine a two-dimensional signal eye diagram according to the input signal at time T, the reference voltage and the output voltage.

2. The decision feedback equalizer DFE according to claim 1, characterized in that: The first-stage feedback filter circuit is composed of a plurality of comparator circuits, wherein the plurality of comparator circuits include: a 0th comparator circuit to an Nth comparator circuit numbered in ascending order of natural numbers, wherein N≤3.

3. The decision feedback equalizer DFE according to claim 2, characterized in that: The first-stage feedback filter circuit is composed of four comparator circuits, and the four comparator circuits are respectively used to input different reference voltages when the feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values.

4. The decision feedback equalizer DFE according to claim 3, characterized in that: The feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values, including: 11, 01, 00, and 10.

5. The decision feedback equalizer DFE according to claim 2, characterized in that: The first-stage feedback filter circuit is composed of two comparator circuits, and the two comparator circuits are respectively used to input different reference voltages when the feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values; Wherein, the corresponding values ​​of the feedback signal at time T-1 and the feedback signal at time T-2 are: when 10 and 00, a comparator circuit input reference voltage is shared; When the corresponding values ​​of the feedback signal at time T-1 and the feedback signal at time T-2 are: 11 and 01, a comparator circuit input reference voltage is shared.

6. The decision feedback equalizer DFE according to claim 1, characterized in that: The second-stage feedback filter circuit is composed of a plurality of signal delay circuits, wherein the plurality of signal delay circuits include: a 0th comparison circuit to an Mth signal delay circuit numbered in ascending order of natural numbers, wherein M≤3.

7. The decision feedback equalizer DFE according to claim 6, characterized in that: The second-stage feedback filter circuit is composed of four signal delay circuits, and the four signal delay circuits are respectively used to input different sampling delays when the feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values; The feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values, including: 11, 01, 00, and 10.

8. The decision feedback equalizer DFE according to claim 6, characterized in that: The second-stage feedback filter circuit is composed of two signal delay circuits, and the two signal delay circuits are respectively used to input different sampling delays when the feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values; The corresponding values ​​of the feedback signal at time T-1 and the feedback signal at time T-2 are: at 11 and 00, a signal delay circuit is shared to input sampling delay; When the corresponding values ​​of the feedback signal at time T-1 and the feedback signal at time T-2 are: 10 and 01, a signal delay circuit is shared to input sampling delay.

9. A receiver, characterized in that: Comprising a decision feedback equalizer DFE as described in any one of claims 1-8.

10. A chip, characterized in that: Comprising a decision feedback equalizer DFE as described in any one of claims 1-8.

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