Embedded printed circuit board layout structure and electronic equipment

Abstract

The invention provides an embedded printed circuit board layout structure and electronic equipment, and belongs to the technical field of semiconductors. In the layout structure, a plurality of chips are arranged in a chip area of the first insulating layer in an array manner. The direct current projection area of the circuit board direct current terminal on the first insulating layer is located in the chip area. The alternating current projection area of the circuit board alternating current terminal on the first insulating layer is located in the chip area. The AC projection areas and the DC projection areas are arranged at intervals. The direct-current projection area and the alternating-current projection area are located in the chip area at intervals, so that the circuit board direct-current terminal and the circuit board alternating-current terminal are arranged close to a plurality of chips and are arranged more tightly, the space in the chip area can be fully utilized, the occupied space of the printed circuit board is small, the board surface area of the printed circuit board is reduced, and the cost is reduced. The problem that in the prior art, the board area is too large is solved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to an embedded printed circuit board layout structure and an electronic device. Background Art

[0002] Printed Circuit Board (PCB) is an important component of electronic equipment. PCB includes insulating substrate, conductive circuit and various electronic components (such as chips, resistors, capacitors, etc.). Among them, it is particularly important to arrange the positions of electronic components (such as chips, resistors, capacitors, inductors, etc.) and wiring (conductive circuits connecting various components) on the surface of PCB reasonably.

[0003] However, in the conventional layout structure, the DC input terminal and the AC output terminal are respectively arranged at the edge positions of two opposite sides of the printed circuit board, resulting in an excessively large board area. Summary of the invention

[0004] The purpose of the present application is to provide an embedded printed circuit board layout structure and an electronic device, aiming to solve the problem of excessively large board area existing in a traditional printed circuit board layout structure.

[0005] The present application provides an embedded printed circuit board layout structure, comprising:

[0006] A plurality of chips are arranged in an array in a chip region of the first insulating layer;

[0007] A circuit board DC terminal, wherein a DC projection area of ​​the first insulating layer is located in the chip area;

[0008] The AC terminal of the circuit board has an AC projection area on the first insulating layer located within the chip area, and the AC projection area and the DC projection area are arranged at intervals.

[0009] In one embodiment, within the chip region, a plurality of chip arrays are arranged into a first concave region;

[0010] The DC projection area is located between the first concave area and the chip area.

[0011] In one embodiment, the circuit board DC terminal comprises:

[0012] a first sub-DC terminal, located between the first concave area and the chip area in a first sub-DC projection area of ​​the first insulating layer;

[0013] a second sub-DC terminal, located between the first concave area and the chip area in a second sub-DC projection area of ​​the first insulating layer;

[0014] The second sub-DC projection area is arranged close to the first sub-DC projection area, and the second sub-DC projection area and the first sub-DC projection area are arranged side by side with an interval.

[0015] In one embodiment, the second sub DC projection area is arranged between two adjacent chips.

[0016] In one embodiment, in the chip area, a plurality of the chip arrays are arranged into a first convex area;

[0017] The DC projection area is located between the first convex area and the chip area.

[0018] In one embodiment, the circuit board DC terminal comprises:

[0019] a first sub-DC terminal, located between the first convex area and the chip area in a first sub-DC projection area of ​​the first insulating layer;

[0020] A first terminal, located between the first convex area and the chip area in a first projection area of ​​the first insulating layer;

[0021] a second terminal located between the first convex region and the chip region in a second projection region of the first insulating layer;

[0022] The first sub-DC projection area is arranged close to the first projection area and the second projection area, and the first sub-DC projection area is arranged side by side with the first projection area and the second projection area respectively.

[0023] In one embodiment, the first projection area and the second projection area are arranged in the same column or the same row, and at least one chip is arranged between the first projection area and the second projection area.

[0024] In one embodiment, within the chip region, a plurality of chip arrays are arranged into a second concave region;

[0025] The AC projection area is located between the second concave area and the chip area.

[0026] In one embodiment, the AC projection area is disposed between two adjacent chips.

[0027] In one embodiment, within the chip region, a plurality of chip arrays are arranged into a second convex region;

[0028] The AC projection area is located between the second convex area and the chip area.

[0029] In one embodiment, the circuit board AC terminal comprises:

[0030] A first sub-AC terminal, projected on the first insulating layer to form a first sub-AC projection (231);

[0031] A second sub-AC terminal, projected on the first insulating layer to form a second sub-AC projection;

[0032] The first sub-AC projection and the second sub-AC projection are arranged in the same column or the same row, and at least one chip is arranged between the first sub-AC projection and the second sub-AC projection.

[0033] In one embodiment, the circuit board DC terminal and the circuit board AC terminal are arranged on the first insulating layer.

[0034] In one embodiment, the embedded printed circuit board layout structure further includes:

[0035] A second insulating layer, stacked with the first insulating layer;

[0036] The second insulating layer is provided with the circuit board DC terminal and / or the circuit board AC terminal.

[0037] In one embodiment, the embedded printed circuit board layout structure further includes:

[0038] At least one conductive layer, stacked with the first insulating layer;

[0039] The plurality of chips are respectively connected to the circuit board DC terminal and the circuit board AC terminal through metal traces on the conductive layer.

[0040] The present application provides an electronic device, comprising the embedded printed circuit board layout structure described in any one of the above embodiments.

[0041] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0042] By dividing the chip area on the first insulating layer, multiple chips can be concentrated together in an array arrangement, shortening the connection lines between multiple chips, thereby improving the space utilization and wiring efficiency of the printed circuit board. The DC projection area and the AC projection area are located in the chip area, so that the DC terminals of the circuit board and the AC terminals of the circuit board are arranged close to multiple chips, and the layout is closer to each other. The DC projection area and the AC projection area are located in the chip area, which can make full use of the space in the chip area, occupy less space on the printed circuit board, and reduce the board area of ​​the printed circuit board.

[0043] The DC projection area and the AC projection area are located in the chip area, which can shorten the relative distance between the DC terminal of the circuit board and the AC terminal of the circuit board and the multiple chips, and then shorten the connection lines between each other, and quickly achieve connection between each other with a shorter path. Furthermore, the connection lines between the multiple chips and the DC terminal of the circuit board and the AC terminal of the circuit board are shortened, which can also reduce the board area occupied by the connection lines. Therefore, through the embedded printed circuit board layout structure provided by the present application, the board area of ​​the printed circuit board can be reduced from multiple dimensions, solving the problem of excessive board area in traditional technology.

[0044] Furthermore, through the embedded printed circuit board layout structure provided by the present application, a highly integrated layout design is achieved, which can shorten the connection lines between the circuit board DC terminal and the circuit board AC terminal and multiple chips, so that the parasitic inductance generated by the connection lines is also reduced. In addition, through the embedded printed circuit board layout structure provided by the present application, the board area of ​​the printed circuit board is reduced, which can further reduce the manufacturing cost and improve the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 This is a schematic diagram of the layout structure of an embedded printed circuit board in some embodiments provided in this application.

[0046] Figure 2 This is a schematic diagram of a concave layout of an embedded printed circuit board layout structure in some embodiments provided in the present application.

[0047] Figure 3 Schematic diagram of the connection structure between the external positive electrode connection structure, the external negative electrode connection structure and the first sub-DC terminal and the second sub-DC terminal respectively in some embodiments provided in the present application.

[0048] Figure 4 It is a cross-sectional schematic diagram of a front view of an external positive electrode connection structure and an external negative electrode connection structure in some embodiments provided in the present application.

[0049] Figure 5 Schematic diagram of convex layout and concave layout in some embodiments provided in this application.

[0050] Figure 6 This is a schematic diagram of the structure of the circuit board DC terminal and the circuit board AC terminal in some embodiments provided in the present application.

[0051] Figure 7 Schematic diagram of convex-convex layout and convex-convex layout in some embodiments provided in this application.

[0052] Figure 8Schematic diagram of the connection structure between the external positive electrode connection structure, the external negative electrode connection structure and the first sub-DC terminal, the first terminal and the second terminal respectively in some embodiments provided in the present application.

[0053] Fig. 9 Schematic diagram of convex layout and concave layout in some embodiments provided in this application.

[0054] Fig.10 Schematic diagram of concave layout and convex layout in some embodiments provided in this application.

[0055] Fig.11 This is a schematic diagram of the structure of the circuit board DC terminal and the circuit board AC terminal in some embodiments provided in the present application.

[0056] Fig.12 Schematic diagram of convex-convex layout and convex-convex layout in some embodiments provided in this application.

[0057] Fig.13 Schematic diagram of the connection structure between the external load connection structure and the first sub-AC terminal and the second sub-AC terminal in some embodiments provided in the present application.

[0058] Fig.14 This is a schematic structural diagram of the circuit board DC terminal and the circuit board AC terminal in the second insulating layer in some embodiments provided in the present application.

[0059] Fig.15 This is a schematic structural diagram of a conductive layer, a first insulating layer, and a second insulating layer in an embedded printed circuit board layout structure in some embodiments provided in the present application. DETAILED DESCRIPTION

[0060] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0061] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0062] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0063] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0064] See also Figure 1 The present application provides an embedded printed circuit board layout structure 100. The embedded printed circuit board layout structure 100 includes a plurality of chips 10, a first insulating layer 20, a circuit board DC terminal 30 and a circuit board AC terminal 40.

[0065] A plurality of chips 10 are arrayed in a chip region 210 of a first insulating layer 20. A DC terminal 30 of a circuit board is located in a DC projection region 220 of the first insulating layer 20 in the chip region 210. An AC terminal 40 of a circuit board is located in an AC projection region 230 of the first insulating layer 20 in the chip region 210. The AC projection region 230 is arranged alternately with the DC projection region 220.

[0066] In this embodiment, a plurality of chips 10 are arranged in an array in the first insulating layer 20. The first insulating layer 20 serves to insulate the plurality of chips 10. The chip region 210 can be understood as a region where a plurality of chips 10 are arranged in an array. By dividing the chip region 210 on the first insulating layer 20, the plurality of chips 10 can be concentrated together in an array arrangement, shortening the connection lines between the plurality of chips 10, thereby improving the space utilization and wiring efficiency of the printed circuit board.

[0067] The circuit board DC terminal 30 can be understood as a DC input terminal, which is an interface component for connecting an external DC power supply. The circuit board DC terminal 30 can be used to introduce the current of an external device (such as an external DC voltage source or an external capacitor device, etc.) into the circuit inside the PCB, and provide the required electrical energy for each electronic component (such as multiple chips 10) in the PCB. The DC projection area 220 of the circuit board DC terminal 30 on the first insulating layer 20 can be understood as the area occupied by the circuit board DC terminal 30 on the first insulating layer 20. The circuit board DC terminal 30 can be arranged on the same layer as the multiple chips 10, or it can be arranged on a different layer. In the present application, the projection area can be the projection area corresponding to when the circuit board DC terminal 30 is arranged on the first insulating layer 20, or it can be the projection area formed on the first insulating layer 20 when the circuit board DC terminal 30 is arranged on other insulating layers.

[0068] The AC projection area 230 of the circuit board AC terminal 40 on the first insulating layer 20 can be understood as the area occupied by the circuit board AC terminal 40 on the first insulating layer 20. The circuit board AC terminal 40 can be arranged on the same layer as the multiple chips 10, or it can be arranged on a different layer. In the present application, the projection area can be the projection area corresponding to when the circuit board AC terminal 40 is arranged on the first insulating layer 20, or it can be the projection area formed on the first insulating layer 20 when the circuit board AC terminal 40 is arranged on other insulating layers. When the circuit board DC terminal 30 and the circuit board AC terminal 40 are respectively connected to the multiple chips 10, the connection is achieved through the vias between the various film layers in the printed circuit board.

[0069] The DC projection area 220 and the AC projection area 230 are spaced apart and located in the chip area 210, so that the circuit board DC terminal 30 and the circuit board AC terminal 40 are arranged close to the multiple chips 10, and the layout between them is more compact. The DC projection area 220 and the AC projection area 230 are spaced apart and located in the chip area 210, which can make full use of the space in the chip area 210, occupying less space on the printed circuit board, and reducing the board area of ​​the printed circuit board.

[0070] The DC projection area 220 and the AC projection area 230 are located in the chip area 210, which can shorten the relative distance between the circuit board DC terminal 30 and the circuit board AC terminal 40 and the multiple chips 10, thereby shortening the connection lines between each other, and quickly realizing the connection between each other with a shorter path. Furthermore, the connection lines between the multiple chips 10 and the circuit board DC terminal 30 and the circuit board AC terminal 40 are shortened, which can also reduce the board area occupied by the connection lines. Therefore, through the embedded printed circuit board layout structure 100 provided by the present application, the board area of ​​the printed circuit board can be reduced from multiple dimensions, solving the problem of excessive board area in traditional technology.

[0071] Furthermore, the embedded printed circuit board layout structure 100 provided by the present application realizes a highly integrated layout design, which can shorten the connection lines between the circuit board DC terminal 30 and the circuit board AC terminal 40 and the plurality of chips 10, respectively, so that the parasitic inductance generated by the connection lines is also reduced. In addition, the embedded printed circuit board layout structure 100 provided by the present application reduces the board area of ​​the printed circuit board, which can further reduce the manufacturing cost and improve the production efficiency.

[0072] Furthermore, through the embedded printed circuit board layout structure 100 provided in the present application, multiple chips 10, circuit board DC terminals 30 and circuit board AC terminals 40 can be concentratedly and evenly arranged in the chip area 210, avoiding the problem of printed circuit board warping caused by unbalanced weight distribution.

[0073] See also Figure 2 In one embodiment, in the chip area 210 , a plurality of chips 10 are arrayed to form a first concave area 211 . The DC projection area 220 is located between the first concave area 211 and the chip area 210 .

[0074] In this embodiment, the first concave region 211 can be understood as a concave region formed by a plurality of chips 10 arranged in the first insulating layer 20 and arranged in combination. Figure 2 As shown, the plurality of chips 10 on the left are arranged in a concave shape. Further, an additional accommodation area is formed between the first concave area 211 and the chip area 210. In the additional accommodation area, a DC projection area 220 can be arranged.

[0075] Thus, the circuit board DC terminal 30 can be arranged in the DC projection area 220 of the first insulating layer 20. The circuit board DC terminal 30 and the multiple chips 10 are arranged in the same insulating layer. Alternatively, the circuit board DC terminal 30 can be arranged in another insulating layer stacked with the first insulating layer 20, and the circuit board DC terminal 30 forms a DC projection area 220 on the first insulating layer 20.

[0076] By arranging the DC projection area 220 between the first concave area 211 and the chip area 210, the area outside the chip occupied space in the chip area 210 is fully utilized, so that the circuit board DC terminals 30 and multiple chips 10 are concentrated together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0077] Furthermore, the DC projection area 220 is located between the first concave area 211 and the chip area 210, so that the circuit board DC terminal 30 can be arranged close to the multiple chips 10. Since the connection between the circuit board DC terminal 30 and the multiple chips 10 needs to be realized through the metal traces on the conductive layer and the vias between the conductive layer and the insulating layer, the circuit board DC terminal 30 is arranged close to the multiple chips 10, which can shorten the connection line between the circuit board DC terminal 30 and the multiple chips 10. Furthermore, the connection line is reduced, which can also reduce the board area occupied by the connection line, and can also reduce the parasitic inductance generated by the connection line.

[0078] In one embodiment, the circuit board DC terminal 30 includes a first sub-DC terminal 310 and a second sub-DC terminal 320. The first sub-DC terminal 310 is located between the first concave area 211 and the chip area 210 in the first sub-DC projection area 221 of the first insulating layer 20. The second sub-DC terminal 320 is located between the first concave area 211 and the chip area 210 in the second sub-DC projection area 222 of the first insulating layer 20. The second sub-DC projection area 222 is arranged close to the first sub-DC projection area 221. The second sub-DC projection area 222 is arranged side by side with the first sub-DC projection area 221 at an interval.

[0079] In this embodiment, the circuit board DC terminal 30 includes two DC terminals. Among them, the first sub-DC terminal 310 can be a positive terminal of the circuit board, and the second sub-DC terminal 320 can be a negative terminal of the circuit board. Alternatively, the first sub-DC terminal 310 can be a negative terminal of the circuit board, and the second sub-DC terminal 320 can be a positive terminal of the circuit board. The first sub-DC terminal 310 and the second sub-DC terminal 320 are respectively used to connect to the positive electrode and the negative electrode (or both ends) of an external device (such as an external DC voltage source or an external capacitor device, etc.).

[0080] The first sub-DC projection area 221 is located between the first concave area 211 and the chip area 210, making full use of the area outside the chip occupied space in the chip area 210, so that the first sub-DC terminal 310 and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0081] The second sub-DC projection area 222 is located between the first concave area 211 and the chip area 210, making full use of the area outside the chip occupied space in the chip area 210, so that the second sub-DC terminal 320 and multiple chips 10 are arranged together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0082] The second sub-DC projection area 222 and the first sub-DC projection area 221 are arranged close to each other and spaced apart from each other, so that the second sub-DC terminal 320 and the first sub-DC terminal 310 are arranged close to each other and spaced apart from each other, making the layout structure of the entire printed circuit board more compact, thereby reducing the board area of ​​the printed circuit board.

[0083] See also Figure 3 , the first sub-DC terminal 310 is connected to the positive electrode of the external device to form an external positive electrode connection structure 710, and the second sub-DC terminal 320 is connected to the negative electrode of the external device to form an external negative electrode connection structure 720. The external positive electrode connection structure 710 flows out from the external negative electrode connection structure 720 after passing through the printed circuit board, thereby forming an external connection loop between the external positive electrode connection structure 710 and the external negative electrode connection structure 720. The second sub-DC projection area 222 is arranged close to the first sub-DC projection area 221, so that the second sub-DC terminal 320 can be arranged close to the first sub-DC terminal 310, thereby making the positive terminal and the negative terminal of the circuit board close to each other. When the second sub-DC terminal 320 is close to the first sub-DC terminal 310, the external connection loop formed between the two DC terminals can be shortened, thereby reducing the parasitic inductance formed by the external connection loop.

[0084] The second DC sub-projection area 222 is arranged close to and spaced apart from the first DC sub-projection area 221, so that the second DC sub-terminal 320 and the first DC sub-terminal 310 are arranged close to and spaced apart from each other. Thus, a laminated structure is formed between the external negative electrode connection structure 720 formed when the second DC sub-terminal 320 is connected to the negative electrode of an external device and the external positive electrode connection structure 710 formed when the first DC sub-terminal 310 is connected to the positive electrode of an external device. The laminated structure can be understood as an overlapped portion between the external negative electrode connection structure 720 and the external positive electrode connection structure 710. Figure 4 As shown, since the current flows in opposite directions between the external negative connection structure 720 and the external positive connection structure 710, magnetic fields in opposite directions will be superimposed and cancel each other out, so that the induced electromotive force caused by the magnetic field change will also be reduced, reducing the parasitic inductance formed by the external connection loop.

[0085] Furthermore, the first sub-DC terminal 310 is located between the first concave area 211 and the chip area 210 in the first sub-DC projection area 221 of the first insulating layer 20, and the second sub-DC terminal 320 is located between the first concave area 211 and the chip area 210 in the second sub-DC projection area 222 of the first insulating layer 20, which can make full use of the chip area 210 and avoid the warping problem of the printed circuit board caused by the existence of excess space in the chip area 210.

[0086] In one embodiment, the first DC sub-terminal 310 is electrically connected to the external positive electrode connection structure 710 by welding. The second DC sub-terminal 320 is electrically connected to the external negative electrode connection structure 720 by welding. In addition, the external positive electrode connection structure 710 and the external negative electrode connection structure 720 are insulated from each other.

[0087] In one embodiment, the second sub DC projection area 222 is disposed between two adjacent chips 10 .

[0088] In this embodiment, in the first concave area 211, a second sub-DC projection area 222 is provided between two adjacent chips 10, so that the two adjacent chips 10 serve as the concave position of the concave layout structure. Furthermore, the second sub-DC projection area 222 can fill the chip area outside the first concave area 211, so that the distribution of various devices in the printed circuit board is more concentrated and uniform, reducing the board area and improving the space utilization rate of the printed circuit board.

[0089] In one embodiment, when the second sub-DC terminal 320 and the multiple chips 10 are located in the same first insulating layer 20 , the second sub-DC terminal 320 is spaced apart from two adjacent chips 10 .

[0090] In one embodiment, when the second sub-DC terminal 320 and the plurality of chips 10 are located in different insulation layers, the second sub-DC projection area 222 of the second sub-DC terminal 320 on the first insulation layer 20 is exactly located between two adjacent chips 10 .

[0091] See also Figure 5 In one embodiment, within the chip region 210 , a plurality of chips 10 are arrayed to form a first convex region 212 . The DC projection region 220 is located between the first convex region 212 and the chip region 210 .

[0092] In this embodiment, the first convex region 212 can be understood as a convex region formed by a plurality of chips 10 arranged in the first insulating layer 20 and arranged in combination. Figure 5 As shown, the plurality of chips 10 on the left are arranged in a convex shape. Further, an additional accommodation area is formed between the first convex area 212 and the chip area 210. In the additional accommodation area, a DC projection area 220 can be arranged.

[0093] Thus, the circuit board DC terminal 30 can be arranged in the DC projection area 220 of the first insulating layer 20. By arranging the DC projection area 220 between the first convex area 212 and the chip area 210, the area outside the chip occupied space in the chip area 210 is fully utilized, so that the circuit board DC terminal 30 and multiple chips 10 are concentrated together, avoiding the terminal occupying a larger board area when arranged, and improving the space utilization rate of the printed circuit board.

[0094] Furthermore, the DC projection area 220 is located between the first convex area 212 and the chip area 210, so that the circuit board DC terminal 30 can be arranged close to the multiple chips 10 to shorten the connection line between the circuit board DC terminal 30 and the multiple chips 10. Furthermore, the connection lines are reduced, the board area occupied by the connection lines can also be reduced, and the parasitic inductance generated by the connection lines can also be reduced.

[0095] See also Figure 6 In one embodiment, the circuit board DC terminal 30 includes a first sub-DC terminal 310, a first terminal 321, and a second terminal 322. The first sub-DC terminal 310 is located between the first convex area 212 and the chip area 210 in the first sub-DC projection area 221 of the first insulating layer 20. The first terminal 321 is located between the first convex area 212 and the chip area 210 in the first projection area 223 of the first insulating layer 20. The second terminal 322 is located between the first convex area 212 and the chip area 210 in the second projection area 224 of the first insulating layer 20.

[0096] See also Figure 7 The first sub-DC projection area 221 is arranged close to the first projection area 223 and the second projection area 224. The first sub-DC projection area 221 is arranged side by side with the first projection area 223 and the second projection area 224, respectively.

[0097] In this embodiment, the circuit board DC terminal 30 includes two DC terminals, and the first terminal 321 and the second terminal 322 are used together as different parts of a DC terminal. Among them, the first sub-DC terminal 310 can be the positive terminal of the circuit board, and the first terminal 321 and the second terminal 322 are used together as the negative terminal of the circuit board. Alternatively, the first sub-DC terminal 310 can be the negative terminal of the circuit board, and the first terminal 321 and the second terminal 322 are used together as the positive terminal of the circuit board. The first sub-DC terminal 310 and the first terminal 321 and the second terminal 322 are respectively used to connect to the positive electrode and the negative electrode (or both ends) of an external device (such as an external DC voltage source or an external capacitor device, etc.).

[0098] The first sub-DC projection area 221 is located between the first convex area 212 and the chip area 210, making full use of the area outside the chip occupied space in the chip area 210, so that the first sub-DC terminal 310 and multiple chips 10 are concentrated together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0099] The second projection area 224 and the first projection area 223 are spaced apart and arranged between the first convex area 212 and the chip area 210, making full use of the area outside the chip occupied space in the chip area 210, so that the first terminal 321 and the second terminal 322 and multiple chips 10 are concentrated together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0100] The first sub-DC projection area 221 is respectively close to and spaced apart from the first projection area 223 and the second projection area 224, so that the first sub-DC terminal 310 is respectively close to and spaced apart from the first terminal 321 and the second terminal 322, making the layout structure of the entire printed circuit board more compact, thereby reducing the board area of ​​the printed circuit board.

[0101] See also Figure 8 The first DC sub-terminal 310 is connected to the positive electrode of the external device to form an external positive electrode connection structure 710. The first terminal 321 is connected to the negative electrode of the external device, and the second terminal 322 is connected to the negative electrode of the external device to form an external negative electrode connection structure 720.

[0102] After passing through the printed circuit board, the external positive connection structure 710 flows out from the external negative connection structure 720, thereby forming an external connection loop between the external positive connection structure 710 and the external negative connection structure 720. The first sub-DC projection area 221 is respectively arranged close to the first projection area 223 and the second projection area 224, so that the first sub-DC terminal 310 is respectively arranged close to the first terminal 321 and the second terminal 322, thereby making the positive terminal and the negative terminal of the circuit board close to each other. When the first sub-DC terminal 310 is respectively arranged close to the first terminal 321 and the second terminal 322, the external connection loop formed between the DC terminals can be shortened, thereby reducing the parasitic inductance formed by the external connection loop.

[0103] The first DC sub-projection area 221 is respectively arranged close to and spaced apart from the first projection area 223 and the second projection area 224, so that the first DC sub-terminal 310 is respectively arranged close to and spaced apart from the first terminal 321 and the second terminal 322. Figure 4As shown, a stacked structure is formed between the external negative electrode connection structure 720 and the external positive electrode connection structure 710, and magnetic fields in opposite directions are superimposed and offset each other, thereby reducing the parasitic inductance formed by the external connection loop.

[0104] Furthermore, the first terminal 321 and the second terminal 322 are dispersedly arranged, so that the corresponding external negative electrode connection structure 720 and the external positive electrode connection structure 710 can cover more stacking area, so as to reduce the parasitic inductance.

[0105] Furthermore, the first sub-DC terminal 310 is located between the first convex area 212 and the chip area 210 in the first sub-DC projection area 221 of the first insulating layer 20, and the first terminal 321 is located between the first convex area 212 and the chip area 210 in the first projection area 223 of the first insulating layer 20, and the second terminal 322 is located between the first convex area 212 and the chip area 210 in the second projection area 224 of the first insulating layer 20, which can make full use of the chip area 210 and avoid the warping problem of the printed circuit board caused by the existence of excess space in the chip area 210.

[0106] In one embodiment, when the first terminal 321 and the second terminal 322 are respectively connected to the external negative electrode connection structure 720, they are electrically connected by welding. Due to the layout structure of the first terminal 321 and the second terminal 322, the external negative electrode connection structure 720 can be set to a U-shaped structure. Figure 3 In the structure shown, both the external negative electrode connection structure 720 and the external positive electrode connection structure 710 can be configured as an I-shaped structure.

[0107] In one embodiment, the first projection area 223 and the second projection area 224 are arranged in the same row (eg Figure 7 ) or the same line (as Fig. 9 As shown), at least one chip 10 is disposed between the first projection area 223 and the second projection area 224.

[0108] In this embodiment, at least one chip 10 is arranged between the first projection area 223 and the second projection area 224 in the first convex area 212, so that at least one chip 10 between the first projection area 223 and the second projection area 224 forms a convex position of the convex layout structure. Furthermore, the first projection area 223 and the second projection area 224 can fill the chip area outside the first convex area 212, so that the distribution of various devices in the printed circuit board is more concentrated and uniform, reducing the board area and improving the space utilization rate of the printed circuit board.

[0109] In one embodiment, when the first terminal 321 and the second terminal 322 and the plurality of chips 10 are located in the same first insulating layer 20 , the first terminal 321 and the second terminal 322 are spaced apart from at least one chip 10 therebetween.

[0110] In one embodiment, when the first terminal 321 and the second terminal 322 and the multiple chips 10 are located in different insulating layers, the first terminal 321 and the second terminal 322 just fall on two sides of at least one chip 10 in the first projection area 223 and the second projection area 224 of the first insulating layer 20 .

[0111] See also Fig. 9 In one embodiment, in the chip area 210 , a plurality of chips 10 are arrayed to form a second concave area 213 . The AC projection area 230 is located between the second concave area 213 and the chip area 210 .

[0112] In this embodiment, the second concave region 213 can be understood as a concave region formed by a plurality of chips 10 arranged in the first insulating layer 20 and arranged in combination. Fig. 9 As shown, the plurality of chips 10 on the right are arranged in a concave shape. Further, an additional accommodation area is formed between the second concave area 213 and the chip area 210. In the additional accommodation area, an AC projection area 230 can be arranged.

[0113] Thus, the circuit board AC terminal 40 can be arranged in the AC projection area 230 of the first insulating layer 20. The circuit board AC terminal 40 and the multiple chips 10 are arranged in the same insulating layer. Alternatively, the circuit board AC terminal 40 can be arranged in another insulating layer stacked with the first insulating layer 20, and the circuit board AC terminal 40 forms an AC projection area 230 on the first insulating layer 20.

[0114] By arranging the AC projection area 230 between the second concave area 213 and the chip area 210, the area outside the chip occupied space in the chip area 210 is fully utilized, so that the circuit board AC terminals 40 and multiple chips 10 are concentrated together, avoiding the terminals occupying a larger board area when arranged, and improving the space utilization of the printed circuit board.

[0115] Furthermore, the AC projection area 230 is located between the second concave area 213 and the chip area 210, so that the circuit board AC terminal 40 can be arranged close to the multiple chips 10. Since the connection between the circuit board AC terminal 40 and the multiple chips 10 needs to be realized through the metal traces on the conductive layer and the vias between the conductive layer and the insulating layer, the circuit board AC terminal 40 is arranged close to the multiple chips 10, which can shorten the connection line between the circuit board AC terminal 40 and the multiple chips 10. Furthermore, the connection line is reduced, which can reduce the board area occupied by the connection line, and can also reduce the parasitic inductance generated by the connection line.

[0116] In one embodiment, the AC projection area 230 is disposed between two adjacent chips 10 .

[0117] In this embodiment, in the second concave area 213, an AC projection area 230 is provided between two adjacent chips 10, so that the two adjacent chips 10 serve as the concave position of the concave layout structure. Furthermore, the AC projection area 230 can fill the chip area outside the second concave area 213, so that the distribution of various devices in the printed circuit board is more concentrated and uniform, reducing the board area and improving the space utilization rate of the printed circuit board.

[0118] Furthermore, the AC projection area 230 is disposed between two adjacent chips 10 , so that the chip area 210 can be fully utilized, thereby avoiding the warping problem of the printed circuit board caused by the redundant space in the chip area 210 .

[0119] See also Fig.10 In one embodiment, within the chip region 210 , a plurality of chips 10 are arrayed to form a second convex region 214 . The AC projection region 230 is located between the second convex region 214 and the chip region 210 .

[0120] In this embodiment, the second convex region 214 can be understood as a convex region formed by a plurality of chips 10 arranged in the first insulating layer 20 and arranged in combination. Fig.10 As shown, the plurality of chips 10 on the right are arranged in a convex shape. Further, an additional accommodation area is formed between the second convex area 214 and the chip area 210. In the additional accommodation area, an AC projection area 230 can be arranged.

[0121] Thus, the circuit board AC terminal 40 can be arranged in the AC projection area 230 of the first insulating layer 20. By arranging the AC projection area 230 between the second convex area 214 and the chip area 210, the area outside the chip occupied space in the chip area 210 is fully utilized, so that the circuit board AC terminal 40 and multiple chips 10 are concentrated together, avoiding the terminal occupying a larger board area when arranged, and improving the space utilization rate of the printed circuit board.

[0122] Furthermore, the AC projection area 230 is located between the second convex area 214 and the chip area 210, so that the circuit board AC terminal 40 can be arranged close to the multiple chips 10 to shorten the connection line between the circuit board AC terminal 40 and the multiple chips 10. In addition, the connection lines are reduced, the board area occupied by the connection lines can also be reduced, and the parasitic inductance generated by the connection lines can also be reduced.

[0123] See also Fig.10 and Fig.11 In one embodiment, the circuit board AC terminal 40 includes a first sub-AC terminal 410 and a second sub-AC terminal 420. The first sub-AC terminal 410 is projected on the first insulating layer 20 to form a first sub-AC projection 231. The second sub-AC terminal 420 is projected on the first insulating layer 20 to form a second sub-AC projection 232. The first sub-AC projection 231 and the second sub-AC projection 232 are arranged in the same row (e.g. Fig.10 ) or the same line (as Fig.12 At least one chip 10 is disposed between the first sub-AC projection 231 and the second sub-AC projection 232.

[0124] In this embodiment, the first sub-AC terminal 410 and the second sub-AC terminal 420 are used together as the circuit board AC terminal 40. It can also be understood that the first sub-AC terminal 410 and the second sub-AC terminal 420 are two different parts of the circuit board AC terminal 40, which are connected to an external AC load (such as a load that requires an AC signal, such as a motor of a vehicle inverter system). The circuit board AC terminal 40 serves as the output end of the printed circuit board.

[0125] In the second convex area 214, at least one chip 10 is arranged between the first sub-AC projection 231 and the second sub-AC projection 232, so that at least one chip 10 between the first sub-AC projection 231 and the second sub-AC projection 232 forms a convex position of the convex layout structure. Furthermore, the first sub-AC projection 231 and the second sub-AC projection 232 can fill the chip area outside the second convex area 214, so that the distribution of various devices in the printed circuit board is more concentrated and uniform, reducing the board area and improving the space utilization rate of the printed circuit board.

[0126] In one embodiment, when the first sub AC terminal 410 and the second sub AC terminal 420 and the multiple chips 10 are located in the same first insulating layer 20 , the first sub AC terminal 410 and the second sub AC terminal 420 are spaced apart from at least one chip 10 therebetween.

[0127] In one embodiment, when the first sub-AC terminal 410 and the second sub-AC terminal 420 are located in different insulating layers from the multiple chips 10 , the first sub-AC projection 231 and the second sub-AC projection 232 of the first sub-AC terminal 410 and the second sub-AC terminal 420 on the first insulating layer 20 just fall on both sides of at least one chip 10 .

[0128] Furthermore, at least one chip 10 is disposed between the first AC sub-projection 231 and the second AC sub-projection 232 , so that the chip area 210 can be fully utilized and the warping problem of the printed circuit board caused by the redundant space in the chip area 210 can be avoided.

[0129] See also Fig.13 In one embodiment, the first sub-AC terminal 410 and the second sub-AC terminal 420 are both connected to an external load to form an external load connection structure 730. The first sub-AC terminal 410 and the second sub-AC terminal 420 are electrically connected to the external load connection structure 730 by welding. Due to the layout structure of the first sub-AC terminal 410 and the second sub-AC terminal 420, the external load connection structure 730 can be set to a U-shaped structure. Or, as Figure 6 In the layout structure of the circuit board AC terminal 40 shown, the external load connection structure 730 can also be set to an I-shaped structure.

[0130] In one embodiment, the circuit board DC terminal 30 and the circuit board AC terminal 40 are disposed on the first insulating layer 20 .

[0131] In this embodiment, the circuit board DC terminal 30 and the circuit board AC terminal 40 can be arranged in the same insulating layer, and arranged in the first insulating layer 20 with the plurality of chips 10. When the circuit board DC terminal 30 and the circuit board AC terminal 40 are arranged in the first insulating layer 20, the space in the first insulating layer 20 can be fully utilized, reducing the complexity and difficulty of wiring in the printed circuit board. Furthermore, when the circuit board DC terminal 30 and the circuit board AC terminal 40 are arranged in the first insulating layer 20, the external connection line is more compact, which is conducive to centralized management and allocation.

[0132] In one embodiment, the circuit board DC terminal 30 and the circuit board AC terminal 40 are arranged at the edge of the first insulating layer 20, which can shorten the length of the connection structure when the circuit board DC terminal 30 and the circuit board AC terminal 40 are respectively connected to external devices (which can also be understood as the length of the connection line), thereby reducing the parasitic inductance of the external connection structure.

[0133] See also Fig.14 In one embodiment, the embedded printed circuit board layout structure 100 further includes:

[0134] A second insulating layer 50 is stacked with the first insulating layer 20;

[0135] The second insulating layer 50 is provided with a circuit board DC terminal 30 and / or a circuit board AC terminal 40 .

[0136] In this embodiment, the second insulating layer 50 is provided with a circuit board DC terminal 30 and / or a circuit board AC terminal 40, which can be understood as the second insulating layer 50 is provided with a circuit board DC terminal 30, or the second insulating layer 50 is provided with a circuit board AC terminal 40, or the second insulating layer 50 is provided with a circuit board DC terminal 30 and a circuit board AC terminal 40.

[0137] The circuit board DC terminal 30 and the circuit board AC terminal 40 may be arranged in the same second insulating layer 50 , or in different insulating layers, and may be arranged according to actual application scenarios.

[0138] In one embodiment, the circuit board DC terminal 30 is disposed on the first insulating layer 20 , and the circuit board AC terminal 40 is disposed on the second insulating layer 50 . Alternatively, the circuit board AC terminal 40 is disposed on the first insulating layer 20 , and the circuit board DC terminal 30 is disposed on the second insulating layer 50 .

[0139] In one embodiment, the embedded printed circuit board layout structure 100 further includes a third insulating layer, the circuit board DC terminal 30 is disposed on the third insulating layer, and the circuit board AC terminal 40 is disposed on the second insulating layer 50. Alternatively, the circuit board AC terminal 40 is disposed on the third insulating layer, and the circuit board DC terminal 30 is disposed on the second insulating layer 50.

[0140] By arranging the circuit board DC terminal 30 , the circuit board AC terminal 40 and the chip 10 in different insulating layers, the risk of crosstalk between the circuit board DC terminal 30 , the circuit board AC terminal 40 and the chip 10 can be reduced, thereby improving safety.

[0141] See also Fig.15 In one embodiment, the embedded printed circuit board layout structure 100 further includes:

[0142] At least one conductive layer 60 is stacked with the first insulating layer 20;

[0143] The plurality of chips 10 are respectively connected to the circuit board DC terminal 30 and the circuit board AC terminal 40 through metal traces on the conductive layer 60 .

[0144] In this embodiment, the circuit board DC terminal 30 and the circuit board AC terminal 40 can be connected to the plurality of chips 10 respectively through the metal traces on the conductive layer 60. Furthermore, by opening vias and arranging metal traces in the laminated structure such as the conductive layer 60, the first insulating layer 20 and the second insulating layer 50, circuit connections between different laminates can be achieved.

[0145] Furthermore, the at least one conductive layer 60 can also be used to dissipate heat for the multiple chips 10 , thereby ensuring that the multiple chips 10 can operate normally.

[0146] In one embodiment, the circuit board DC terminal 30, the circuit board AC terminal 40 and the plurality of chips 10 are arranged on the first insulating layer 20. Conductive layers 60 are arranged on both the upper and lower surfaces of the first insulating layer 20. The circuit board DC terminal 30, the circuit board AC terminal 40 and the plurality of chips 10 are cooled by the two conductive layers 60 on the upper and lower surfaces, and the heat can be better transferred to the heat sink to achieve the heat dissipation of the printed circuit board, so as to ensure that the plurality of chips 10 can work normally.

[0147] The present application provides an electronic device, including the embedded printed circuit board layout structure 100 in any one of the above embodiments.

[0148] In this embodiment, the electronic device may be a wireless charger, a switching power supply, a motor driver, an inverter, an audio power amplifier, etc.

[0149] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned functional units, regions, and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different functional units, regions, and modules as needed. In addition, the specific names in the above-mentioned embodiments are only for the convenience of distinguishing from each other and are not used to limit the scope of protection of this application.

[0150] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, please refer to the relevant description of other embodiments. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0151] The division of modules or units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.

[0152] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An embedded printed circuit board layout structure, characterized in that: include: A plurality of chips are arranged in an array in a chip region of the first insulating layer; A circuit board DC terminal, wherein a DC projection area of ​​the first insulating layer is located in the chip area; The AC terminal of the circuit board has an AC projection area on the first insulating layer located within the chip area, and the AC projection area and the DC projection area are arranged at intervals.

2. The embedded printed circuit board layout structure according to claim 1, characterized in that: In the chip area, a plurality of chip arrays are arranged into a first concave area; The DC projection area is located between the first concave area and the chip area.

3. The embedded printed circuit board layout structure as claimed in claim 2, characterized in that: The circuit board DC terminal comprises: a first sub-DC terminal, located between the first concave area and the chip area in a first sub-DC projection area of ​​the first insulating layer; a second sub-DC terminal, located between the first concave area and the chip area in a second sub-DC projection area of ​​the first insulating layer; The second sub-DC projection area is arranged close to the first sub-DC projection area, and the second sub-DC projection area and the first sub-DC projection area are arranged side by side with an interval.

4. The embedded printed circuit board layout structure as claimed in claim 3, characterized in that: The second sub-DC projection area is arranged between two adjacent chips.

5. The embedded printed circuit board layout structure according to claim 1, characterized in that: In the chip area, a plurality of chip arrays are arranged into a first convex area; The DC projection area is located between the first convex area and the chip area.

6. The embedded printed circuit board layout structure according to claim 5, characterized in that: The circuit board DC terminal comprises: a first sub-DC terminal, located between the first convex area and the chip area in a first sub-DC projection area of ​​the first insulating layer; A first terminal, located between the first convex area and the chip area in a first projection area of ​​the first insulating layer; a second terminal located between the first convex region and the chip region in a second projection region of the first insulating layer; The first sub-DC projection area is arranged close to the first projection area and the second projection area, and the first sub-DC projection area is arranged side by side with the first projection area and the second projection area respectively.

7. The embedded printed circuit board layout structure according to claim 6, characterized in that: The first projection area and the second projection area are arranged in the same column or the same row, and at least one chip is arranged between the first projection area and the second projection area.

8. The embedded printed circuit board layout structure according to any one of claims 1 to 7, characterized in that: In the chip area, a plurality of chip arrays are arranged into a second concave area; The AC projection area is located between the second concave area and the chip area.

9. The embedded printed circuit board layout structure according to any one of claims 1 to 7, characterized in that: In the chip area, a plurality of chip arrays are arranged into a second convex area; The AC projection area is located between the second convex area and the chip area.

10. An electronic device, characterized in that: The invention comprises the embedded printed circuit board layout structure as claimed in any one of claims 1 to 9.

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