Embedded element structure and alignment method

Abstract

The invention relates to the technical field of packaging products, in particular to an embedded element structure and an alignment method, and the embedded element structure comprises an inner core plate, a first fixing layer and a second fixing layer. The first fixing layer is fixedly connected to one side of the inner-layer core plate, the second fixing layer is fixedly connected to the other side of the inner-layer core plate, a first base material point used for alignment is arranged on one side of the inner-layer core plate, and a second base material point used for alignment is arranged on the other side of the inner-layer core plate. The first base material point and the second base material point are adopted for alignment, the alignment accuracy in the element embedding process is improved, and the fault problem caused by deviation is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of packaging products, and in particular to an embedded component structure and an alignment method. Background Art

[0002] Currently, in the packaging process of embedding the chip inside the PCB board, it is necessary to align it according to the reference object so as to process the core board.

[0003] In the current process flow, a specific copper area is set as a circular pad for reference. The inner copper layer of the PCB board needs to be treated with browning to form a browning film. Although this process can enhance the visual system of the placement machine's ability to recognize the target, during transportation and operation, microscopic scratches on the browning film often cause the bottom copper to be exposed on the target surface. In addition, due to the small grayscale difference between the bottom copper and the substrate area, the placement machine cannot accurately identify the circular pad in the scratched part, affecting production efficiency, and further causing the identification to be offset, resulting in component placement deviation. In addition, there are problems such as low recognition pass rate of the circular pad in the DI machine's visual system, and serious deviation of the laser drilling on the chip caused by the inconsistency between the blind hole window exposure on the back of the chip and the chip placement target, which affects the overall quality of the product. The above problems need to be solved. Summary of the invention

[0004] In order to improve the alignment accuracy during the embedded component process and reduce the fault problems caused by misalignment, the present application provides an embedded component structure and an alignment method, which adopts the following technical solutions:

[0005] In a first aspect, the present application provides an embedded component structure, including an inner core plate, a first fixing layer, and a second fixing layer;

[0006] The first fixing layer is fixedly connected to one side of the inner core plate, and the second fixing layer is fixedly connected to the other side of the inner core plate. A first substrate point for alignment is provided on one side of the inner core plate, and a second substrate point for alignment is provided on the other side of the inner core plate.

[0007] Preferably, the inner core board comprises a first copper layer, a second copper layer and a first dielectric layer;

[0008] The first copper layer is fixedly connected to one side of the first dielectric layer, the second copper layer is fixedly connected to the other side of the first dielectric layer, the first substrate point is arranged on the first copper layer, and the second substrate point is arranged on the second copper layer.

[0009] Preferably, the first substrate point includes a first circular portion and a first window portion, and the first window portion is arranged at the center of the first circular portion.

[0010] Preferably, the second substrate point includes a second circular portion and a second window portion, and the second window portion is arranged at the center of the second circular portion.

[0011] Preferably, the diameter of the first circular portion is 3 mm, and the diameter of the first window portion is 1 mm.

[0012] Preferably, the diameter of the second circular portion is 3 mm, and the diameter of the second window portion is 2 mm.

[0013] In a second aspect, the present application provides an alignment method, comprising:

[0014] In the case where the encapsulation step is the first stage, first image information including a first substrate point is acquired, and ablation position analysis is performed according to a plurality of first substrate point positions of the first image information to obtain first execution information;

[0015] When the packaging step is the second stage, second image information including the first substrate point is obtained, and chip placement position analysis is performed according to the positions of a plurality of first substrate points in the second image information to obtain second execution information;

[0016] When the packaging step is in the third stage, third image information is acquired, and whether the third image information includes the first substrate point is identified. When the third image information includes the first substrate point, a first stop execution instruction is obtained;

[0017] When the packaging step is in the third stage, fourth image information is acquired, and it is identified whether the fourth image information includes the second substrate point. When the fourth image information includes the second substrate point, a second stop execution instruction is obtained.

[0018] Preferably, it also includes:

[0019] When the first stop execution instruction and the second stop execution instruction are obtained, the third execution information and the fourth execution information for coordinating the penetration of the inner core plate are output.

[0020] In a third aspect, the present application provides an alignment device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the alignment method as described above.

[0021] In a fourth aspect, the present application provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the alignment method as described above when run.

[0022] In summary, compared with the prior art, the technical solution provided by this application has at least the following beneficial effects:

[0023] The inner core board of the present application is provided with a first fixed layer and a second fixed layer on both sides respectively, the chip is embedded in the inner core board, the first fixed layer and the second fixed layer fix the chip, the inner core board is provided with a first substrate point and a second substrate point, the first substrate point is used for aligning one side of the inner core board and the first fixed layer during processing, the second substrate point is used for aligning the other side of the inner core board and the second fixed layer during processing, the first substrate point and the second substrate point assist in alignment at different packaging stages, improve the alignment accuracy during the embedded component process, and reduce the failure problems caused by deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a structural schematic diagram of an embedded component structure described in an embodiment of the present application.

[0025] Figure 2 It is a schematic diagram of the structure of the inner core board during laser grooving and chip mounting as described in the embodiment of the present application.

[0026] Figure 3 It is a flow chart of an alignment method described in an embodiment of the present application.

[0027] Figure 4 It is a schematic diagram of the cross-sectional structure of the funnel hole during CMF exposure described in the embodiment of the present application.

[0028] Figure 5 It is a schematic diagram of the cross-sectional structure of the CMF during exposure before the improvement described in the embodiment of the present application.

[0029] Description of reference numerals:

[0030] 1. Inner core board; 11. First copper layer; 12. Second copper layer; 13. First dielectric layer; 2. First fixed layer; 3. Second fixed layer; 100. First substrate point; 101. First circular portion; 102. First window portion; 200. Second substrate point; 201. Second circular portion; 202. Second window portion. DETAILED DESCRIPTION

[0031] The following combination Figure 1-Figure 5 The present application is described in further detail. The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to be limiting.

[0032] The embedded component alignment structure is a PCB package product with embedded chips. During the processing of this package product, there are several processing steps, some of which require precise processing after alignment. Conventional technology is to align the first circular Pad and the second circular Pad generated during the processing, that is, the copper layer round blocks on both sides of the packaged product. In this way, before the chip is attached, the first copper layer 11 and the second copper layer 12 of the inner core board 1 need to be treated with surface browning. At this time, a layer of browning film is also formed on the surface of the first circular Pad. When the first circular Pad is used as an alignment target for the component attachment process, in the visual system of the placement machine, the browned first target appears black, and the light-colored substrate area around the target appears white. When the grayscale difference between the two in the visual system of the placement machine reaches more than 30, the placement machine can smoothly identify the edge contour of the first target and accurately calculate the coordinate value of the first target. However, during the transportation and operation from browning to placement, the browning film of part of the first circular Pad will have microscopic fine scratches, revealing the bottom copper color. The grayscale difference between the bottom copper and the substrate area in the visual system of the placement machine is very small. Therefore, this part of the scratched first circular Pad cannot be clearly identified, resulting in frequent alarms from the placement machine to indicate target capture failure and interruption of production, seriously affecting production efficiency. In addition, it also causes the identification of part of the first circle Pad to be offset, that is, the coordinate value calculation error, which further causes the component patch to be offset.

[0033] And refer to Figure 5 , the first circular Pad or the second circular Pad has a low recognition pass rate in the DI machine vision system. In the DI machine, that is, the built-in program of the laser direct imaging machine, the alignment target is set to a circle with a diameter of 1.0 mm, and then the DI machine's vision system captures the edge contour of the first circular Pad and locks it as the alignment target, and calculates the coordinate value of the first circular Pad. With the first circular Pad as the alignment target, the blind hole window pattern is exposed. However, the grayscale difference between the first circular Pad and the surrounding substrate area in the DI machine's vision system is too small, and the DI machine often cannot accurately identify the edge contour of the first circular Pad. Adjusting the DI machine's target light source cannot completely improve the problem, resulting in a low target recognition pass rate, which seriously restricts the exposure production efficiency. If the target is forced to pass manually, it may also cause the blind hole window position to deviate, further causing the blind hole to deviate from the pad on the chip during laser drilling. In addition, when the back of the build-up board is exposed, the same problem of low target capture pass rate of the second circular Pad exists under the same operating conditions.

[0034] The first circular Pad and the second circular Pad are formed by exposure and etching with a DI machine. The product exposed with a DI machine will have a maximum deviation of 20μm between the upper and lower layers of the graphics, so the maximum deviation value of the first circular Pad and the second circular Pad is also 20μm. The placement machine grabs the first circular Pad as a positioning target for chip placement. The pads on the upper or lower sides of the chip have a high degree of alignment with the first circular Pad, which is consistent with the precision capability of the placement machine, that is, ±10μm, but the alignment with the second circular Pad is poor, and the accumulation of the patch precision deviation and the inter-layer graphic deviation is 22μm. Therefore, when the blind hole window is exposed, the front blind hole window is aligned with the first circular Pad, so the alignment accuracy with the top surface pad of the chip is high, while the back blind hole window is aligned with the second circular Pad, so the alignment accuracy with the back pad of the chip is poor, resulting in the probability of blind hole collapse on the back pad of the chip being much higher than that on the front of the chip.

[0035] In summary, in order to solve the problem of inaccurate alignment processing, an embedded component structure and an alignment method are provided.

[0036] Reference Figure 1 , an embedded component structure involved in the present application specifically comprises an inner core plate 1, a first fixing layer 2 and a second fixing layer 3;

[0037] The first fixing layer 2 is fixedly connected to one side of the inner core panel 1, and the second fixing layer 3 is fixedly connected to the other side of the inner core panel 1. A first substrate point 100 for alignment is provided on one side of the inner core panel 1, and a second substrate point 200 for alignment is provided on the other side of the inner core panel 1.

[0038] Specifically, the embedded component structure of the present application is a packaged product obtained in the chip packaging process. Figure 1 Specifically, it is a cross-sectional view of the alignment target position after UV window opening. The first fixed layer 2 and the second fixed layer 3 are respectively provided on both sides of the inner core board 1, and the chip is embedded in the inner core board 1. The first fixed layer 2 and the second fixed layer 3 fix the chip. The inner core board 1 is provided with a first substrate point 100 and a second substrate point 200. The first substrate point 100 is used to align one side of the inner core board 1 and the first fixed layer 2 during processing, and the second substrate point 200 is used to align the other side of the inner core board 1 and the second fixed layer 3 during processing. The first substrate point 100 and the second substrate point 200 assist in alignment at different packaging stages, improve the alignment accuracy during the embedded component process, and reduce the fault problems caused by deviation.

[0039] As one embodiment, the inner core board 1 includes a first copper layer 11, a second copper layer 12 and a first dielectric layer 13;

[0040] The first copper layer 11 is fixedly connected to one side of the first dielectric layer 13 , the second copper layer 12 is fixedly connected to the other side of the first dielectric layer 13 , the first substrate point 100 is disposed on the first copper layer 11 , and the second substrate point 200 is disposed on the second copper layer 12 .

[0041] Specifically, refer to Figure 2 , the middle of the inner core board 1 of the embodiment of the present application is the first dielectric layer 13, and the first copper layer 11 and the second copper layer 12 are fixed on both sides of the first dielectric layer 13. After the inner core board 1 is formed during the processing, the second step is to perform film pasting, exposure, development, etching, and film stripping operations on the inner core board 1, so that the first pattern is formed on the first copper layer 11, and the second pattern is formed on the second copper layer 12. The first pattern is the first substrate point 100, and the second pattern is the second substrate point 200, which is convenient for the subsequent packaging product processing alignment.

[0042] In the third step of the processing of the embodiment of the present application, the four first substrate points 100 are used as alignment targets, and the core plate layer is ablated with the front side facing upward by CO2 laser, and then the second substrate point 200 is used as an alignment target, and the core plate layer is ablated with the back side facing upward by CO2 laser. After ablation, a core plate through groove is formed for placing the embedded chip.

[0043] As one embodiment, the first substrate point 100 includes a first circular portion 101 and a first window portion 102, and the first window portion 102 is disposed at the center of the first circular portion 101. The diameter of the first circular portion 101 is 3 mm, and the diameter of the first window portion 102 is 1 mm.

[0044] Specifically, the first substrate point 100 of the embodiment of the present application is specifically an area formed by a window opened in the first copper layer 11, specifically, a first circular portion 101 is opened on the first copper layer 11, and the first circular portion 101 is a circular copper sheet with a diameter of 3 mm, that is, the circular copper sheet is surrounded by an annular window. The first circular portion 101 includes a first window portion 102 in the middle, and the first window portion 102 is also circular and located at the center of the first circular portion 101. The first window portion 102 is a circular window with a diameter of 1 mm. The first substrate point 100 is identified by identifying the first circular portion 101 and the first window portion 102, so as to align the packaging product processing.

[0045] In the embodiment of the present application, the first copper layer 11 is provided with four first substrate points 100, which are respectively arranged at different positions of the first copper layer 11 at intervals. When alignment operation is required, the four first substrate points 100 are used as alignment targets to ensure accurate alignment.

[0046] As one embodiment, the second substrate point 200 includes a second circular portion 201 and a second window portion 202, and the second window portion 202 is disposed at the center of the second circular portion 201. The diameter of the second circular portion 201 is 3 mm, and the diameter of the second window portion 202 is 2 mm.

[0047] Specifically, the second substrate point 200 of the embodiment of the present application is specifically an area formed by a window opened in the second copper layer 12, specifically, a second circular portion 201 is opened on the second copper layer 12, and the second circular portion 201 is a circular copper sheet with a diameter of 3 mm, that is, the circular copper sheet is surrounded by an annular window. The second circular portion 201 includes a second window portion 202 in the middle, and the second window portion 202 is also circular and located at the center of the second circular portion 201. The second window portion 202 is a circular window with a diameter of 2 mm. The second substrate point 200 is identified by identifying the second circular portion 201 and the second window portion 202, so as to align the packaging product processing.

[0048] In the embodiment of the present application, the second copper layer 12 is provided with four second substrate points 200, which are spaced apart at different positions of the second copper layer 12. When alignment operation is required, the four second substrate points 200 are used as alignment targets to ensure accurate alignment.

[0049] During the alignment process of the embodiment of the present application, the recognition system directly determines whether the processing surface is the first copper layer 11 or the second copper layer 12 by identifying the size of the window portion, thereby increasing the accuracy of the recognition and processing process.

[0050] The first substrate point 100 and the second substrate point 200 of the present application are set according to the needs of the processing process. If a hole or groove of the inner core board 1 is used as a target, and semi-cured sheets and copper foil are added to the upper and lower surfaces of the inner core board 1 to form a build-up board, the glue of the semi-cured sheet will melt and fill the holes and grooves, and there will be a dielectric layer and a copper foil formed after the semi-cured sheet is cured on the filled holes and grooves, causing these holes and grooves to be obscured in the subsequent processing and unable to be used for alignment identification. Therefore, compared with the ordinary setting, the present application can have a more obvious display effect, so that the alignment is more accurate.

[0051] Reference Figure 3 , an alignment method is provided for an embodiment of the present application, the system comprising:

[0052] In the case where the encapsulation step is the first stage, first image information including the first substrate point 100 is obtained, and ablation position analysis is performed according to the positions of a plurality of first substrate points 100 of the first image information to obtain first execution information;

[0053] When the packaging step is the second stage, second image information including the first substrate point 100 is obtained, and chip placement position analysis is performed according to the positions of a plurality of first substrate points 100 of the second image information to obtain second execution information;

[0054] When the packaging step is in the third stage, third image information is acquired, and it is identified whether the third image information includes the first substrate point 100. When the third image information includes the first substrate point 100, a first stop execution instruction is obtained;

[0055] When the packaging step is in the third stage, the fourth image information is acquired, and it is identified whether the fourth image information includes the second substrate point 200. When the fourth image information includes the second substrate point 200, a second stop execution instruction is obtained.

[0056] Specifically, several stages of the present application are processing steps in the chip packaging process that require obtaining the first substrate point 100 or the second substrate point 200 for alignment identification.

[0057] The first step of the chip packaging process is to prepare an inner core board 1, wherein the middle of the core board is a first dielectric layer 13, and the upper and lower parts are a first copper layer 11 and a second copper layer 12 respectively.

[0058] The second step of the chip packaging process is to laminate, expose, develop, etch, and strip the inner core board 1, form a first pattern on the first copper layer 11, and form a second pattern on the second copper layer 12. When the core board forms the first pattern and the second pattern, it includes a first substrate point 100 and a second substrate point 200 respectively.

[0059] The third step of the chip packaging process is the first stage of the packaging step. The four first substrate points 100 are used as alignment targets, and the core board layer is ablated with the front side facing up by CO2 laser. Then, the second substrate point 200 is used as an alignment target, and the core board layer is ablated with the back side facing up by CO2 laser. After ablation, a core board through groove is formed.

[0060] The fourth step of the chip packaging process is to apply a high temperature protective tape to the second copper layer 12 after the surface of the first copper layer 11 and the second copper layer 12 of the inner core board 1 are browned.

[0061] The fifth step of the chip packaging process is the second stage of the packaging step. A high-precision chip mounter is used to pick up the chip. The chip mounter then uses the four first substrate points 100 as alignment targets to find the coordinates of the position on the core board where the chip needs to be mounted, and accurately places the chip on the tape at the bottom of the core board slot to complete the chip mounting. The present application identifies the first substrate point 100 through the second image information, thereby determining the chip placement position, and outputting the second execution information for the chip mounting device to perform the corresponding action.

[0062] The sixth step of the chip packaging process is to place a prepreg and copper foil on the top surface of the core board to complete the first pressure transfer and form the third copper layer and the second dielectric layer. The prepreg glue fills the gap between the chip and the core board slot and fixes the chip.

[0063] The seventh step of the chip packaging process is to tear off the high temperature protection tape on the second pattern.

[0064] The eighth step of the chip packaging process is to place a prepreg and copper foil on the back of the core board, and perform a second press to form the fourth copper layer and the third dielectric layer. The processing of the build-up board is completed, and the chip is completely encapsulated inside the PCB board. The build-up board specifically includes the third copper layer, the second dielectric layer, the fourth copper layer, and the third dielectric layer on both sides of the inner core board 1.

[0065] Reference Figure 4 The ninth step of the chip packaging process is the third stage of the packaging step. The build-up board is UV laser windowed, and the third copper layer and the second dielectric layer on the first substrate point 100 are ablated to expose the first copper layer 11 around the first substrate point 100. The first stop execution instruction is output, and the processing equipment stops after receiving the instruction, forming the first UV window. Then the fourth copper layer and the third dielectric layer on the second substrate point 200 are ablated to expose the second copper layer 12 around the second substrate point 200, and then the second stop execution instruction is output. After receiving the instruction, the processing equipment further ablates the 200μm diameter area of ​​the second substrate point until the remaining thickness of the first dielectric layer is ≤60μm and then stops, forming the second UV window. The UV laser window is a circular window with a diameter of 3.0mm.

[0066] As one of the implementation modes, when the first stop execution instruction and the second stop execution instruction are obtained, the third execution information and the fourth execution information for cooperating with the penetration of the inner core plate 1 are output.

[0067] Specifically, the tenth step of the chip packaging process of the embodiment of the present application is to make a CO2 laser burning target for the build-up board, first facing up, and hitting the first UV window with CO2 laser light that penetrates the 30μm thickness of the interlayer; after turning over, hit the second UV window with CO2 laser light that penetrates the 30μm thickness of the interlayer. After the processing is completed, a funnel hole is formed at the position of the original first substrate point 100 and the second substrate point 200.

[0068] The eleventh step of the chip packaging process is to set the alignment target to a circle with a diameter of 1.0mm in the built-in program of the DI machine. Then the visual system of the DI machine locks it as the alignment target by capturing the edge contour of the upper part of the funnel hole and calculates the coordinate values ​​of the upper parts of the four funnel holes. Then, the blind hole window pattern exposure is performed using the upper parts of the four funnel holes as alignment targets. Because the funnel hole has been pierced, the target light source of the DI machine is adjusted to achieve a high grayscale difference between the upper part of the funnel hole, that is, the opening with a diameter of 1.0mm, and the surrounding area in the visual system of the DI machine. The DI machine can accurately identify the edge contour of the upper part of the funnel hole and improve the automatic target recognition pass rate.

[0069] The eleventh step of the chip packaging process also includes setting the alignment target to a circle with a diameter of 1.0mm in the built-in program of the DI machine, and then the visual system of the DI machine locks it as the alignment target by capturing the edge contour of the upper frame of the funnel hole. At this time, the upper frame of the funnel hole is not the lower frame with a diameter of 1.0mm, and the coordinate values ​​of the four upper frames of the funnel holes are calculated. Then, the blind hole window pattern exposure is performed using these four upper frames of the funnel holes as alignment targets. At this time, although the upper frame of the funnel hole is facing downward, the DI machine can still accurately identify the edge contour of the upper frame of the funnel hole by adjusting the target light source of the DI machine, thereby improving the automatic target recognition pass rate.

[0070] In addition, in the embodiment of the present application, since the blind hole window exposure on the front and back sides of the build-up board uses the upper panels of the four funnel holes as alignment targets, the same set of targets are used for chip mounting, which solves the problem of easy deviation of the laser holes at the bottom of the original chip and reduces the resulting product scrap rate.

[0071] The present application solves the problem that the original SMT machine uses the first circular Pad as the alignment target, and the brown film scratches on the first circular Pad cause the target to be misaligned. The SMT machine uses the first substrate point 100 as the alignment target. In the SMT machine vision system, there is a high contrast between the substrate point and the surrounding browned copper surface, and even if there are small scratches on the surrounding copper surface, it can be smoothly identified. The problem that the original DI machine uses the circular Pad as the alignment target and has a low target recognition pass rate in the DI machine vision system is solved. By adjusting the DI machine target light source parameters, the funnel hole can be clearly identified in the DI machine vision system, and the automatic target grasping pass rate is close to 100%. The problem that the blind hole window exposure on the back of the chip is inconsistent with the chip SMT target, resulting in the easy deviation of the laser hole at the bottom of the chip, reduces the resulting product scrap rate.

[0072] An embodiment of the present application provides an alignment device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the alignment method as described above.

[0073] An embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the alignment method as described above when running.

[0074] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described device and product can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0075] In several embodiments provided in this application, it should be understood that the disclosed methods, systems, devices and program products may be implemented in other ways.

[0076] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0077] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An embedded component structure, characterized in that: It includes an inner core plate, a first fixing layer and a second fixing layer; The first fixing layer is fixedly connected to one side of the inner core plate, and the second fixing layer is fixedly connected to the other side of the inner core plate. A first substrate point for alignment is provided on one side of the inner core plate, and a second substrate point for alignment is provided on the other side of the inner core plate.

2. The embedded component structure according to claim 1, characterized in that: The inner core board comprises a first copper layer, a second copper layer and a first dielectric layer; The first copper layer is fixedly connected to one side of the first dielectric layer, the second copper layer is fixedly connected to the other side of the first dielectric layer, the first substrate point is arranged on the first copper layer, and the second substrate point is arranged on the second copper layer.

3. The embedded component structure according to claim 2, characterized in that: The first substrate point includes a first circular portion and a first window portion, and the first window portion is disposed at the center of the first circular portion.

4. The embedded component structure according to claim 3, characterized in that: The second substrate point includes a second circular portion and a second window portion, and the second window portion is disposed at the center of the second circular portion.

5. The embedded component structure according to claim 3, characterized in that: The diameter of the first circular portion is 3 mm, and the diameter of the first window portion is 1 mm.

6. The embedded component structure according to claim 4, characterized in that: The diameter of the second circular portion is 3 mm, and the diameter of the second window portion is 2 mm.

7. A positioning method, characterized in that: include: In the case where the encapsulation step is the first stage, first image information including a first substrate point is acquired, and ablation position analysis is performed according to a plurality of first substrate point positions of the first image information to obtain first execution information; When the packaging step is the second stage, second image information including the first substrate point is obtained, and chip placement position analysis is performed according to the positions of a plurality of first substrate points in the second image information to obtain second execution information; When the packaging step is in the third stage, third image information is acquired, and whether the third image information includes the first substrate point is identified. When the third image information includes the first substrate point, a first stop execution instruction is obtained; When the packaging step is in the third stage, fourth image information is acquired, and it is identified whether the fourth image information includes the second substrate point. When the fourth image information includes the second substrate point, a second stop execution instruction is obtained.

8. The alignment method according to claim 7, characterized in that: Also includes: When the first stop execution instruction and the second stop execution instruction are obtained, the third execution information and the fourth execution information for coordinating the penetration of the inner core plate are output.

9. A positioning device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the alignment method according to any one of claims 7 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program is configured to execute the alignment method according to any one of claims 7 to 8 when running.

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