Anti-breakdown silicon carbide-based MOS (Metal Oxide Semiconductor) device and preparation method thereof

By adopting a multi-layered gate structure in silicon carbide-based MOS devices, and using gate oxide layers with different dielectric constants to reduce the gate electric field and tunneling current, the problems of device instability and breakdown in high-temperature and high-voltage environments are solved, and higher stability and voltage resistance are achieved.

CN119653782APending Publication Date: 2025-03-18BEIJING SMARTCHIP MICROELECTRONICS TECHNOLOGY CO LTD +1
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Patent Information

Application Number
CN202411678886.5
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-22
Publication Date
2025-03-18

AI Technical Summary

Technical Problem

In high temperature and high voltage environment, the electric field aggregation of gate dielectrics of silicon carbide-based MOS devices leads to instability and even damage to the device, especially the gates of devices such as MOS capacitors, MOSFETs and IGBTs are sensitive to reverse and forward high voltages, which easily leads to gate dielectric breakdown.

Method used

At least two stacked gate structures are used to stack the gate dielectrics. The stacked gate structure is composed of two gate oxide layers. The dielectric constant of the upper gate oxide layer is greater than that of the lower gate oxide layer, so as to increase the dielectric constant of the gate dielectric and reduce the gate oxide electric field peak and gate FN tunneling current after positive and negative gate voltage bias.

Benefits of technology

It effectively reduces the gate oxide electric field peak and gate FN tunneling current after positive and negative gate voltage bias, and improves the stability and voltage withstandability of the device.

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Abstract

The invention provides a breakdown-resistant silicon carbide-based MOS device and a preparation method thereof. The device comprises a silicon carbide epitaxial substrate; the stacked gate structures comprise a first gate oxide layer and a second gate oxide layer which are stacked, at least two stacked gate structures are stacked on the first surface of the silicon carbide epitaxial substrate, the first gate oxide layer is close to the first surface, and the second gate oxide layer is far away from the first surface; the dielectric constant of the first gate oxide 1 is smaller than that of the second gate oxide layer; wherein the at least two stacked gate structures are configured to bias and protect a gate oxide electric field at positive and negative gate voltages, and reduce gate FN tunneling leakage current.
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