Heterojunction bipolar transistor device and forming method thereof

Abstract

The invention discloses a heterojunction bipolar transistor device and a forming method thereof. The heterojunction bipolar transistor device structurally comprises a substrate; the emitter layer is located on the substrate, the base layer is located on the emitter layer, the collector layers and the base contact layers are located on the base layer and are separated from each other, and the first isolation structure is located in the emitter layer and the base layer. And the emitter conductive structure is located on the emitter layer, the emitter conductive structure comprises an emitter conductive part, the emitter conductive part and the base layer are separated from each other, and the emitter conductive structure is a multi-layer metal structure, so that the stray capacitance CBE and the stray capacitance CBC can be reduced, a photomask can be saved, and the production cost can be controlled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a heterojunction bipolar transistor device and a forming method thereof. Background Art

[0002] The RF front-end chips of wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low noise amplifiers, etc. Among them, power amplifiers include bipolar junction transistor (BJT) power amplifiers, heterojunction bipolar transistor (HBT) power amplifiers, pseudomorphic high electron mobility transistor (PHEMT) power amplifiers, etc.

[0003] With the development of wireless communication technology, more and more frequency bands are used, and more frequency bands mean more complex circuit design. However, the parasitic capacitance inside the device limits the operating frequency and bandwidth of the device.

[0004] Therefore, the existing heterojunction bipolar transistor technology needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a heterojunction bipolar transistor device and a forming method thereof, so as to improve the performance of the heterojunction bipolar transistor device.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a heterojunction bipolar transistor device, comprising: a substrate; an emitter layer located on the substrate, a base layer located on the emitter layer, a plurality of collector layers and base contact layers located on the base layer and separated from each other, and a first isolation structure located in the emitter layer and the base layer; an emitter conductive structure located on the emitter layer, the emitter conductive structure comprising an emitter conductive part, the emitter conductive part and the base layer being separated from each other, the emitter conductive structure being a multi-layer metal structure, the multi-layer metal structure comprising a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate, the first metal layer comprising titanium, the second metal layer comprising platinum, the third metal layer comprising titanium, the fourth metal layer comprising platinum, and the fifth metal layer comprising gold.

[0007] Optionally, it also includes: a collector conductive structure located on the collector layer, the collector conductive structure including a first collector conductive layer located on the surface of each collector layer; the first collector conductive layer is a multilayer metal structure, the multilayer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0008] Optionally, the collector layer includes a main collector layer and a collector transition layer located on the surface of the main collector layer, and the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer; the first collector conductive layer is located on the surface of the collector transition layer.

[0009] Optionally, the thickness of the collector transition layer is in the range of to The doping ion concentration in the collector transition layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 The thickness of the main collector layer is in the range of 1 μm to 2 μm; the doping ion concentration in the main collector layer is in the range of 1×10 15 atom / cm 3 Up to 5.0×10 18 atom / cm 3 .

[0010] Optionally, the emitter layer includes an auxiliary emitter layer and a main emitter layer located on the surface of the auxiliary emitter layer, the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer; the emitter layer has a groove, and the bottom of the groove exposes the auxiliary emitter layer; the emitter conductive part is located in the groove.

[0011] Optionally, the thickness of the auxiliary emitter layer is in the range of to The doping ion concentration in the auxiliary emitter layer is in the range of 1.0×10 19 atom / cm3 to 2.0×10 19 atom / cm3; the thickness of the main emitter layer ranges from 200nm to 2000nm; the doping ion concentration in the main emitter layer ranges from 1×10 17 atom / cm3 to 2.0×10 19 atom / cm 3 .

[0012] Optionally, the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region.

[0013] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0014] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0015] Optionally, the base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

[0016] Optionally, the first contact strip crosses the first isolation region.

[0017] Optionally, the base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

[0018] Optionally, it also includes: a base conductive structure located on the base contact layer, the base conductive structure including a first base conductive layer and a second base conductive layer located on the first base conductive layer; the first base conductive layer is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0019] Optionally, the emitter conductive portion is located on both sides of the base layer in the first direction and extends along the second direction; the emitter conductive structure also includes an emitter conductive bus, the emitter conductive bus is connected to the emitter conductive portion, and the emitter conductive bus extends along the first direction.

[0020] Optionally, the collector conductive structure also includes: a second collector conductive layer located on the first collector conductive layer, the second collector conductive layer including a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts are arranged along the first direction and extend along the second direction, the collector conductive bus extends along the first direction and is connected to the plurality of second collector conductive parts; the collector conductive bus and the base conductive structure are respectively located on two opposite sides of the emitter layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

[0021] Optionally, the collector conductive structure also includes: a second collector conductive layer located on the first collector conductive layer, the second collector conductive layer including a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts extending along the first direction and arranged along the second direction, the collector conductive bus extending along the second direction and connected to the plurality of second collector conductive parts; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction.

[0022] Correspondingly, the technical solution of the present invention also provides a method for forming a heterojunction bipolar transistor device, comprising: providing a substrate; forming an emitter material layer on the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; etching the collector material layer to form a plurality of collector layers; etching the base material layer until the emitter material layer is exposed to form a base layer; using an ion implantation process to implant ions into the emitter material layer and the base layer to form a first isolation structure in the emitter material layer and the base layer, and using the emitter material layer to form a plurality of collector layers; etching the base material layer until the emitter material layer is exposed to form a base layer; and injecting ions into the emitter material layer and the base layer to form a first isolation structure in the emitter material layer and the base layer. An emitter layer is formed; a base contact layer is formed on the surface of the base layer; an emitter conductive structure is formed on the emitter layer, the emitter conductive structure includes an emitter conductive part, the emitter conductive part and the base layer are separated from each other, the emitter conductive structure is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0023] Optionally, it also includes: forming a first collector conductive layer on each of the collector layers; the first collector conductive layer is a multilayer metal structure, and the multilayer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0024] Optionally, the collector layer includes a main collector layer and a collector transition layer located on the surface of the main collector layer, and the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer; the method also includes: forming the first collector conductive layer on the surface of each of the collector transition layers.

[0025] Optionally, the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region.

[0026] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0027] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0028] Optionally, the method for forming the base contact layer includes: forming a plurality of first contact strips, wherein the first contact strips are located in the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

[0029] Optionally, the first contact strip crosses the first isolation region.

[0030] Optionally, the method for forming the base contact layer further includes: forming a plurality of second contact strips connected to the plurality of first contact strips on the first isolation region, the second contact strips extending along the second direction, and the second contact strips being located between two adjacent collector layers in the first direction.

[0031] Optionally, it also includes: forming a first base conductive layer on the base contact layer; forming a second base conductive layer on the first base conductive layer, with the first base conductive layer and the second base conductive layer as a base conductive structure; the first base conductive layer is a multi-layer metal structure, and the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0032] Optionally, a first dielectric layer covering the emitter layer, the base layer and the collector layer is formed; the first dielectric layer is etched to form a first opening, a plurality of second openings and a third opening in the first dielectric layer, the first opening exposing a portion of the surface of the emitter layer, the second openings respectively correspond to the collector layer and expose a portion of the surface of the collector layer, and the third opening exposes a portion of the surface of the base contact layer; the emitter conductive portion is formed in the first opening, the first collector conductive layer is formed in the second opening, and the first base conductive layer is formed in the third opening.

[0033] Optionally, the emitter layer includes an auxiliary emitter layer and a main emitter layer located on the surface of the auxiliary emitter layer, and the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer; the method for forming the emitter conductive portion also includes: etching the emitter layer at the bottom of the first opening until the auxiliary emitter layer is exposed, forming a groove in the emitter layer; and forming the emitter conductive portion in the groove.

[0034] Optionally, the emitter conductive portion is formed on both sides of the base layer in the first direction and extends along the second direction; the method for forming the emitter conductive structure also includes: forming the emitter conductive bus, the emitter conductive bus extends along the first direction, and the emitter conductive bus is connected to the emitter conductive portion.

[0035] Optionally, it also includes: forming a second collector conductive layer on the first collector conductive layer, with the first collector conductive layer and the second collector conductive layer as a collector conductive structure, the second collector conductive layer including a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts are arranged along the first direction and extend along the second direction, the collector conductive bus extends along the first direction and is connected to the plurality of second collector conductive parts; the collector conductive bus and the base conductive structure are respectively located on opposite sides of the emitter layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

[0036] Optionally, it also includes: forming a second collector conductive layer on the first collector conductive layer, with the first collector conductive layer and the second collector conductive layer as the collector conductive structure, the second collector conductive layer including a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts extending along the first direction and arranged along the second direction, the collector conductive bus extending along the second direction and connected to the plurality of second collector conductive parts; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction.

[0037] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0038] In the heterojunction bipolar transistor device provided by the technical solution of the present invention, the emitter layer is placed at the bottom layer to carry the emitter conductive part and the base layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the emitter conductive structure is located on the emitter layer, and the contact layer between the emitter conductive structure and the emitter layer is eliminated, which is beneficial to saving masks and controlling production costs.

[0039] Furthermore, the collector conductive structure located on the collector layer includes the first collector conductive layer located on the surface of each collector layer, and the multilayer metal structure of the first collector conductive layer is set to reduce the contact resistance between the collector conductive structure and the collector layer. The first collector conductive layer can be formed simultaneously with the base conductive structure and the emitter conductive structure, and does not need to be formed separately by a photolithography process, which is beneficial to saving masks and controlling production costs.

[0040] Furthermore, a plurality of collector regions are arranged along the first direction, and a plurality of the collector regions are also arranged along the second direction, the first direction and the second direction are perpendicular to each other, and under the requirement of a fixed emitter layer area, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0041] Furthermore, the first contact strip crosses the first isolation region, and by increasing the size of the first isolation region along the second direction, thereby increasing the area of ​​the first isolation region, further reducing the area of ​​the PN junction formed between the emitter layer and the base layer, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0042] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0043] In the method for forming a heterojunction bipolar transistor device provided by the technical solution of the present invention, the emitter layer is placed at the bottom layer to carry the emitter conductive part and the base layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the emitter conductive structure is located on the emitter layer, and the contact layer between the emitter conductive structure and the emitter layer is eliminated, which is beneficial to saving masks and controlling production costs.

[0044] Furthermore, a first collector conductive layer is formed on the surface of each collector layer, and the collector conductive structure includes a plurality of the first collector conductive layers. The multilayer metal structure of the first collector conductive layer is arranged to reduce the contact resistance between the collector conductive structure and the collector layer. The first collector conductive layer can be formed simultaneously with the base conductive structure and the emitter conductive structure, and does not need to be formed separately by a photolithography process, which is beneficial to saving masks and controlling production costs.

[0045] Furthermore, a plurality of collector regions are arranged along the first direction, and a plurality of the collector regions are also arranged along the second direction, the first direction and the second direction are perpendicular to each other, and under the requirement of a fixed emitter layer area, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0046] Furthermore, the first contact strip crosses the first isolation region, and by increasing the size of the first isolation region along the second direction, thereby increasing the area of ​​the first isolation region, further reducing the area of ​​the PN junction formed between the emitter layer and the base layer, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0047] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figures 1 to 3 It is a schematic diagram of the structure of a heterojunction bipolar transistor device;

[0049] Figures 4 to 37 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to an embodiment of the present invention;

[0050] Figures 38 to 40 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0051] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0052] As described in the background art, the performance of heterojunction bipolar transistor devices formed by the existing technology needs to be improved. Now, a heterojunction bipolar transistor device is described and analyzed.

[0053] Figures 1 to 3 It is a structural schematic diagram of a heterojunction bipolar transistor device.

[0054] Please refer to Figures 1 to 3 , Figure 1 for Figure 2 and Figure 3 The schematic diagram of the top view of the passivation layer is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 3 for Figure 1 The cross-sectional structural schematic diagram along the EE1 direction in the figure, the heterojunction bipolar transistor device comprises: a substrate 100; a first collector portion 101, an isolation layer 102 and a prism structure on the first collector portion 101 located on the substrate 100, the prism structure comprising a second collector portion 103 and a base layer 104 located on the second collector portion 103, the collector layer comprising the first collector portion 101 and the second collector portion 103, the isolation layer 102 is located on the side wall of the first collector portion 101 and surrounds the first collector portion 101; a plurality of emitter layers 105 and a base contact layer located on the base layer 104, the plurality of emitter layers 105 are arranged parallel to the first direction X and along the second direction Y, the first The direction X is perpendicular to the second direction Y, the base contact layer includes a base bus line 106 parallel to the second direction Y and a plurality of base portions 107 parallel to the first direction X, each of the base portions 107 is located between adjacent emitter layers 105 and is electrically connected to the base bus line 106; an emitter contact layer 108 located on each of the emitter layers 105; a passivation layer 109 located on the surfaces of the emitter layer 105, the emitter contact layer 108 and the base layer 104, the passivation layer 109 having an opening (not shown in the figure), the opening exposing a portion of the surface of the base layer 104, and the base contact layer is also located in the opening; a collector contact layer 110 located on the first collector portion 101.

[0055] In the above heterojunction bipolar transistor device, there is a parasitic capacitance (ie, junction capacitance) C at the contact surface (ie, PN interface) between the collector layer and the base layer 104. BCThe prism structure formed by the second collector portion 103 of the collector layer and the base layer 104 is at the bottom layer, which is used to carry the emitter layer 105 and the base contact layer. Therefore, the area of ​​the upper surface of the prism structure is larger than the area of ​​the emitter layer 105. The area of ​​the emitter layer 105 determines the output power of the device. Under the requirement of a fixed emitter layer area, the above structure makes the contact surface between the collector layer and the base layer 104 larger, thereby making the parasitic capacitance C BC Large, affecting the device's RF performance (such as power gain).

[0056] In order to solve the above problems, the present invention provides a heterojunction bipolar transistor device and a method for forming the same, in which the emitter layer is placed at the bottom layer to carry the emitter conductive part and the base layer and other devices, so that the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the interface between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C at the PN interface between the collector layer and the base layer. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the parasitic capacitance C at the PN interface of the emitter layer and the base layer can be reduced. BE , which is beneficial to improving the radio frequency performance of the device. In addition, an emitter conductive structure is formed on a partial surface of the emitter layer, and the emitter conductive structure includes an emitter conductive part. The emitter conductive part is used to reduce the contact resistance between the emitter conductive structure and the emitter layer. The emitter conductive part can be formed simultaneously with the base conductive structure and the collector conductive structure, and does not need to be formed separately by a photolithography process, which is beneficial to saving masks and controlling production costs.

[0057] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0058] Figures 4 to 37 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to an embodiment of the present invention.

[0059] Please refer to Figures 4 to 5 , Figure 4 for Figure 5 A top view of the structure. Figure 5 yes Figure 4 A schematic cross-sectional structure diagram along the MM1 direction in FIG. 1 provides a substrate 200 .

[0060] In this embodiment, the substrate 200 includes a device region C and a second isolation region I, and the second isolation region I surrounds the device region C. The device region C is used to define the position of the emitter layer, and the second isolation region I is used to define the position of the second isolation structure.

[0061] In this embodiment, the device region C includes a base mesa region bp; the base mesa region bp includes a base lead-out region bc, a gap region g and a collector mesa region cp arranged along the second direction Y, and the base lead-out region bc and the collector mesa region cp are located on both sides of the gap region g. The base mesa region bp is used to define the position of the base layer, the collector mesa region cp is used to define the positions of several collector layers, and the base lead-out region bc is used to define the position of the base terminal.

[0062] In this embodiment, the device region C further includes two emission extraction regions ec, the two emission extraction regions ec and the base platform region cp are arranged along the first direction X, and the two emission extraction regions ec are respectively located on both sides of the base platform region cp. The emission extraction region ec is used to define the position of the emitter conductive portion.

[0063] The material of the substrate 200 includes gallium arsenide or indium phosphide. In this embodiment, the material of the substrate 200 is gallium arsenide.

[0064] Please continue to refer to Figure 4 and Figure 5 , an emitter material layer 201 is formed on the substrate 200 ; a base material layer 202 is formed on the emitter material layer 201 ; and a collector material layer 203 is formed on the base material layer 202 .

[0065] The emitter material layer 201 is used to form an emitter layer, the base material layer 202 is used to form a base layer, and the collector material layer 203 is used to form a collector layer.

[0066] In this embodiment, the emitter material layer includes an auxiliary emitter material layer (not shown in the figure) and a main emitter material layer (not shown in the figure) located on the surface of the auxiliary emitter material layer, and the doping ion concentration in the auxiliary emitter material layer is greater than the doping ion concentration in the main emitter material layer. The auxiliary emitter material layer is used to form an auxiliary emitter layer, and the auxiliary emitter layer has a higher concentration, which is used to reduce the contact resistance between the emitter layer and the emitter conductive structure.

[0067] In another embodiment, the emitter material layer may include only the main emitter material layer.

[0068] In this embodiment, the material of the auxiliary emitter material layer includes indium gallium arsenide.

[0069] In this embodiment, the thickness range of the auxiliary emitter material layer is to The doping ion concentration in the auxiliary emitter material layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19atom / cm 3 .

[0070] In this embodiment, the material of the main emitter material layer 201 includes gallium arsenide.

[0071] In this embodiment, the thickness of the main emitter material layer is in the range of 200 nm to 2000 nm; the doping ion concentration in the main emitter material layer is in the range of 1×10 17 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

[0072] In this embodiment, the material of the base material layer 202 includes gallium arsenide.

[0073] In this embodiment, the thickness of the base material layer 202 is in the range of 40 nm to 80 nm; the conductive ion doping concentration in the base material layer is in the range of 1.0×10 19 atom / cm 3 Up to 5.5×10 19 atom / cm 3 .

[0074] In this embodiment, the collector material layer includes a main collector material layer (not shown in the figure) and a collector transition material layer (not shown in the figure) located on the surface of the main collector material layer, and the doping ion concentration in the collector transition material layer is greater than the doping ion concentration in the main collector material layer.

[0075] In another embodiment, the collector layer may only include the main collector material layer.

[0076] In this embodiment, the material of the current collecting transition material layer includes indium gallium arsenide.

[0077] In this embodiment, the thickness range of the current collector transition material layer is to The doping ion concentration in the current collecting transition material layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

[0078] In this embodiment, the material of the main collector material layer includes gallium arsenide.

[0079] In this embodiment, the thickness of the main collector material layer is in the range of 1 μm to 2 μm; the doping ion concentration in the main collector material layer is in the range of 1×10 15 atom / cm3 Up to 5.0×10 18 atom / cm 3 .

[0080] In this embodiment, it is used to form an NPN type heterojunction bipolar transistor, that is, the conductivity type of the collector layer and the emitter layer is N type, and the conductivity type of the base layer is P type. In another embodiment, it can also be used to form a PNP type heterojunction bipolar transistor.

[0081] In this embodiment, a barrier material layer (not shown in the figure) is further formed on the surface of the base material layer 202, and the collector material layer 203 is formed on the surface of the barrier material layer. The material of the barrier material layer is different from that of the base material layer 202, and the conductivity type of the barrier material layer is different from that of the base material layer 202. The barrier material layer is used to protect the base layer to reduce the influence of surface defects on the performance of the base layer, and in the etching process of forming the collector, it also serves as an etching stop layer to protect the base layer.

[0082] In another embodiment, the barrier material layer may not be formed.

[0083] In this embodiment, the material of the barrier material layer includes indium gallium phosphide.

[0084] In this embodiment, the thickness of the barrier material layer is in the range of 30 nm to 50 nm; the conductive ion doping concentration in the barrier material layer is in the range of 2.0×10 17 atom / cm 3 Up to 5.0×10 17 atom / cm 3 .

[0085] Please refer to Figures 6 to 9 , Figure 6 for Figures 7 to 9 A top view of the structure. Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the MM1 direction, Figure 8 yes Figure 6 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig. 9 yes Figure 6 The cross-sectional structure schematic diagram along the FF1 direction, wherein the collector material layer 203 is etched to form a plurality of collector layers 205.

[0086] Specifically, a plurality of collector layers 205 are formed on the collector surface region cp.

[0087] In this embodiment, the collector layer 205 includes a main collector layer (not shown in the figure) and a collector transition layer (not shown in the figure) located on the surface of the main collector layer, and the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer.

[0088] Specifically, the main collector layer is formed by the main collector material layer, and the collector transition layer is formed by the collector transition material layer.

[0089] In this embodiment, the method for forming the collector layers 205 includes: forming a first mask layer (not shown) on the surface of the collector material layer 203; using the first mask layer as a mask, etching the collector material layer 203 to form the collector layers 205.

[0090] In this embodiment, the material of the first mask layer includes photoresist.

[0091] More specifically, the collector material layer 203 is etched using the first mask layer as a mask until the barrier material layer on the surface of the base material layer 202 is exposed.

[0092] Here, due to the barrier material layer on the surface of the base material layer 202, in the process of etching the collector material layer 203, a process with different etching selectivities for the base material layer 202 and the barrier material layer can be selected so that the barrier material layer acts as an etching stop layer, thereby reducing the etching damage to the base material layer 202 and improving the performance of the formed base layer.

[0093] In this embodiment, the plurality of collector layers 205 are arranged along a first direction X and extend along a second direction Y, and the first direction X and the second direction Y are perpendicular to each other. Under the requirement of a fixed emitter layer area, by providing a plurality of collector layers arranged along the first direction X, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0094] In this embodiment, the plurality of collector layers 205 are further arranged along the second direction Y. Here, by arranging the plurality of collector layers 205 along the second direction Y, the total area of ​​the collector layer is further reduced under the requirement of a fixed emitter layer area, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC A base contact layer may be provided on the surface of the base layer between adjacent collector layers 205 in the second direction Y (see the subsequent description of the first contact strip).

[0095] It should be noted that Figure 6Only a number of collector layers arranged in a 3×2 array are shown. The number and arrangement of the collector layers are not limited thereto and can be adjusted according to actual needs. For example, the arrangement of the collector layers can also be a 2×3 array.

[0096] In another embodiment, a plurality of the collector layers are arranged along the first direction and extend along the second direction, but are not arranged along the second direction. For example, the plurality of collector layers are arranged in a 3×1 array.

[0097] In yet another embodiment, a plurality of the collector layers are arranged along a first direction and extend along the first direction, but are not arranged along the second direction.

[0098] Please refer to Figures 10 to 13 , Fig.10 for Figures 11 to 13 A top view of the structure. Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.12 yes Fig.10 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.13 yes Fig.10 The cross-sectional structure schematic diagram along the FF1 direction, etching the base material layer 202 (such as Figure 6 As shown), until the emitter material layer 201 is exposed, the base layer 206 is formed, and the base layer 206 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 and a plurality of first isolation regions S2.

[0099] Specifically, the base layer 206 is formed on the base mesa region bp.

[0100] The collector region is used to define the position of the collector layer 205, and the collector layer 205 is located on the collector region; the electrical contact region S1 is used to define the position where the base contact layer is in electrical contact with the base layer; and the first isolation region S2 is used to define the position of the first isolation structure.

[0101] In this embodiment, a plurality of collector regions are arranged along the first direction X and along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0102] In this embodiment, a plurality of the electrical contact regions S1 are located between the collector regions adjacent to each other in the second direction Y, and a plurality of the first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X.

[0103] In another embodiment, a plurality of collector regions are arranged along the first direction and extend along the second direction but are not arranged along the second direction, and the electrical contact region is located at one side of the collector region in the second direction.

[0104] In this embodiment, the electrical contact regions located in the first direction X are interconnected and extend along the first direction X.

[0105] In this embodiment, a plurality of first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X and are arranged along the second direction Y at intervals.

[0106] In another embodiment, the first isolation region is adjacent to the electrical contact region.

[0107] In another embodiment, a plurality of the first isolation regions are located between the collector regions adjacent to each other in the first direction, and the first isolation regions located in the second direction are interconnected and extend along the second direction.

[0108] In this embodiment, the method for forming the base layer 206 also includes: forming a second mask layer (not shown in the figure) on the base platform area bp; using the second mask layer as a mask, etching the base material layer 202 to form the base layer 206.

[0109] In this embodiment, the barrier material layer is further etched to form a barrier layer. Specifically, before etching the base material layer 202, the barrier material layer is etched using the second mask layer as a mask to form a barrier layer.

[0110] In this embodiment, the material of the second mask layer includes photoresist.

[0111] Please refer to Figures 14 to 17 , Fig.14 for Figures 15 to 17 A top view of the structure. Fig.15 yes Fig.14 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.16 yes Fig.14 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.17 yes Fig.14 , ions are injected into the base layer 206 located in the first isolation region S2 and the emitter material layer 201 located below the first isolation region S2 by using an ion implantation process, that is, into the emitter material layer 201 (such as Fig.10 As shown in the figure, ions are implanted into the emitter material layer 201 and the base layer 206 to form the first isolation structure 207 in the emitter material layer 201 and the base layer 206, and the emitter layer 208 is formed with the emitter material layer 201.

[0112] Specifically, the emitter material layer 201 on the device region C is used to form the emitter layer 208 .

[0113] In this embodiment, a plurality of first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X and are arranged at intervals along the second direction Y; the first isolation structure 207 is formed between two collector layers 205 adjacent to each other in the first direction X, and the first isolation structures 207 are arranged at intervals along the second direction Y (e.g. Fig.14 shown).

[0114] In another embodiment, a plurality of the first isolation regions are located between the collector regions adjacent to each other in the first direction, and the first isolation regions located in the second direction are interconnected and extend along the second direction; the first isolation structure is formed between two adjacent collector layers in the first direction, and the first isolation structure extends along the second direction. By increasing the size of the first isolation region along the second direction, thereby increasing the area of ​​the first isolation region, the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0115] In this embodiment, the emitter layer 208 includes an auxiliary emitter layer (not shown in the figure) and a main emitter layer (not shown in the figure) located on the surface of the auxiliary emitter layer, and the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer.

[0116] Specifically, the main emitter layer is formed by using the main emitter material layer, and the auxiliary emitter layer is formed by using the auxiliary emitter material layer.

[0117] In this embodiment, while forming the first isolation structure 207, the ion implantation process is also used to implant the ions into the emitter material layer 201 on the second isolation region I to form a second isolation structure 209 with the emitter material layer 201 on the second isolation region I.

[0118] In this embodiment, the process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

[0119] Please refer to Figures 18 to 21 , Fig.18 for Figures 19 to 21 The top view of the second dielectric layer is omitted. Fig.19 yes Fig.18 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig. 20 yes Fig.18 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.21 yes Fig.18 A cross-sectional structural diagram along the FF1 direction is shown in FIG. 1 , in which a base contact layer is formed on the base layer 206 .

[0120] In this embodiment, the method for forming the base contact layer includes: forming a first contact strip 302 on the electrical contact region S1 , wherein the first contact strip 302 extends along the first direction X, and the first contact strip 302 connects the adjacent electrical contact regions S1 in the first direction X.

[0121] In another embodiment, the first isolation regions located in the second direction are connected to each other and extend along the second direction, and the first contact strip crosses the first isolation regions.

[0122] In this embodiment, the method for forming the base contact layer also includes: forming a plurality of second contact strips 301 connected to the plurality of first contact strips 302, the plurality of second contact strips 301 being located on the first isolation region S2 and extending along the second direction Y, and each of the second contact strips 301 being located between two adjacent collector layers 205 in the first direction X.

[0123] Here, relative to only setting a plurality of first contact strips 302, a plurality of second contact strips 301 in the base contact layer are set between the collector layers 205 adjacent to each other in the first direction X, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the setting of the plurality of second contact strips 301 and the plurality of first contact strips 302 makes the distribution of the base contact layer more uniform, which is beneficial to reducing stress and preventing device deformation.

[0124] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 300 on one side of the collector layer 205 in the second direction Y, and connecting the second contact strips 301 to the base terminal 300. Specifically, the base terminal 300 is formed on the base lead-out region bc.

[0125] In another embodiment, the base terminal may not be formed. By omitting the base terminal, the base layer does not need to provide a placement position for the base terminal, which can effectively reduce the area of ​​the base layer, further reduce the area of ​​the PN junction formed between the base layer and the emitter layer, and further reduce the parasitic capacitance C between the emitter layer and the base layer. BE, thereby improving the RF gain and cutoff frequency of the device structure and improving the performance of the device structure. Since the base layer removes the portion that is provided for the base terminal and cannot contribute to current, the utilization efficiency of the device structure can be effectively improved.

[0126] In another embodiment, the electrical contact regions located in the first direction are connected and extend along the first direction, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strips are omitted, each of the first contact strips is located between the adjacent collector layers in the second direction and extends along the first direction; the base terminal is located on one side of the plurality of collector layers in the first direction.

[0127] In another embodiment, the base contact layer comprises only the first contact strip.

[0128] In this embodiment, the base contact layer is formed after the first isolation structure 207 is formed.

[0129] In this embodiment, the first isolation structure 207 is formed between two adjacent collector layers in the first direction X; and the second contact strip 301 is located on the first isolation structure 207 .

[0130] In another embodiment, the electrical contact region is formed between two adjacent collector layers in the first direction, the isolation region is formed between two adjacent collector layers in the second direction, and the first isolation structure is formed between two adjacent collector layers in the second direction; the first contact strip is located on the first isolation structure.

[0131] In this embodiment, more specifically, the method for forming the base contact layer includes: forming a second dielectric layer 210 on the emitter layer 208, the base layer 206 and the collector layer 205, the second dielectric layer 210 having a first groove (not shown in the figure), the first groove exposing a portion of the barrier layer (not shown in the figure); forming the base contact layer in the first groove.

[0132] In another embodiment, the barrier layer may not be formed, and the first groove exposes a portion of the base layer.

[0133] The material of the second dielectric layer 210 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second dielectric layer 210 is silicon nitride.

[0134] In this embodiment, the process for forming the base contact layer includes an evaporation process.

[0135] The base contact layer includes a multi-layer metal structure, and the multi-layer metal structure includes: a sixth metal layer, a seventh metal layer, an eighth metal layer and a ninth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 200 .

[0136] In this embodiment, the material of the sixth metal layer includes platinum, the material of the seventh metal layer includes titanium, the material of the eighth metal layer includes platinum, and the material of the ninth metal layer includes copper or gold.

[0137] In this embodiment, the method for forming the base contact layer further includes: performing an annealing treatment on the base contact layer so that the base contact layer is embedded in the barrier layer and the material of the base contact layer is diffused into the base layer so that the base contact layer is in contact with the base layer. The annealing treatment is used to reduce the ohmic contact resistance between the base contact layer and the base layer 206.

[0138] Subsequently, an emitter conductive structure is formed on the emitter layer 208 , wherein the emitter conductive structure includes an emitter conductive portion, and the emitter conductive portion is separated from the base layer.

[0139] In this embodiment, a collector conductive structure is further formed on each of the collector layers 205 ; and a base conductive structure is further formed on the base contact layer.

[0140] In this embodiment, a collector conductive structure is formed on each of the collector layers 205 , including: forming a first collector conductive layer on each of the collector layers 205 .

[0141] In this embodiment, forming a base conductive structure on the base contact layer includes: forming a first base conductive layer on the base contact layer.

[0142] Specifically, the formation method of the emitter conductive structure, the first collector conductive layers, and the first base conductive layer can be referred to Figure 22 to Figure 29 .

[0143] Please refer to Figure 22 to Figure 25 , Fig. 22 for Figure 23 to Figure 25 The schematic diagram of the top view of the first dielectric layer and the second dielectric layer is omitted. Fig.23 yes Fig. 22 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.24 yes Fig. 22 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.25 yes Fig. 22The cross-sectional structure schematic diagram along the FF1 direction in the figure, forms a first dielectric layer 211 covering the emitter layer 208, the base layer 206 and the collector layer 205; etches the first dielectric layer 211 to form a first opening 221, a plurality of second openings 222 and a third opening 223 in the first dielectric layer 211, the first opening 221 exposes a portion of the surface of the emitter layer 208, the second openings 222 respectively correspond to the collector layer 205 and expose a portion of the surface of the collector layer 205, and the third opening 223 exposes a portion of the surface of the base contact layer.

[0144] Specifically, the first dielectric layer 211 is formed on the surface of the second dielectric layer 210 and the surface of the base contact layer.

[0145] Specifically, the second dielectric layer 210 is further etched so that the first opening 221 and the second opening 222 are also formed in the second dielectric layer 210 .

[0146] More specifically, the second opening 222 exposes the surface of the collector transition layer.

[0147] In this embodiment, a groove 224 is defined in the emitter layer 208 , and the auxiliary emitter layer is exposed at the bottom of the groove 224 .

[0148] In this embodiment, the method for forming the groove 224 includes: after forming the first opening 221, a plurality of the second openings 222 and the third opening 223, etching the emitter layer 208 at the bottom of the first opening 221 until the auxiliary emitter layer is exposed, and forming the groove 224 in the emitter layer 208.

[0149] In another embodiment, the emitter layer may not form the groove.

[0150] The material of the first dielectric layer 211 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first dielectric layer 211 is silicon nitride.

[0151] In this embodiment, the first openings 221 are respectively located on the two emission extraction regions ec and extend along the second direction Y.

[0152] Please refer to Figure 26 to Figure 29 , Fig.26 for Figure 27 to Figure 29 The schematic diagram of the top view of the first dielectric layer and the second dielectric layer is omitted. Fig. 27 yes Fig.26 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.28 yes Fig.26 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.29 yes Fig.26 In the cross-sectional structural diagram along the FF1 direction, the emitter conductive portion 303a is formed in the first opening 221, the first collector conductive layer 304a is formed in the second opening 222, and the first base conductive layer 305a is formed in the third opening 223.

[0153] At this point, the emitter layer 208 is placed at the bottom layer to carry the emitter conductive portion 303a and the base layer 206, so the area of ​​the emitter layer 208 is the largest. Under the requirement of a fixed emitter layer 208 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 206 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 206. BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 206, the PN junction area formed between the emitter layer 208 and the base layer 206 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer 208 and the base layer 206. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the emitter conductive structure is located on the emitter layer 208, and the contact layer between the emitter conductive structure and the emitter layer 208 is eliminated, which is beneficial to saving masks and controlling production costs.

[0154] In this embodiment, the formation process of the emitter conductive portion 303a, the first collector conductive layer 304a and the first base conductive layer 305a includes a lift-off process.

[0155] In the present embodiment, the first base conductive layer 305a, the first collector conductive layer 304a and the emitter conductive part 303a are all the multilayer metal structure, and the multilayer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0156] The multi-layer metal structure is advantageous for reducing the contact resistance between the emitter conductive structure and the emitter layer 208 .

[0157] In addition, the multilayer metal structure of the first collector conductive layer 304a is set up to reduce the contact resistance between the collector conductive structure and the collector layer 205. The first collector conductive layer 304a can be formed simultaneously with the first base conductive layer 305a and the emitter conductive part 303a, and does not need to be formed by a separate photolithography process, which is beneficial to saving masks and controlling production costs.

[0158] In this embodiment, the first collector conductive layer 304 is formed on the surface of the collector transition layer in the collector layer 205. The collector transition layer has a high doping concentration, which is conducive to reducing the contact resistance between the first collector conductive layer 304 and the collector layer 205.

[0159] In this embodiment, the method for forming the emitter conductive structure further includes: forming the emitter conductive bus 303 b, the emitter conductive bus 303 b extending along the first direction X, and the emitter conductive bus 303 b connecting with the emitter conductive portion 303 a. Specifically, the emitter conductive bus 303 b is formed on the surface of the first dielectric layer 211 adjacent to the first opening 221 .

[0160] In this embodiment, the emitter conductive bus 303 b and the base conductive structure are respectively located on two sides of the emitter layer 208 .

[0161] In this embodiment, the emitter conductive portion 303 a is formed on both sides of the base layer 206 in the first direction X, and extends along the second direction Y. That is, the emitter conductive portion 303 a is located on the emitter extraction region ec.

[0162] In this embodiment, the emitter conductive portion 303 a is also formed in the groove 224 and is in contact with the auxiliary emitter layer.

[0163] Here, the configuration of the groove 224 enables the emitter conductive portion 303a to be formed on the surface of the auxiliary emitter layer in the emitter layer 208. Since the auxiliary emitter layer has a relatively large doping concentration, it is beneficial to increase the contact resistance between the emitter conductive portion 303a and the emitter layer 208.

[0164] In another embodiment, the emitter layer may not form the groove, and the emitter conductive portion is formed in the first opening 221 and contacts the main emitter layer.

[0165] In this embodiment, a base conductive structure is formed on the base contact layer, and the method further includes: forming a second base conductive layer on the first base conductive layer, with the first base conductive layer and the second base conductive layer as the base conductive structure; forming a collector conductive structure on several of the first collector layers, and the method further includes: forming a second collector conductive layer on several of the first collector layers, with the several of the first collector conductive layers and the second collector conductive layer as the collector conductive structure.

[0166] In this embodiment, the method for forming the second base conductive layer and the second collector conductive layer can be found in Figures 30 to 37 .

[0167] Please refer to Figure 30 to Figure 33 , Fig.30 The schematic diagram of the top view of the first dielectric layer and the second dielectric layer is omitted. Fig.31 yes Fig.30 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.32 yes Fig.30 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.33 yes Fig.30 In the schematic diagram of the cross-sectional structure along the FF1 direction, a packaging material layer 225 is formed on the surface of the first dielectric layer 211, the surface of the emitter conductive structure, the surfaces of several first collector conductive layers 304a and the surface of the first base conductive layer 305a; a fourth opening 226 and several fifth openings 227 are formed in the packaging material layer 225, the fourth opening 226 exposes the top surface of the first base conductive layer 305a, and one of the fifth openings 227 exposes the top surface of one of the first collector conductive layers 304a.

[0168] The material of the packaging material layer 225 includes a polymer. In this embodiment, the material of the packaging material layer 225 is polyimide.

[0169] Please refer to Figure 34 to Figure 37 , Fig.34 The schematic diagram of the top view structure of the first dielectric layer, the second dielectric layer and the packaging material layer is omitted. Fig.35 yes Fig.34 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.36 yes Fig.34 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.37 yes Fig.34In the schematic diagram of the cross-sectional structure along the FF1 direction, the second base conductive layer 305b is formed on the surface of the packaging material layer 225 in the fourth opening 226 and adjacent to the fourth opening 226, and the second collector conductive layer is formed on the surface of the packaging material layer 225 in the plurality of the fifth openings 227 and adjacent to the plurality of the fifth openings 227.

[0170] In this embodiment, the formation process of the second base conductive layer 305 b and the second collector conductive layer includes a lift-off process.

[0171] In this embodiment, the second base conductive layer 305 b and the second collector conductive layer are formed simultaneously, and do not need to be formed separately by a photolithography process, which is beneficial to saving masks and controlling production costs.

[0172] In this embodiment, the material of the second base conductive layer 305 b and the second collector conductive layer includes metal, and the metal includes one or more of titanium, gold, platinum, silver, copper, and aluminum.

[0173] In this embodiment, the base conductive structure includes a first base conductive layer 305 a and a second base conductive layer 305 b located on the surface of the first base conductive layer 305 a .

[0174] In this embodiment, the collector conductive structure includes a plurality of first collector conductive layers 304a and a plurality of second collector conductive layers, the second collector conductive layer includes a plurality of second collector conductive portions 304b and a collector conductive bus 304c, the plurality of second collector conductive portions 304b are arranged along a first direction X and extend along a second direction Y, the collector conductive bus 304c extends along the first direction X and is connected to the plurality of second collector conductive portions 304b.

[0175] In this embodiment, the collector conductive bus 304 c and the base conductive structure are located on two opposite sides of the emitter layer 208 in the second direction Y, respectively.

[0176] In another embodiment, the base contact layer includes a plurality of first contact strips and a plurality of second contact strips, the base terminal is omitted, the base conductive structure is located on the surface of the plurality of second contact strips, and the base conductive structure is located between two adjacent collector layers in the first direction.

[0177] In another embodiment, the base contact layer includes only a plurality of first contact strips, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base conductive structure is located on the surfaces of the plurality of first contact strips, and the base conductive structure is located between two adjacent collector layers in the second direction.

[0178] In another embodiment, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strip is omitted, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base terminal is located on one side of the plurality of collector layers in the first direction, the base conductive structure is located on the surface of the base terminal, and the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction.

[0179] In this embodiment, the collector conductive bus 304c has a first projection on the surface of the substrate 200, and the emitter conductive bus 303b has a second projection on the surface of the substrate, and the first projection and the second projection do not overlap each other.

[0180] Accordingly, the embodiment of the present invention also provides a heterojunction bipolar transistor device formed by the above method, please continue to refer to Figure 34 to Figure 37 The heterojunction bipolar transistor device includes: a substrate 200; an emitter layer 208 located on the substrate 200, a base layer 206 located on the emitter layer 208, a plurality of collector layers 205 and a base contact layer located on the base layer 206 and separated from each other, and a first isolation structure 207 located in the emitter layer 208 and the base layer 206; an emitter conductive structure located on the emitter layer 208, the emitter conductive structure includes an emitter conductive portion 303a, the emitter conductive portion 303a is separated from the base layer 206, the emitter conductive structure is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 200, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0181] At this point, the emitter layer 208 is placed at the bottom layer to carry the emitter conductive portion 303a and the base layer 206, so the area of ​​the emitter layer 208 is the largest. Under the requirement of a fixed emitter layer 208 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 206 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 206.BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 206, the PN junction area formed between the emitter layer 208 and the base layer 206 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer 208 and the base layer 206. BE , which is beneficial to improving the cutoff frequency and radio frequency gain of the device. In addition, the emitter conductive structure is located on the emitter layer 208, and the contact layer between the emitter conductive structure and the emitter layer 208 is eliminated, which is beneficial to saving masks and controlling production costs.

[0182] In this embodiment, the heterojunction bipolar transistor device also includes: a collector conductive structure located on the collector layer 205, the collector conductive structure including a first collector conductive layer 304a located on the surface of each collector layer 205; the first collector conductive layer 304a is a multilayer metal structure, the multilayer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 200, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0183] The multilayer metal structure of the first collector conductive layer 304a is set up to reduce the contact resistance between the collector conductive structure and the collector layer 205. The first collector conductive layer 304a can be formed simultaneously with the base conductive structure and the emitter conductive structure, and does not need to be formed by a separate photolithography process, which is beneficial to saving masks and controlling production costs.

[0184] In this embodiment, the collector layer 205 includes a main collector layer (not shown in the figure) and a collector transition layer (not shown in the figure) located on the surface of the main collector layer, and the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer.

[0185] In this embodiment, the first collector conductive layer 304 a is located on the surface of the collector transition layer. The collector transition layer has a high doping concentration, which is beneficial to reducing the contact resistance between the first collector conductive layer 304 and the collector layer 205 .

[0186] In this embodiment, the thickness range of the collector transition layer is to The doping ion concentration in the collector transition layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

[0187] In this embodiment, the thickness of the main collector layer is in the range of 1 μm to 2 μm; the doping ion concentration in the main collector layer is in the range of 1×10 15 atom / cm 3 Up to 5.0×10 18 atom / cm 3 .

[0188] In this embodiment, the heterojunction bipolar transistor device also includes: a base conductive structure located on the base contact layer, the base conductive structure including a first base conductive layer 305a and a second base conductive layer 305b located on the first base conductive layer 305a; the first base conductive layer 305a is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

[0189] In this embodiment, the surface of the base layer 206 also has a barrier layer (not shown in the figure).

[0190] In this embodiment, the emitter layer 208, the base layer 206 and the collector layer 205 also have a second dielectric layer 210, and the second dielectric layer 210 has a first groove (not shown in the figure), and the first groove exposes part of the barrier layer; the base contact layer is located in the first groove.

[0191] In another embodiment, the surface of the base layer has no barrier layer, and the first groove exposes the base layer.

[0192] In this embodiment, the heterojunction bipolar transistor device further includes: a first dielectric layer 211 located on the emitter layer, the base layer and the collector layer, the first dielectric layer 211 being located on the surface of the second dielectric layer 210 and the base contact layer; a first opening 221, a plurality of second openings 222 and a third opening 223 located in the first dielectric layer 211, the first opening 211 exposing a portion of the surface of the emitter layer 208, one of the second openings 222 being located on one of the collector layers 205 and exposing a portion of the top surface of the collector layer 205, and the third opening 223 exposing a portion of the top surface of the base contact layer; the emitter conductive portion 303a being located in the first opening 221, the first collector conductive layer 304a being located in the second opening 222, and the first base conductive layer 305a being located in the third opening 223.

[0193] Specifically, the first opening 221 and the second opening 222 are also located in the second dielectric layer 210 .

[0194] In this embodiment, the emitter layer 208 includes an auxiliary emitter layer (not shown in the figure) and a main emitter layer (not shown in the figure) located on the surface of the auxiliary emitter layer, and the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer; the emitter layer 208 has a groove 224, and the bottom of the groove 224 exposes the auxiliary emitter layer; the emitter conductive portion 303a is also located in the groove 224 and is in contact with the auxiliary emitter layer.

[0195] Here, the arrangement of the groove 224 enables the emitter conductive portion 303a to be located on the surface of the auxiliary emitter layer in the emitter layer 208. Since the auxiliary emitter layer has a relatively large doping concentration, it is beneficial to increase the contact resistance between the emitter conductive portion 303a and the emitter layer 208.

[0196] In another embodiment, the emitter layer may not have the groove, and the emitter conductive portion is located in the first opening 221 and in contact with the main emitter layer.

[0197] In this embodiment, the thickness range of the auxiliary emitter layer is to The doping ion concentration in the auxiliary emitter layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

[0198] In this embodiment, the thickness of the main emitter layer is in the range of 200 nm to 2000 nm; the doping ion concentration in the main emitter layer is in the range of 1×10 17 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

[0199] In this embodiment, the substrate 200 includes a device region C and a second isolation region I, and the second isolation region I surrounds the device region C.

[0200] In this embodiment, the heterojunction bipolar transistor device further includes: a second isolation structure 209 located on the second isolation region I, and the second isolation structure 209 is also located on the side wall of the emitter layer 208.

[0201] In this embodiment, the device region C includes a base mesa surface region bp; the base mesa surface region bp includes a base lead-out region bc, a gap region g and a collector surface region cp arranged along the second direction Y, and the base lead-out region bc and the collector surface region cp are located on both sides of the gap region g; a plurality of collector layers 205 are located on the collector surface region cp.

[0202] In this embodiment, the base layer includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 and a plurality of first isolation regions S2, the plurality of collector regions are arranged along a first direction X, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region S2.

[0203] Specifically, the plurality of collector layers 205 are arranged along the first direction X and extend along the second direction Y.

[0204] In this embodiment, the plurality of collector regions are further arranged along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0205] Specifically, the plurality of collector layers 205 are also arranged along the second direction Y. Here, under the requirement of a fixed emitter layer area, the total area of ​​the collector layer is reduced, and the parasitic capacitance (ie, junction capacitance) C between the collector layer and the base layer is further reduced. BC .

[0206] In another embodiment, a plurality of collector regions are arranged along the first direction but not along the second direction. Specifically, a plurality of collector layers are arranged along the first direction and extend along the second direction but not along the second direction, or a plurality of collector layers are arranged along the first direction and extend along the second direction but not along the second direction. For example, a plurality of collector layers are arranged in a 3×1 array.

[0207] In this embodiment, the electrical contact region S1 is located between the collector regions adjacent to each other in the second direction Y, and the first isolation region S2 is located between the collector regions adjacent to each other in the first direction X.

[0208] In this embodiment, the base contact layer includes a plurality of first contact strips 302 . The first contact strips 302 are located on the electrical contact region and extend along the first direction X. The first contact strips 302 are located between the collector layers 205 adjacent to each other in the second direction Y.

[0209] In another embodiment, the first contact strip crosses the first isolation region. By increasing the size of the first isolation region along the second direction, thereby increasing the area of ​​the first isolation region, the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0210] In this embodiment, the base contact layer further includes: a plurality of second contact strips 301 connected to the plurality of first contact strips 302 , the plurality of second contact strips 301 are located on the first isolation region S2 and extend along the second direction Y, and each of the second contact strips 301 is located between the adjacent collector layers 205 in the first direction X.

[0211] Here, relative to setting only a plurality of first contact strips 302, a plurality of second contact strips 301 in the base contact layer are set between the collector layers 205 adjacent to each other in the second direction Y, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the setting of the plurality of second contact strips 301 and the plurality of first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0212] In this embodiment, the first isolation structure 207 is located between two adjacent collector layers 205 in the first direction X; and the second contact strip 301 is located on the first isolation structure 207 .

[0213] In this embodiment, the device region C further includes two emission extraction regions ec, the two emission extraction regions ec and the base platform region cp are arranged along the first direction X, and the two emission extraction regions ec are respectively located on both sides of the base platform region cp.

[0214] In this embodiment, the first openings 221 are respectively located on the two emitter extraction regions ec and extend along the second direction Y. That is, the emitter conductive portion 303a is located on both sides of the base layer 206 in the first direction X and extends along the second direction Y.

[0215] In this embodiment, the emitter conductive structure further includes: an emitter conductive bus 303b, the emitter conductive bus 303b is connected to the emitter conductive portion 303a, and the emitter conductive bus 303b extends along the first direction X.

[0216] In this embodiment, the emitter conductive bus 303 b and the base conductive structure are respectively located on two sides of the emitter layer 208 .

[0217] In this embodiment, the collector conductive structure also includes: a second collector conductive layer located on the first collector conductive layer, the second collector conductive layer includes a plurality of second collector conductive parts 304b and a collector conductive bus 304c, the plurality of second collector conductive parts 304b are arranged along the first direction X and extend along the second direction Y, the collector conductive bus 304c extends along the first direction X and is connected to the plurality of second collector conductive parts 304b.

[0218] In this embodiment, the base contact layer further includes a base terminal 300 , and the base terminal 300 is located on the base lead-out region bc.

[0219] In this embodiment, the base conductive structure is located on the surface of the base terminal 300 ; the collector conductive bus 304 b and the base conductive structure are located on two opposite sides of the emitter layer 208 in the second direction Y, respectively.

[0220] In another embodiment, the base contact layer includes a plurality of first contact strips and a plurality of second contact strips, the base terminal is omitted, the base conductive structure is located on the surface of the plurality of second contact strips, and the base conductive structure is located between two adjacent collector layers in the first direction.

[0221] In another embodiment, the base contact layer includes only a plurality of first contact strips, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base conductive structure is located on the surfaces of the plurality of first contact strips, and the base conductive structure is located between two adjacent collector layers in the second direction.

[0222] In another embodiment, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strip is omitted, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base terminal is located on one side of the plurality of collector layers in the first direction, the base conductive structure is located on the surface of the base terminal, and the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction.

[0223] In this embodiment, the collector conductive bus 304c has a first projection on the surface of the substrate 200, and the emitter conductive bus 303b has a second projection on the surface of the substrate, and the first projection and the second projection do not overlap each other.

[0224] Figures 38 to 40 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to another embodiment of the present invention.

[0225] This embodiment is based on the previous embodiment ( Fig. 9 ) continues to describe the method for forming a heterojunction bipolar transistor device, and the rest is the same as the previous embodiment. Fig.10 ) is mainly different in that the first isolation region and the electrical contact region are distributed differently. Detailed description will be given below in conjunction with the accompanying drawings.

[0226] Please refer to Fig.38 , etching the base material layer 202 (such as Figure 6 As shown), until the emitter material layer 201 is exposed, the base layer 406 is formed, and the base layer 406 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions n1 and a plurality of first isolation regions n2.

[0227] In this embodiment, the first isolation region n1 is adjacent to the electrical contact region n2 ; a plurality of the first isolation regions n2 are located between the adjacent collector regions in the first direction X; and the first isolation regions n2 located in the second direction Y are interconnected and extend along the second direction Y.

[0228] Here, relative to the previous embodiment, by increasing the size of the first isolation region n2 along the second direction, thereby increasing the area of ​​the first isolation region n2, the area of ​​the PN junction formed between the emitter layer and the base layer 406 is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer 406. BE , improving the cutoff frequency and RF gain of the device.

[0229] In another embodiment, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the electrical contact regions located in the first direction are interconnected and extend along the first direction; a plurality of the first isolation regions are located between the collector regions adjacent to each other in the first direction and are arranged along the second direction; and the first isolation region is adjacent to the electrical contact region.

[0230] Please refer to Fig.39 , using an ion implantation process, ions are implanted into the base layer 206 located in the first isolation region S2 and the emitter material layer 201 located below the first isolation region S2, that is, into the emitter material layer 201 (such as Fig.38 As shown in the figure, ions are implanted into the emitter material layer 201 and the base layer 406 to form the first isolation structure 407 in the emitter material layer 201 and the base layer 406, and the emitter layer 408 is formed with the emitter material layer 201.

[0231] In this embodiment, while forming the first isolation structure 407, the ion implantation process is also used to implant the ions into the emitter material layer 201 on the second isolation region I to form a second isolation structure 409 with the emitter material layer 201 on the second isolation region I.

[0232] Please refer to Fig.40 , a base contact layer is formed on the base layer 206 .

[0233] In this embodiment, the method for forming the base contact layer includes: forming a first contact strip 602 on the electrical contact region n1 , wherein the first contact strip 602 extends along the first direction X, and the first contact strip 602 connects the adjacent electrical contact regions n1 in the first direction X.

[0234] In this embodiment, the first contact strip 602 crosses the first isolation region n2.

[0235] In this embodiment, the method for forming the base contact layer further includes: forming a plurality of second contact strips 601 connected to the first contact strips 602, wherein the second contact strips 601 are located on the first isolation region n2 and extend along the second direction Y, and the second contact strips 601 are located between two adjacent collector layers 205 in the first direction X.

[0236] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 600 on one side of the collector layer 205 in the second direction Y, and connecting the second contact strips 601 to the base terminal 600. Specifically, the base terminal 600 is formed on the base lead-out region bc.

[0237] Subsequently, the method for forming the heterojunction bipolar transistor device may refer to the method described in the previous embodiment. Figures 22 to 37 And related narratives will not be repeated here.

[0238] Accordingly, the embodiment of the present invention also provides a heterojunction bipolar transistor device formed by the above method, please continue to refer to Fig.40 , I will not go into details here.

[0239] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A heterojunction bipolar transistor device, characterized in that: include: substrate; An emitter layer located on the substrate, a base layer located on the emitter layer, a plurality of collector layers and base contact layers located on the base layer and separated from each other, and a first isolation structure located in the emitter layer and the base layer; An emitter conductive structure located on the emitter layer, the emitter conductive structure including an emitter conductive part, the emitter conductive part and the base layer are separated from each other, the emitter conductive structure is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

2. The heterojunction bipolar transistor device according to claim 1, characterized in that: It also includes: a collector conductive structure located on the collector layer, the collector conductive structure includes a first collector conductive layer located on the surface of each collector layer; the first collector conductive layer is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

3. The heterojunction bipolar transistor device according to claim 2, characterized in that: The collector layer includes a main collector layer and a collector transition layer located on the surface of the main collector layer, wherein the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer; and the first collector conductive layer is located on the surface of the collector transition layer.

4. The heterojunction bipolar transistor device according to claim 3, characterized in that: The thickness range of the collector transition layer is to The doping ion concentration in the collector transition layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 The thickness of the main collector layer is in the range of 1 μm to 2 μm; the doping ion concentration in the main collector layer is in the range of 1×10 15 atom / cm 3 Up to 5.0×10 18 atom / cm 3 .

5. The heterojunction bipolar transistor device according to claim 1, characterized in that: The emitter layer comprises an auxiliary emitter layer and a main emitter layer located on the surface of the auxiliary emitter layer, the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer; the emitter layer has a groove, and the bottom of the groove exposes the auxiliary emitter layer; The emitter conductive portion is located in the groove.

6. The heterojunction bipolar transistor device according to claim 5, characterized in that: The thickness of the auxiliary emitter layer is in the range of to The doping ion concentration in the auxiliary emitter layer is in the range of 1.0×10 19 atom / cm 3 Up to 2.0×10 19 atom / cm 3 The thickness of the main emitter layer is in the range of 200 nm to 2000 nm; the doping ion concentration in the main emitter layer is in the range of 1×10 17 atom / cm 3 Up to 2.0×10 19 atom / cm 3 .

7. The heterojunction bipolar transistor device according to claim 2, characterized in that: The base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, wherein the plurality of collector regions are arranged along a first direction, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region.

8. The heterojunction bipolar transistor device according to claim 7, characterized in that: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

9. The heterojunction bipolar transistor device according to claim 8, characterized in that: The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

10. The heterojunction bipolar transistor device according to claim 9, characterized in that: The base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

11. The heterojunction bipolar transistor device according to claim 10, characterized in that: The first contact strip crosses the first isolation region.

12. The heterojunction bipolar transistor device according to claim 10, characterized in that: The base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

13. The heterojunction bipolar transistor device according to claim 8, characterized in that: Also includes: A base conductive structure located on the base contact layer, the base conductive structure comprising a first base conductive layer and a second base conductive layer located on the first base conductive layer; the first base conductive layer is a multi-layer metal structure, the multi-layer metal structure comprising a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer comprising titanium, the second metal layer comprising platinum, the third metal layer comprising titanium, the fourth metal layer comprising platinum, and the fifth metal layer comprising gold.

14. The heterojunction bipolar transistor device according to claim 13, characterized in that: The emitter conductive part is located on both sides of the base layer in the first direction and extends along the second direction; the emitter conductive structure also includes an emitter conductive bus, the emitter conductive bus is connected to the emitter conductive part, and the emitter conductive bus extends along the first direction.

15. The heterojunction bipolar transistor device according to claim 13, characterized in that: The collector conductive structure also includes: a second collector conductive layer located on the first collector conductive layer, the second collector conductive layer includes a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts are arranged along the first direction and extend along the second direction, the collector conductive bus extends along the first direction and is connected to the plurality of second collector conductive parts; the collector conductive bus and the base conductive structure are respectively located on opposite sides of the emitter layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

16. The heterojunction bipolar transistor device according to claim 13, characterized in that: The collector conductive structure further includes: a second collector conductive layer located on the first collector conductive layer, the second collector conductive layer including a plurality of second collector conductive portions and a collector conductive bus, the plurality of second collector conductive portions extending along the first direction and arranged along the second direction, the collector conductive bus extending along the second direction and connected to the plurality of second collector conductive portions; The base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are respectively located on two opposite sides of the emitter layer in the first direction.

17. A method for forming a heterojunction bipolar transistor device, characterized in that: include: providing a substrate; forming an emitter material layer on the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; Etching the collector material layer to form a plurality of collector layers; Etching the base material layer until the emitter material layer is exposed to form a base layer; Using an ion implantation process, ions are implanted into the emitter material layer and the base layer to form a first isolation structure in the emitter material layer and the base layer, and an emitter layer is formed by using the emitter material layer; forming a base contact layer on the surface of the base layer; An emitter conductive structure is formed on the emitter layer, the emitter conductive structure includes an emitter conductive part, the emitter conductive part is separated from the base layer, the emitter conductive structure is a multi-layer metal structure, the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

18. The method for forming a heterojunction bipolar transistor device according to claim 17, wherein: Also includes: forming a first collector conductive layer on each of the collector layers; The first collector conductive layer is a multilayer metal structure, which includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

19. The method for forming a heterojunction bipolar transistor device according to claim 18, characterized in that: The collector layer includes a main collector layer and a collector transition layer located on the surface of the main collector layer, and the doping ion concentration in the collector transition layer is greater than the doping ion concentration in the main collector layer; the method also includes: forming the first collector conductive layer on the surface of each collector transition layer.

20. The method for forming a heterojunction bipolar transistor device according to claim 18, wherein: The base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, wherein the plurality of collector regions are arranged along a first direction, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region.

21. The method for forming a heterojunction bipolar transistor device according to claim 20, wherein: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

22. The method for forming a heterojunction bipolar transistor device according to claim 21, characterized in that: The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

23. The method for forming a heterojunction bipolar transistor device according to claim 22, characterized in that: The method for forming the base contact layer includes: forming a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

24. The method for forming a heterojunction bipolar transistor device according to claim 23, characterized in that: The first contact strip crosses the first isolation region.

25. The method for forming a heterojunction bipolar transistor device according to claim 23, characterized in that: The method for forming the base contact layer further includes: forming a plurality of second contact strips connected to the plurality of first contact strips on the first isolation region, wherein the second contact strips extend along the second direction and are located between two adjacent collector layers in the first direction.

26. The method for forming a heterojunction bipolar transistor device according to claim 21, characterized in that: Also includes: A first base conductive layer is formed on the base contact layer; a second base conductive layer is formed on the first base conductive layer, and the first base conductive layer and the second base conductive layer are used as a base conductive structure; the first base conductive layer is a multi-layer metal structure, and the multi-layer metal structure includes a first metal layer, a second metal layer, a third metal layer, a fourth metal layer and a fifth metal layer stacked in sequence in a direction perpendicular to the substrate surface, the first metal layer includes titanium, the second metal layer includes platinum, the third metal layer includes titanium, the fourth metal layer includes platinum, and the fifth metal layer includes gold.

27. The method for forming a heterojunction bipolar transistor device according to claim 26, wherein: forming a first dielectric layer covering the emitter layer, the base layer and the collector layer; The first dielectric layer is etched to form a first opening, a plurality of second openings and a third opening in the first dielectric layer, wherein the first opening exposes a portion of the surface of the emitter layer, the second openings correspond to the collector layer respectively and expose a portion of the surface of the collector layer, and the third opening exposes a portion of the surface of the base contact layer; the emitter conductive portion is formed in the first opening, the first collector conductive layer is formed in the second opening, and the first base conductive layer is formed in the third opening.

28. The method for forming a heterojunction bipolar transistor device according to claim 27, characterized in that: The emitter layer includes an auxiliary emitter layer and a main emitter layer located on the surface of the auxiliary emitter layer, and the doping ion concentration in the auxiliary emitter layer is greater than the doping ion concentration in the main emitter layer; The method for forming the emitter conductive portion further includes: etching the emitter layer at the bottom of the first opening until the auxiliary emitter layer is exposed, and forming a groove in the emitter layer; The emitter conductive portion is formed in the groove.

29. The method for forming a heterojunction bipolar transistor device according to claim 26, wherein: The emitter conductive portion is formed on both sides of the base layer in the first direction and extends along the second direction; the method for forming the emitter conductive structure also includes: forming the emitter conductive bus, the emitter conductive bus extends along the first direction, and the emitter conductive bus is connected to the emitter conductive portion.

30. The method for forming a heterojunction bipolar transistor device according to claim 26, wherein: Also includes: A second collector conductive layer is formed on the first collector conductive layer, with the first collector conductive layer and the second collector conductive layer as a collector conductive structure, the second collector conductive layer includes a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts are arranged along the first direction and extend along the second direction, the collector conductive bus extends along the first direction and is connected to the plurality of second collector conductive parts; the collector conductive bus and the base conductive structure are respectively located on opposite sides of the emitter layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

31. The method for forming a heterojunction bipolar transistor device according to claim 26, wherein: Also includes: A second collector conductive layer is formed on the first collector conductive layer, with the first collector conductive layer and the second collector conductive layer as a collector conductive structure, the second collector conductive layer includes a plurality of second collector conductive parts and a collector conductive bus, the plurality of second collector conductive parts extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction and is connected to the plurality of second collector conductive parts; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are respectively located on opposite sides of the emitter layer in the first direction.

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