Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a pair of gate electrodes, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is arranged on the first electrode. The pair of gate electrodes are respectively arranged on the first semiconductor region through the gate insulating layer. The distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region is 150 nm or more and 450 nm or less. The second semiconductor region is provided between the pair of gate electrodes. The third semiconductor region is arranged on the second semiconductor region. The second electrodes are respectively arranged on the pair of gate electrodes through the insulating layers. The second electrode includes a contact portion in contact with a portion of the second semiconductor region and the third semiconductor region in the second direction. The length of the bottom portion of the contact portion in the second direction is greater than 28 nm and no greater than 206 nm.

Description

[0001] Related Applications

[0002] This application claims the priority of Japanese Patent Application No. 2023-149462 (filing date: September 14, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device. Background Art

[0004] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) are used for applications such as power conversion, etc. Semiconductor devices are expected to have low on-resistance. Summary of the invention

[0005] A semiconductor device of an embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a pair of gate electrodes, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, and a second electrode. The first semiconductor region is provided on the first electrode. The pair of gate electrodes are provided on the first semiconductor region via a gate insulating layer, respectively. The distance between the gate insulating layers in a second direction perpendicular to the first direction from the first electrode toward the first semiconductor region is greater than 150 nm and less than 450 nm. The second semiconductor region is provided between the pair of gate electrodes. The third semiconductor region is provided on the second semiconductor region. The second electrodes are provided on the pair of gate electrodes via an insulating layer, respectively. The second electrode includes a contact portion that is in contact with a portion of the second semiconductor region and the third semiconductor region in the second direction. The length of the bottom of the contact portion in the second direction is greater than 28 nm and less than 206 nm.

[0006] According to this embodiment, a semiconductor device capable of reducing on-resistance can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a perspective cross-sectional view showing a part of the semiconductor device according to the embodiment.

[0008] Figure 2 Yes Figure 1 An enlarged cross-sectional view of a portion of the

[0009] Figure 3 Yes Figure 1 An enlarged cross-sectional view of a portion of the

[0010] Figure 4 It is a simulation result showing the characteristics of the semiconductor device.

[0011] Figure 5 It is a simulation result showing the characteristics of the semiconductor device.

[0012] Figure 6 It is a simulation result showing the characteristics of the semiconductor device.

[0013] Figure 7 It is a simulation result showing the characteristics of the semiconductor device.

[0014] Figure 8 It is a simulation result showing the characteristics of the semiconductor device.

[0015] Fig. 9 (a) and Fig. 9 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0016] Fig.10 (a) and Fig.10 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0017] Fig.11 (a) and Fig.11 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0018] Fig.12 (a) and Fig.12 (b) is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0019] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0020] Description of Reference Numerals

[0021] 1:n - Type drift area; 1x:n - Type semiconductor layer; 2: p-type base region; 2x: p-type semiconductor region; 3: n + Type source region; 3a: first part; 3b: second part; 3x: n + Type semiconductor region; 4: p + Type contact area; 5: n + Type drain region; 5x:n +type semiconductor layer; 10: gate electrode; 11: gate insulating layer; 11x: insulating layer; 12: insulating layer; 12x, 13x: insulating layer; 13y: mask; 21: drain electrode; 21x, 21y: metal layer; 22: source electrode; 22a, 22b: contact portion; 22x~22z: metal layer; 100: semiconductor device; D, D1~D3: distance; J1: first junction; J2: second junction; LS: bottom surface; OP1, OP2: opening; P: spacing; US: upper surface; US1: first region; US2: second region; W, W1~W4: width. DETAILED DESCRIPTION

[0022] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings. The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. In addition, even when representing the same part, there is a case where the dimensions and ratios of each other are represented differently according to the accompanying drawings. In the specification and each figure of the present application, the same reference numerals are marked for the same elements as those already described, and the detailed description is appropriately omitted.

[0023] In the following description, n + 、n - 、p + These symbols, n, and p, indicate the relative high and low impurity concentrations in each conductivity type. + Indicates that n - Compared with n-type, the impurity concentration is relatively high. + It means that the p-type impurity concentration is relatively higher than that of the p-type. In each embodiment described below, the p-type and n-type of each semiconductor region may be reversed to implement each embodiment.

[0024] Figure 1 This is a perspective cross-sectional view showing a part of the semiconductor device according to the embodiment.

[0025] The semiconductor device 100 of the embodiment is a MOSFET. Figure 1 As shown, the semiconductor device 100 includes n - type (first conductivity type) drift region 1 (first semiconductor region), p type (second conductivity type) base region 2 (second semiconductor region), n + Type source region 3 (third semiconductor region), p + Type contact region 4 (fourth semiconductor region), n + The type drain region 5, the gate electrode 10, the gate insulating layer 11, the insulating layer 12, the drain electrode 21 (first electrode) and the source electrode 22 (second electrode). Figure 1 , the source electrode 22 is shown by a dotted line.

[0026] In the description of the embodiment, an XYZ orthogonal coordinate system is used. - The direction of the drift region 1 is defined as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are defined as the X direction (second direction) and the Y direction (third direction). - The direction of the type drift region 1 is called "up", and the opposite direction is called "down". These directions are based on the drain electrode 21 and the n - The relative position relationship of the drift area 1 has nothing to do with the direction of gravity.

[0027] A drain electrode 21 is provided on the lower surface of the semiconductor device 100. + The type drain region 5 is provided on the drain electrode 21 and is electrically connected to the drain electrode 21. - The drift region 1 is located at n + The type drain region 5 is above. - Type drift region 1 via n + The type drain region 5 is electrically connected to the drain electrode 21. - The n-type impurity concentration in the drift region 1 is n + The n-type drain region 5 has a low n-type impurity concentration.

[0028] The gate electrode 10 is provided on the n - A plurality of gate electrodes 10 are provided in the X direction, and these gate electrodes 10 are separated from each other. A p-type base region 2 is provided between adjacent gate electrodes 10. The p-type base region 2 is located at the n - Type drift region 1. + The p-type source region 3 is provided on the p-type base region 2. The gate electrode 10 is sandwiched between the gate insulating layer 11 and the n-type base region 2 in the X direction. - A portion of the p-type drift region 1, the p-type base region 2, and the n-type + Relative to a portion of the type source region 3.

[0029] The source electrode 22 is provided on the plurality of gate electrodes 10 through the insulating layer 12. The source electrode 22 is located on the upper surface of the semiconductor device 100 and is connected to the p-type base region 2 and the n-type base region 2. + The source electrode 22 includes a contact portion 22a. The contact portion 22a extends downward and contacts a portion of the p-type base region 2 and the n-type base region 3 in the X direction. + Type source region 3 is in contact. + The p-type contact region 4 is provided between the p-type base region 2 and the contact portion 22a. +The p-type impurity concentration of the p-type contact region 4 is higher than the p-type impurity concentration of the p-type base region 2 .

[0030] p-type base region 2, n + Type source region 3, p + The type contact region 4, the gate electrode 10, and the contact portion 22a extend in the Y direction and are provided in a stripe shape.

[0031] The operation of the semiconductor device 100 is described. In a state where a positive voltage is applied to the drain electrode 21 relative to the source electrode 22, a voltage above the threshold is applied to the gate electrode 10. As a result, a channel (inversion layer) is formed in the p-type base region 2. Electrons flow from the source electrode 22 to the n-type base region 2 through the channel. - The semiconductor device 100 is turned on by the p-type drift region 1. Thereafter, when the voltage applied to the gate electrode 10 is lower than the threshold, the channel in the p-type base region 2 disappears, and the semiconductor device 100 is turned off.

[0032] An example of the material of each component is described. - Type drift region 1, p-type base region 2, n + Type source region 3, p + Type contact area 4 and n + The type drain region 5 includes silicon, silicon carbide, gallium nitride or gallium arsenide as a semiconductor material. When silicon is used as a semiconductor material, arsenic, phosphorus or antimony can be used as an n-type impurity. Boron can be used as a p-type impurity. The gate electrode 10 includes a conductive material such as polysilicon. The gate insulating layer 11 and the insulating layer 12 include insulating materials such as silicon oxide. The drain electrode 21 and the source electrode 22 include metals such as titanium, gold, and aluminum. As long as the drain electrode 21 and the source electrode 22 can be in ohmic contact with the semiconductor region, the specific materials and compositions of the drain electrode 21 and the source electrode 22 can be appropriately changed.

[0033] The preferred range of the impurity concentration of each semiconductor region is as follows. - The n-type impurity concentration in the drift region 1 is 1.0×10 16 atom / cm 3 Above and 1.0×10 18 atom / cm 3 The n-type impurity concentration in the p-type base region 2 is 1.0×10 17 atom / cm 3 Above and 1.0×10 19 atom / cm 3 Below. + The n-type impurity concentration in the source region 3 is 5.0×10 18 atom / cm3 Above and 5.0×10 20 atom / cm 3 Below. + The n-type impurity concentration in the contact region 4 is 5.0×10 18 atom / cm 3 Above and 5.0×10 20 atom / cm 3 Below. + The n-type impurity concentration in the drain region 5 is 1.0×10 19 atom / cm 3 Above and 1.0×10 21 atom / cm 3 the following.

[0034] Figure 2 as well as Figure 3 Yes Figure 1 An enlarged cross-sectional view of a portion of the

[0035] Figure 2 as well as Figure 3 is a cross-sectional view showing an enlarged portion of the semiconductor device 100. Figure 2 as well as Figure 3 The detailed structure and specific dimensions of each element of the semiconductor device 100 will be described.

[0036] The p-type base region 2 and the gate electrode 10 are alternately arranged in the X direction. The distance D between a pair of gate insulating layers 11 adjacent in the X direction is preferably greater than 150 nm and less than 450 nm. The width W of the gate electrode 10 is preferably greater than 160 nm and less than 240 nm. For example, the thickness of the gate insulating layer 11 is 20 nm. The thickness of the gate insulating layer 11 is preferably greater than 10 nm and less than 30 nm. The sum of the distance D, the width W, and twice the thickness of the gate insulating layer 11 is also referred to as the pitch of the gate electrodes 10. The pitch of the gate electrodes 10 is preferably greater than 450 nm and less than 650 nm.

[0037] The width W1 of the contact portion 22a is wider than 28nm and is less than 206nm. "Width" refers to the length in the X direction. The length L1 of the contact portion 22a in the Z direction is preferably greater than 250nm and less than 450nm. The side surface of the contact portion 22a may also be inclined relative to the Z direction. The inclination of the side surface of the contact portion 22a relative to the Z direction is preferably greater than 0 degrees and less than 5 degrees.

[0038] When the side surface of the contact portion 22a is inclined, the width W1 is equivalent to the width of the lower end of the contact portion 22a. In this case, the width W2 of the upper end of the contact portion 22a is preferably wider than 50nm and less than 270nm. More specifically, the contact portion 22a refers to a portion of the source electrode 22 that is located between the gate insulating layers 11 and between the insulating layers 12 in the X direction and has a substantially constant width in the Y direction. The upper end of the contact portion 22a refers to the end portion on the upper side of the portion with a constant width. When the side surface of the contact portion 22a is not inclined, the width W2 is equal to the width W1.

[0039] In addition, when the side surface of the contact portion 22a is inclined, the width W and the distance D refer to the dimension in the X direction at the depth of the bottom of the contact portion 22a. Specifically, first, in the Z direction, the position (depth) of the bottom of the contact portion 22a is determined. Next, at the depth of the bottom of the contact portion 22a, the end of the gate electrode 10 in the X direction, the interface between the p-type base region 2 and the gate insulating layer 11, etc. are determined. Based on the above-mentioned end, interface, etc., the distance D and the width W are measured.

[0040] For example, Figure 3 As shown, the source electrode 22 includes a contact portion 22b in addition to the contact portion 22a. The contact portion 22b is provided on the contact portion 22a and is located between the insulating layers 12 in the X direction. The width of the contact portion 22b is wider than the width of the contact portion 22a. For example, the width of the contact portion 22a changes in a step-like manner toward the width of the contact portion 22b.

[0041] like Figure 2 As shown, n + The upper surface US of the source region 3 may also include a first region US1 and a second region US2. The inclination of the first region US1 relative to the X direction is greater than 0 degrees and less than 15 degrees. The inclination of the second region US2 relative to the X direction is greater than 30 degrees and less than 90 degrees. The position of the first region US1 in the X direction is between the position of the second region US2 in the X direction and the position of the contact portion 22a in the X direction. The width W3 of the first region US1 is greater than 87nm. The width W4 of the second region US2 is greater than 5nm and less than 20nm. The upper limit of the width W3 is not particularly limited and is appropriately designed according to the width W1 of the contact portion 22a, the pitch P of the gate electrode 10, etc.

[0042] like Figure 3 As shown, in the semiconductor device 100, n + The type source region 3 may also include a first portion 3a and a second portion 3b. The first portion 3a has Figure 2The second portion 3b is located between the first region US1 and the insulating layer 12 in the X direction. For example, the n-type impurity concentration of the second portion 3b is lower than that of the first portion 3a. Therefore, the resistivity of the second portion 3b is higher than that of the first portion 3a.

[0043] like Figure 2 As shown, in n - A first junction J1 is formed between the p-type drift region 1 and the p-type base region 2. + A second junction J2 is formed between the first and second source regions 3. The bottom surface LS of the contact portion 22a is located above the first junction J1 and below the second junction J2. The distance D1 (first distance) from the first junction J1 to the bottom surface LS in the Z direction is at least 0.5 times the distance D2 (second distance) from the first junction J1 to the second junction J2 in the Z direction. That is, the bottom surface LS is located above the center between the first junction J1 and the second junction J2.

[0044] Figures 4 to 8 It is a simulation result showing the characteristics of the semiconductor device.

[0045] Figure 4 It is a simulation result which shows the relationship between the pitch P and the on-resistance Ron. Figure 5 2 is a simulation result showing the relationship between the pitch P and the threshold voltage Vth. Figure 6 This is the simulation result showing the relationship between the spacing P and the withstand voltage Vdss. Figures 4 to 6 In the figure, the values ​​of the on-resistance Ron, the threshold voltage Vth, and the withstand voltage Vdss are expressed in relative comparison. The threshold voltage Vth is the voltage applied to the gate electrode 10 required to turn on the semiconductor device 100. The withstand voltage Vdss means the maximum voltage that can be applied between the drain electrode 21 and the source electrode 22 when the gate electrode 10 and the source electrode 22 are short-circuited. In the simulation, the width W is set to 160nm. The length L1 is set to 390nm. The width W1 is set to 70nm.

[0046] according to Figure 4 The simulation results show that the wider the pitch P, the greater the on-resistance Ron. This is because the wider the pitch P, the smaller the number of gate electrodes 10 per unit area. The fewer the number of gate electrodes 10 per unit area, the smaller the area of ​​the channel per unit area. In other words, the channel density decreases. If the channel density decreases, the on-resistance Ron increases. On the other hand, according to Figure 4 The simulation results show that when the pitch P is too narrow, the on-resistance Ron also increases. When the pitch P is narrow, p-type impurities are easily introduced from p to p during the manufacturing process of the semiconductor device 100. +The p-type contact region 4 diffuses toward the interface between the p-type base region 2 and the gate insulating layer 11. The higher the p-type impurity concentration at the interface, the greater the resistance to electrons, and the greater the on-resistance Ron. When the spacing P is less than 400nm, the diffusion of p-type impurities has a greater effect on the increase in the on-resistance Ron, and the on-resistance Ron increases. However, since the increase is slight, from the perspective of the on-resistance Ron, the spacing P can be less than 650nm.

[0047] according to Figure 5 It can be seen from the simulation results that the narrower the pitch P, the higher the threshold voltage Vth. Specifically, when the pitch P is less than 400nm, the threshold voltage Vth increases significantly. This is because, when the pitch P is narrow, as described above, the p-type impurity concentration at the interface between the p-type base region 2 and the gate insulating layer 11 increases. Therefore, from the perspective of the threshold voltage Vth, the pitch P is preferably greater than 450nm.

[0048] according to Figure 6 The simulation results show that when the pitch P is narrow or wide, the withstand voltage Vdss decreases. The wider the pitch P, the greater the gap between the gate electrodes 10 when viewed from the Z direction. + When the pitch P is too wide, holes are not efficiently discharged when breakdown occurs in the semiconductor device 100, and the withstand voltage Vdss is reduced. On the other hand, when the pitch P is too narrow, the p + Due to the influence of the p-type contact region 4, the p-type impurity concentration of the p-type base region 2 increases. As a result, in the p-type base region 2, the depletion layer is difficult to extend in the X direction, and the withstand voltage Vdss is reduced. Therefore, from the viewpoint of the withstand voltage Vdss, the pitch P is preferably greater than or equal to 450nm and less than or equal to 650nm.

[0049] according to Figures 4 to 6 According to the simulation results, the pitch P is preferably greater than 450nm and less than 650nm.

[0050] Figure 7 is a simulation result showing the relationship between the width W1 of the contact portion 22a and the on-resistance Ron. Figure 7 In the simulation, the value of the on-resistance Ron is expressed as a relative ratio. In the simulation, the width W is set to 160nm. The length L1 is set to 390nm. The spacing P is set to 600nm. Figure 7The results shown show that when the width W1 is less than 160nm, the on-resistance Ron is approximately constant. If the width W1 exceeds 160nm, the on-resistance Ron gradually increases. This is believed to be because, as the width W1 becomes wider, the p-type impurities are more likely to diffuse near the interface between the p-type base region 2 and the gate insulating layer 11. If the width W1 exceeds 206nm and reaches 230nm, the on-resistance Ron increases by more than 10% compared to the case where the width W1 is less than 100nm. Therefore, the width W1 is preferably less than 206nm. In order to further suppress the increase in the on-resistance Ron, the width W1 is more preferably less than 160nm.

[0051] In addition, the width W1 is preferably greater than 28 nm. When the width W1 is less than 28 nm, although the reason is unclear, it is confirmed that impact ionization occurs near the lower end of the gate insulating layer 11. If impact ionization occurs near the lower end of the gate insulating layer 11, the gate insulating layer 11 may be damaged, and the semiconductor region and the gate electrode 10 may be connected. In order to reduce the possibility of damage to the gate insulating layer 11 and improve the reliability of the semiconductor device 100, the width W1 is preferably greater than 28 nm.

[0052] according to Figure 7 According to the simulation results, the width W1 is preferably greater than or equal to 28 nm and less than or equal to 206 nm.

[0053] Figure 8 It means to make Figure 2 The experimental results of the change of the on-resistance Ron when the width W3 changes are shown in FIG. In the semiconductor device used in this experiment, Figure 2 The distance D shown is designed to be 295 nm. The width W1 of the contact portion 22 a is designed to be 64 nm. The width W4 is designed to be 20 nm.

[0054] according to Figure 8 The experimental results shown in FIG. 1 show that when the width W3 is less than 73 nm, the on-resistance Ron increases significantly. This is because when the width W3 is narrow, n + The contact area between the source region 3 and the source electrode 22 is reduced, n + The resistance between the source region 3 and the source electrode 22 increases. The upper limit of the width W3 is not particularly limited. As long as the width W3 is greater than 87nm, the width W3 can be appropriately set according to the width W1 of the contact portion 22a, the distance D, the spacing P, etc. For example, the width W3 is preferably greater than 87nm and less than 200nm. More preferably, the width W3 is greater than 87nm and less than 150nm.

[0055] In addition, for the bottom of the contact portion 22a, the distance D1 from the first junction J1 to the bottom surface LS in the Z direction is preferably greater than 100 nm and less than 400 nm. The distance D2 from the first junction J1 to the second junction J2 in the Z direction is preferably greater than 200 nm and less than 500 nm. The distance D3 from the second junction J2 to the bottom surface LS in the Z direction is preferably greater than 100 nm and less than 400 nm.

[0056] Advantages of the embodiment will be described.

[0057] In the semiconductor device 100, Figure 2 The distance D shown is preferably shorter. The shorter the distance D is, the more the channel density can be increased and the on-resistance of the semiconductor device 100 can be reduced. On the other hand, if the distance D is too short, the threshold voltage of the gate electrode 10 increases. In addition, the p-type impurity concentration in the region where the channel is formed increases. The effect of the increase in the p-type impurity concentration in the channel region on the increase in on-resistance may exceed the effect of reducing on-resistance brought about by increasing the channel density. As a result, the on-resistance of the semiconductor device 100 may increase.

[0058] like Figures 4 to 6 As shown in FIG. 1 , according to the results verified by the inventors of the present application, the pitch P is preferably greater than 450 nm and less than 650 nm. Figures 4 to 6 In the simulation shown, Figure 2 The width W of the gate electrode 10 shown is set to 160 nm. The thickness of the gate insulating layer 11 is set to 20 nm. In this case, the distance D is preferably greater than or equal to 250 nm and less than or equal to 450 nm.

[0059] In addition, the width W of the gate electrode 10 is preferably set within a range of 160 nm to 240 nm. As described later, the gate electrode 10 is formed by embedding a conductive material into an opening formed in the semiconductor layer. When the width W is less than 160 nm, it is difficult to evenly embed the conductive material, and a gap may be generated in the gate electrode 10. As a result, the formation of the channel in the p-type base region 2 becomes unstable, and the on-resistance may increase. On the other hand, if the width W exceeds 240 nm, the increase in on-resistance caused by the reduction in channel density becomes significant. When the spacing P is 450 nm to 650 nm, the thickness of the gate insulating layer 11 is 20 nm, and the width W is 240 nm, the distance D is preferably 150 nm to 450 nm. That is, when the width W is set within a range of 160 nm to 240 nm, the distance D is preferably 150 nm to 450 nm. By setting the distance D within this range, it is possible to suppress an increase in the threshold voltage of the gate electrode 10 and reduce the on-resistance of the semiconductor device 100 .

[0060] When the distance D is short, such as 150 nm to 450 nm, the source electrode 22 preferably includes the contact portion 22a. By providing the contact portion 22a, the contact area between the p-type base region 2 and the source electrode 22 and the n + The contact area between the p-type source region 3 and the source electrode 22 is increased. By increasing the contact area between the p-type base region 2 and the source electrode 22, holes are discharged from the p-type base region 2 to the source electrode 22. For example, when avalanche breakdown occurs in the semiconductor device 100, the rise in the potential of the p-type base region 2 can be suppressed. As a result, the semiconductor device 100 can be suppressed from operating as a bipolar transistor. That is, the latch-up of the semiconductor device 100 can be suppressed, and the avalanche resistance of the semiconductor device 100 can be improved. In addition, by making the n + The contact area between the source region 3 and the source electrode 22 increases, n + The resistance between the source region 3 and the source electrode 22 is reduced, and the semiconductor device 100 can reduce the on-resistance.

[0061] When the contact portion 22a is provided, the width W1 of the contact portion 22a also affects the characteristics of the semiconductor device 100. In particular, when the distance D is short, such as 150nm to 450nm, the characteristics of the semiconductor device 100 may vary greatly depending on the width W1. Figure 7 As shown in FIG. 1 , if the width W1 is expanded to be greater than 230 nm, the on-resistance Ron increases by more than 10% compared to the case where the width W1 is less than 100 nm. In addition, when the width W1 is less than 28 nm, more impact ionization occurs near the gate insulating layer 11, and the reliability of the semiconductor device 100 is reduced. Therefore, the width W1 is preferably greater than 28 nm and less than 206 nm.

[0062] In addition, for n located between the gate insulating layer 11 and the contact portion 22a + As mentioned above, the wider the width W3, the greater the n + On the other hand, as the width W3 increases, the width W1 of the contact portion 22a decreases, and the reliability of the semiconductor device 100 may decrease. Figure 8 The experimental results shown, Figure 2 The width W3 shown is preferably 87 nm or more. By setting the width W3 to 87 nm or more, it is possible to suppress a decrease in the reliability of the semiconductor device 100 and reduce the on-resistance of the semiconductor device 100 .

[0063] In particular, Figure 1 to Figure 3 In the semiconductor device 100 shown in the example, n +The upper surface US of the source region 3 includes a first region US1 and a second region US2. The second region US2 is generated when the contact portion 22a is formed by the manufacturing method described later. When the second region US2 exists, the width W3 of the first region US1 becomes narrower. Therefore, more detailed control is required for the width W3.

[0064] Moreover, according to the results verified by the inventors, in n + In the n-type source region 3, the resistivity of the second portion 3b is considered to be higher than that of the first portion 3a. This is considered to be because the width W4 of the second portion 3b is shorter than the width W3 of the first portion 3a, so the n-type impurities in the second portion 3b diffuse to the surroundings. Therefore, when the second portion 3b exists and the width of the first portion 3a is narrowed, n + The contact resistance between the source region 3 and the source electrode 22 is likely to increase. However, even when the second portion 3b exists, by making the width W3 greater than 87nm as described above, the reliability of the semiconductor device 100 can be suppressed from being reduced and the on-resistance of the semiconductor device 100 can be reduced.

[0065] In addition, by providing the second portion 3b, the current density of the semiconductor device 100 can be adjusted. That is, from the perspective of reducing the on-resistance, the second portion 3b is not preferred. On the other hand, the resistivity of the second portion 3b is higher than the resistivity of the first portion 3a. Therefore, the voltage drop when the current flows through the second portion 3b is greater than the voltage drop when the current flows through the first portion 3a. For example, if the semiconductor device 100 is in a short-circuit state, a large current flows through the semiconductor device 100. At this time, the voltage drop becomes larger due to the second portion 3b, so that the current flowing in the semiconductor device 100 can be suppressed. By setting the width W3 to 87nm or more on the basis of providing the second portion 3b, the on-resistance of the semiconductor device 100 can be reduced, and the current density during short circuit can be reduced.

[0066] Fig. 9 (a) Fig. 9 (b) Fig.10 (a) Fig.10 (b) Fig.11 (a) Fig.11 (b) Fig.12 (a) Fig.12 (b) and Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment.

[0067] First, prepare the + Type semiconductor layer 5x and n - A semiconductor substrate having a semiconductor layer 1x. -The type semiconductor layer 1x is provided on the n + By photolithography and reactive ion etching (RIE), on the n - An opening OP1 is formed on the upper surface of the semiconductor layer 1x. Fig. 9 As shown in (a) of FIG. 1 , a plurality of openings OP1 are formed in the X direction, and each opening OP1 extends in the Y direction.

[0068] By thermal oxidation, along n - An insulating layer 11x is formed on the surface of the semiconductor layer 1x. A conductive layer is formed on the insulating layer 11x by chemical vapor deposition (CVD). The conductive layer includes, for example, polysilicon. The opening OP1 is filled with the conductive layer. The upper surface of the conductive layer is retreated by wet etching. Fig. 9 As shown in (b) , the conductive layer is divided into a plurality of parts, and a gate electrode 10 is formed inside each opening OP1 .

[0069] An insulating layer 12x is formed on the gate electrode 10. The opening OP1 is filled with the insulating layer 12x. Chemical dry etching (CDE) is performed until n - The upper surface of the semiconductor layer 1x is exposed. Fig.10 As shown in (a), a portion of the insulating layer 11x and a portion of the insulating layer 12x are removed to expose n - type semiconductor layer 1x.

[0070] By CDE, the n between the insulating layers 12x is removed. - In CDE, a gas is selected that has a higher etching rate for the semiconductor than for the insulating layer. As the gas, for example, HBr (hydrogen bromide) is used. When CDE is performed, a difference in etching rate occurs between the portion near the insulating layer 12x and the portion away from the insulating layer 12x. It is difficult to remove the n-type semiconductor layer 1x near the insulating layer 12x. - As a result, Fig.10 As shown in (b), the upper surface of a portion near the insulating layer 12x is inclined, and the position of the upper surface is higher than the position of the upper surface of a portion away from the insulating layer 12x.

[0071] To n - The upper surface of the semiconductor layer 1x is ion-implanted with p-type impurities and n-type impurities in sequence to form a p-type semiconductor region 2x and an n-type semiconductor region 2x. + Type semiconductor region 3x. Fig.11 As shown in (a), the covering n is formed by CVD +The insulating layer 13x of the semiconductor region 3x and the insulating layer 12x. For example, the insulating layer 13x includes an insulating material such as silicon oxide or silicon nitride. As described later, the material of the insulating layer 13x can be changed as long as it can be used as a mask when etching the semiconductor layer.

[0072] A portion of the insulating layer 13x is located at n + The other part of the insulating layer 13x is located above both ends of the n-type semiconductor region 3x in the X direction. + The insulating layer 13x is partially removed by anisotropic etching until the n-type semiconductor region 3x is located above the center in the X direction. + A portion of the upper surface of the semiconductor region 3x is exposed. The thickness (dimension in the Z direction) of the portion of the insulating layer 13x is greater than the thickness of the other portion of the insulating layer 13x. Fig.11 As shown in (b), the thinner portion of the insulating layer 13x is removed, and the thicker portion remains. Specifically, on the side (n + The insulating layer 13x remains above both ends of the semiconductor region 3x, and the other parts of the insulating layer 13x are removed. + The central portion of the n-type semiconductor region 3x in the X direction is exposed. + A mask 13y is formed to cover the vicinity of the insulating layer 12x of the type semiconductor region 3x.

[0073] Use mask 13y to remove n + A portion of the p-type semiconductor region 3x and a portion of the p-type semiconductor region 2x are formed. Thus, an opening OP2 is formed. Fig.12 As shown in (a), p-type impurities are ion-implanted into the bottom surface of the opening OP2 through the opening OP2 to form a p + Type contact area 4.

[0074] The mask 13y is removed. By sputtering, the surface of the p-type semiconductor region 2x and the n + A metal layer 22x and a metal layer 22y are formed on the surface of the semiconductor region 3x. The metal layer 22x includes titanium nitride. The metal layer 22y includes titanium. Fig.12 As shown in (b), a metal layer 22z that fills the opening OP2 is formed on the metal layer 22y by sputtering. The metal layer 22z includes aluminum.

[0075] For + The lower surface of the semiconductor layer 5x is ground until n + The semiconductor layer 5x has a predetermined thickness. Fig.13 As shown, after grinding, n +On the lower surface of the type semiconductor layer 5x, a metal layer 21x and a metal layer 21y are formed by sputtering. The metal layer 21x includes titanium. The metal layer 21y includes aluminum. The semiconductor device 100 of the embodiment is manufactured through the above steps.

[0076] Fig.13 The n shown - The semiconductor layer 1x corresponds to Figure 1 The n shown - The p-type drift region 1. The p-type semiconductor region 2x corresponds to the p-type base region 2. + The semiconductor region 3x corresponds to n + Type source region 3. + The portion near the insulating layer 12x in the type semiconductor region 3x corresponds to the first portion 3a. + The portion of the N-type semiconductor region 3x that is away from the insulating layer 12x corresponds to the second portion 3b. + The type semiconductor layer 5x corresponds to n + The gate insulating layer 11x corresponds to the gate insulating layer 11. The insulating layer 12x corresponds to the insulating layer 12. The metal layer 21x corresponds to the drain electrode 21. The metal layers 22x to 22z correspond to the source electrode 22. A portion of the metal layer 22x, a portion of the metal layer 22y, and a portion of the metal layer 22z are located in the opening OP2. The portion of the metal layer 22x, the portion of the metal layer 22y, and the portion of the metal layer 22z correspond to the contact portion 22a.

[0077] When manufacturing the semiconductor device 100, the position deviation of the contact portion 22a in the X direction is preferably small. For example, if the position of the contact portion 22a is deviated, the distance between the insulating layer 11x and the contact portion 22a is shortened. + When the p-type contact region 4 is formed, the p-type impurities are easily diffused to the vicinity of the insulating layer 11x. As a result, the threshold voltage of the gate electrode 10 increases. In addition, if the position of the contact portion 22a is shifted, the distance between the other insulating layer 11x and the contact portion 22a becomes longer. The position where the impact ionization occurs changes, and the reliability of the semiconductor device 100 may be reduced.

[0078] In the manufacturing method of the embodiment, if Fig.12As shown in (a), a mask 13y is used when forming the opening OP2. The position of the mask 13y is determined based on the difference in thickness of each portion of the insulating layer 13x. Specifically, the mask 13y is formed only on the side of the insulating layer 12x and is not formed at a position away from the insulating layer 12x. That is, the position of the mask 13y is determined in a self-matching manner based on the position of the insulating layer 12x. Therefore, even when the spacing between the insulating layers 12x is narrow, the positional deviation of the mask 13y can be suppressed. As a result, the positional deviation of the opening OP2 formed using the mask 13y is also suppressed.

[0079] The embodiment of the present invention is applicable to a semiconductor device in which no conductor (so-called field plate electrode) is provided below the gate electrode 10. Generally, the field plate electrode is located at n in the Z direction. - The field plate electrode is provided between the n type drift region 1 and the gate electrode 10 and is electrically connected to the gate electrode 10 or the source electrode 22. - A thick insulating layer is provided between the drift region 1 and the field plate electrode. Therefore, it is difficult to set the spacing of the gate electrode 10 to 450nm to 650nm. By applying the above structure to a semiconductor device without a field plate electrode, the increase of the threshold voltage of the gate electrode 10 can be suppressed and the on-resistance of the semiconductor device 100 can be effectively reduced.

[0080] The embodiments of the present invention include the following features.

[0081] (Feature 1)

[0082] A semiconductor device comprising:

[0083] a first electrode;

[0084] A first semiconductor region of a first conductivity type, disposed on the first electrode;

[0085] A pair of gate electrodes, each provided on the first semiconductor region via a gate insulating layer, wherein a distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region is greater than 150 nm and less than 450 nm;

[0086] A second semiconductor region of a second conductivity type is disposed between the pair of gate electrodes;

[0087] A third semiconductor region of the first conductivity type, disposed on the second semiconductor region; and

[0088] The second electrode is arranged on the pair of gate electrodes respectively via an insulating layer, and includes a contact portion connected to a portion of the second semiconductor region and the third semiconductor region in the second direction, and the bottom of the contact portion has a length in the second direction that is longer than 28nm and less than 206nm.

[0089] (Feature 2)

[0090] A semiconductor device as described in feature 1, wherein:

[0091] The upper surface of the third semiconductor region comprises:

[0092] The first region has an inclination of not less than 0 degrees and not more than 15 degrees with respect to the second direction; and

[0093] The second region has an inclination of 30 degrees or more relative to the second direction;

[0094] The position of the first region in the second direction is between the position of the second region in the second direction and the position of the contact portion in the second direction.

[0095] (Feature 3)

[0096] A semiconductor device as described in feature 2, wherein:

[0097] The length of the first region in the second direction is greater than 87 nm,

[0098] A length of the second region in the second direction is greater than or equal to 5 nm and less than or equal to 20 nm.

[0099] (Feature 4)

[0100] A semiconductor device as described in feature 2 or 3, wherein:

[0101] The third semiconductor region comprises:

[0102] a first portion connected to the contact portion and including the first region; and

[0103] a second portion having the second region and located between the second region and the insulating layer;

[0104] The concentration of the first conductivity type impurity in the second portion is lower than the concentration of the first conductivity type impurity in the first portion.

[0105] (Feature 5)

[0106] The semiconductor device according to any one of features 1 to 4, wherein:

[0107] A first distance from a first junction between the first semiconductor region and the second semiconductor region to a bottom surface of the contact portion is longer than 0.5 times a second distance from the first junction to a second junction between the second semiconductor region and the third semiconductor region.

[0108] (Feature 6)

[0109] The semiconductor device according to any one of features 1 to 5, wherein:

[0110] The semiconductor device further includes a fourth semiconductor region of the second conductivity type provided between the second semiconductor region and the contact portion.

[0111] The second conductivity type impurity concentration of the fourth semiconductor region is higher than the second conductivity type impurity concentration of the second semiconductor region.

[0112] (Feature 7)

[0113] The semiconductor device according to any one of features 1 to 6, wherein:

[0114] A sum of the distance between the gate insulating layers, the length of one gate electrode of the pair of gate electrodes in the second direction, and twice the thickness of the gate insulating layer is greater than or equal to 450 nm and less than or equal to 650 nm.

[0115] The relative height of the impurity concentration between each semiconductor region in each embodiment described above can be confirmed, for example, using a scanning electrostatic capacitance microscope (SCM). In addition, the carrier concentration in each semiconductor region can be regarded as equal to the impurity concentration activated in each semiconductor region. Therefore, the relative height of the carrier concentration between each semiconductor region can also be confirmed using SCM. In addition, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0116] Several embodiments of the present invention are illustrated above, but these embodiments are proposed as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their modifications are included in the scope and main purpose of the invention, and are included in the invention described in the claims and their equivalents. In addition, the aforementioned embodiments can be implemented in combination with each other.

Claims

1. A semiconductor device, characterized in that: have: a first electrode; A first semiconductor region of a first conductivity type, disposed on the first electrode; A pair of gate electrodes, each provided on the first semiconductor region via a gate insulating layer, wherein a distance between the gate insulating layers in a second direction perpendicular to a first direction from the first electrode toward the first semiconductor region is greater than 150 nm and less than 450 nm; A second semiconductor region of a second conductivity type is disposed between the pair of gate electrodes; A third semiconductor region of the first conductivity type, disposed on the second semiconductor region; as well as The second electrode is arranged on the pair of gate electrodes respectively via an insulating layer, and includes a contact portion connected to a portion of the second semiconductor region and the third semiconductor region in the second direction, and the bottom of the contact portion has a length in the second direction that is longer than 28nm and less than 206nm.

2. The semiconductor device according to claim 1, wherein The upper surface of the third semiconductor region comprises: The first area has an inclination of not less than 0 degrees and not more than 15 degrees with respect to the second direction; and The second region has an inclination of 30 degrees or more relative to the second direction; The position of the first region in the second direction is between the position of the second region in the second direction and the position of the contact portion in the second direction.

3. The semiconductor device according to claim 2, wherein: The length of the first region in the second direction is greater than 87 nm, A length of the second region in the second direction is greater than or equal to 5 nm and less than or equal to 20 nm.

4. The semiconductor device according to claim 2 or 3, wherein: The third semiconductor region comprises: a first portion connected to the contact portion and including the first region; and a second portion having the second region and located between the second region and the insulating layer; The concentration of the first conductivity type impurity in the second portion is lower than the concentration of the first conductivity type impurity in the first portion.

5. The semiconductor device according to any one of claims 1 to 3, wherein A first distance from a first junction between the first semiconductor region and the second semiconductor region to a bottom surface of the contact portion is longer than 0.5 times a second distance from the first junction to a second junction between the second semiconductor region and the third semiconductor region.

6. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor device further includes a fourth semiconductor region of the second conductivity type provided between the second semiconductor region and the contact portion. The second conductivity type impurity concentration of the fourth semiconductor region is higher than the second conductivity type impurity concentration of the second semiconductor region.

7. The semiconductor device according to any one of claims 1 to 3, wherein A sum of the distance between the gate insulating layers, the length of one gate electrode of the pair of gate electrodes in the second direction, and twice the thickness of the gate insulating layer is greater than or equal to 450 nm and less than or equal to 650 nm.

Images