ESD protection device

Abstract

The invention relates to an ESD (Electro-Static Discharge) protection device, which comprises an N well; a P well; the first P-type region is positioned in the N well; the second P-type region is positioned in the N well; the first grid electrode is positioned above the N well between the first P-type region and the second P-type region; the first N-type region is positioned in the P well; the second N-type region is positioned in the P well; the second grid electrode is positioned above the P well between the first N-type region and the second N-type region; the third P-type region is positioned between the N well and the P well and is connected with the N well and the P well; wherein the second P-type region, the N well, the first grid electrode and the second N-type region are used for being connected with an anode, and the first P-type region, the P well, the first N-type region and the second grid electrode are used for being connected with a cathode. The ESD protection device has low trigger voltage and high secondary breakdown current, and the robustness of the ESD protection device can be greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an ESD protection device. Background Art

[0002] Electrostatic discharge protection (ESD) is an important part of integrated circuit (IC) design. Figure 1 , ESD protection devices are used between the anode Anode (also known as the positive electrode) and the cathode Cathode (also known as the negative electrode).

[0003] The SOI (Silicon on Insulator) process has the advantages of low power consumption, high speed, and anti-latch effect. However, due to the thin thickness of the bulk silicon layer of the SOI device, it is difficult to achieve strong ESD capabilities, which limits the application of SOI devices in special fields. In addition, with the miniaturization of process nodes, the design window of ESD is getting narrower and narrower, posing higher challenges to the electrostatic protection of SOI devices. Therefore, it is of great significance to design SOI electrostatic protection devices with low trigger voltage and high secondary breakdown current. Summary of the invention

[0004] Based on this, it is necessary to provide an ESD protection device with lower trigger voltage and higher secondary breakdown current.

[0005] An ESD protection device comprises: an N-well; a P-well; a first P-type region located in the N-well; a second P-type region located in the N-well; a first gate located above the N-well between the first P-type region and the second P-type region; a first N-type region located in the P-well; a second N-type region located in the P-well; a second gate located above the P-well between the first N-type region and the second N-type region; a third P-type region located between the N-well and the P-well and connected to the N-well and the P-well; wherein the second P-type region, the N-well, the first gate and the second N-type region are used to connect to an anode, and the first P-type region, the P-well, the first N-type region and the second gate are used to connect to a cathode.

[0006] The ESD protection device, the first P-type region, the second P-type region, the N-well and the first gate constitute a GDPMOS (the gate is connected to V DDThe first N-type region, the second N-type region, the P-well and the second gate constitute a GGNMOS (a gate-grounded N-channel metal oxide semiconductor field effect transistor), the second P-type region, the N-well, the P-well and the first N-type region constitute an SCR (Silicon Controlled Rectifier, thyristor) structure, and the third P-type region and the N-well constitute a parasitic diode. When the anode is subjected to ESD stress, the diode is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. Among them, the holes move toward the cathode, and the generated hole current forms a voltage drop on the parasitic resistance formed by the P-well, causing the NPN transistor in the SCR to turn on. The collector current of the NPN transistor flows through the parasitic resistance formed by the N-well to generate a voltage drop, causing the PNP transistor in the SCR to turn on, and the SCR turns on. In addition, the GGNMOS and GDPMOS will also turn on, forming two other paths for discharging current. In this way, the avalanche breakdown of the parasitic diode can be used to reduce the trigger voltage of the entire ESD protection device, and the secondary breakdown current can be increased by using GGNMOS and GDPMOS, which can greatly improve the robustness of the ESD protection device.

[0007] In one embodiment, the first P-type region serves as the drain of the PMOS, the second P-type region serves as the source of the PMOS, and the first gate serves as the gate of the PMOS; the first N-type region serves as the source of the NMOS, the second N-type region serves as the drain of the NMOS, and the second gate serves as the gate of the NMOS; the second P-type region also serves as the emitter of the PNP transistor in the thyristor, the N-well serves as the base of the PNP transistor and the collector of the NPN transistor in the thyristor, the P-well serves as the collector of the PNP transistor and the base of the NPN transistor, and the first N-type region also serves as the emitter of the NPN transistor; the third P-type region serves as the anode of the diode, and the N-well also serves as the cathode of the diode.

[0008] In one embodiment, the ESD protection device further includes: an N-well lead-out region, the N-well lead-out region is in direct contact with the N-well, has N-type doping and a doping concentration greater than that of the N-well, and the N-well is connected to the anode through the N-well lead-out region.

[0009] In one embodiment, the ESD protection device further includes: a P-well lead-out region, the P-well lead-out region is in direct contact with the P-well, has P-type doping and a doping concentration greater than the doping concentration of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

[0010] In one of the embodiments, the third P-type region is in direct contact with the N-well and the P-well.

[0011] In one embodiment, the third P-type region is located between the N-well lead-out region and the P-well lead-out region.

[0012] In one embodiment, the N-well is in direct contact with the side surface and the bottom surface of the third P-type region, and the P-well is in direct contact with the side surface and the bottom surface of the third P-type region.

[0013] In one embodiment, the N-well lead-out region is surrounded by the N-well in a cross section; a portion of the second P-type region is located between the first N-well and the N-well lead-out region, and a portion of the second P-type region is located on both sides of the N-well surrounding the N-well lead-out region in a channel width direction, and the first N-well is the N-well under the first gate.

[0014] In one embodiment, the P-well lead-out region is surrounded by the P-well in a cross section; a portion of the first N-type region is located between the first P-well and the P-well lead-out region, and a portion is located on both sides of the P-well surrounding the P-well lead-out region in a channel width direction, and the first P-well is the P-well below the second gate.

[0015] In one of the embodiments, it also includes a floating gate structure, which is located above the N-well surrounding the N-well lead-out region, above the P-well surrounding the P-well lead-out region, and above the N-well and P-well between the second P-type region and the first N-type region, and the floating gate structure includes a dielectric layer and a gate on the dielectric layer.

[0016] In one embodiment, the ESD protection device is a silicon-on-insulator device, the ESD protection device includes bottom silicon and a buried oxide layer on the bottom silicon, and the N-well and the P-well are located above the buried oxide layer.

[0017] It is also necessary to provide another ESD protection device.

[0018] An ESD protection device, comprising:

[0019] The thyristor comprises a PNP transistor and an NPN transistor, wherein the base of the PNP transistor is connected to the collector of the NPN transistor, and the collector of the PNP transistor is connected to the base of the NPN transistor; a diode, wherein the positive electrode is connected to the collector of the PNP transistor and the base of the NPN transistor; and an NMOS transistor; wherein the drain of the NMOS transistor, the cathode of the diode, and the emitter of the PNP transistor are used to connect to the anode, and the gate and source of the NMOS tube and the emitter of the NPN transistor are used to connect to the cathode.

[0020] In the above-mentioned ESD protection device, the NMOS tube is a GGNMOS with the gate connected to the cathode. When the anode is subjected to ESD stress, the diode is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The holes move toward the cathode, and the generated hole current forms a voltage drop, causing the NPN transistor in the SCR to turn on. The collector current of the NPN transistor produces a voltage drop, causing the PNP transistor in the SCR to turn on, and the SCR turns on. In addition, the GGNMOS will also turn on, forming another path for the discharge current. In this way, the trigger voltage of the entire ESD protection device can be reduced, and the secondary breakdown current can be increased, which can greatly improve the robustness of the ESD protection device.

[0021] In one embodiment, the ESD protection device further includes a PMOS tube, a gate and a source of the PMOS tube are used to connect to the anode, and a drain of the PMOS tube is used to connect to the cathode.

[0022] In one embodiment, the ESD protection device also includes: a first voltage divider unit, one end of the first voltage divider unit is used to connect the anode, and the other end of the first voltage divider unit is connected to the base of the PNP transistor and the collector of the NPN transistor; a second voltage divider unit, one end of the second voltage divider unit is connected to the positive electrode of the diode and the base of the NPN transistor, and the other end of the first voltage divider unit is used to connect the cathode.

[0023] In one embodiment, the first voltage dividing unit is a first resistor, and the second voltage dividing unit is a second resistor.

[0024] There is also a need to provide yet another ESD protection device.

[0025] An ESD protection device comprises: a thyristor, comprising a PNP triode and an NPN triode, wherein the base of the PNP triode is connected to the collector of the NPN triode, and the collector of the PNP triode is connected to the base of the NPN triode; a diode, wherein the positive electrode is connected to the collector of the PNP triode and the base of the NPN triode; and a PMOS tube; wherein the cathode of the diode, the emitter of the PNP triode, and the gate and source of the PMOS tube are used to connect to the anode, and the emitter of the NPN triode and the drain of the PMOS tube are used to connect to the cathode.

[0026] In the above-mentioned ESD protection device, the PMOS tube is a GDPMOS with the gate connected to the anode. When the anode is subjected to ESD stress, the diode is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The holes move toward the cathode, and the generated hole current forms a voltage drop, causing the NPN transistor in the SCR to turn on. The collector current of the NPN transistor produces a voltage drop, causing the PNP transistor in the SCR to turn on, and the SCR turns on. In addition, the GDPMOS will also turn on, forming another path for the discharge current. In this way, the trigger voltage of the entire ESD protection device can be reduced, and the secondary breakdown current can be increased, which can greatly improve the robustness of the ESD protection device.

[0027] In one embodiment, the ESD protection device also includes: a first resistor, one end of which is used to connect to the anode, and the other end of which is connected to the base of the PNP transistor and the collector of the NPN transistor; a second resistor, one end of which is connected to the positive electrode of the diode and the base of the NPN transistor, and the other end of which is used to connect to the cathode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0029] Figure 1 An exemplary circuit architecture in which an ESD protection device is connected;

[0030] Figure 2a is an exemplary GGNMOS layout structure. Figure 2b is a schematic diagram of its cross-sectional structure;

[0031] Figure 3 is an exemplary TLP (transmission line pulse) curve of GGNMOS;

[0032] Figure 4 is a circuit schematic diagram of an ESD protection device in an embodiment of the present application;

[0033] Figure 5 is a circuit schematic diagram of an ESD protection device in another embodiment of the present application;

[0034] Figure 6 is a circuit schematic diagram of an ESD protection device in another embodiment of the present application;

[0035] Figure 7is a layout of an ESD protection device in an embodiment of the present application;

[0036] Figure 8 is along Figure 7 Sectional view along line A-A';

[0037] Fig. 9 is along Figure 7 Cross-sectional view along line BB'. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0044] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0045] Among many traditional SOI ESD protection devices, GGNMOS (Gate Grounded N-Channel Metal Oxide Semiconductor Field Effect Transistor) is a commonly used one. GGNMOS often uses a multi-finger structure to increase the breakdown current of the ESD device. A two-finger GGNMOS structure such as Figure 2a and Figure 2b shown.

[0046] For traditional GGNMOS, when there is a positive ESD pulse at the anode, the voltage of GGNMOS rises to the trigger voltage Vt1, such as Figure 3 As shown, the parasitic NPN transistor is turned on and discharged. At this time, there will be a rapid voltage hysteresis phenomenon (snapback). After the voltage drops back to the holding voltage Vh, as the ESD pulse continues to increase, the GGNMOS continues to discharge, and the voltage across the device increases accordingly. After reaching the breakdown voltage Vt2, the device burns out. It can be seen that since Vt2 is generally less than Vt1, after a few parasitic NPN transistors of the multi-finger structure (usually the ones near the middle) are turned on and triggered, the other surrounding parasitic NPN transistors do not have time to turn on, and the device burns out. This is what the industry calls the uneven conduction phenomenon of ESD devices, which will result in a lower secondary breakdown current of the GGNMOS. In addition, the GGNMOS structure needs to ensure that the emitter junction voltage of the parasitic NPN tube reaches the threshold voltage before it will turn on, so the trigger voltage of the device is relatively high. If Vt1 is higher than V DD , which will make the device unsuitable for use in low power supply voltage scenarios.

[0047] In view of the problems existing in the above-mentioned designs, the present application designs an ESD protection device with low trigger voltage and high secondary breakdown current, which can greatly improve the robustness of the ESD protection device.

[0048] Figure 4 1 is a circuit diagram of an ESD protection device in an embodiment of the present application. In this embodiment, the ESD protection device includes a thyristor (SCR), a diode D and an NMOS tube Mn. The thyristor includes a PNP transistor Qp and an NPN transistor Qn, and the NMOS tube Mn is a GGNMOS (a gate-grounded N-channel metal oxide semiconductor field effect transistor). The base of the PNP transistor Qp is connected to the collector of the NPN transistor Qn, and the collector of the PNP transistor Qp is connected to the base of the NPN transistor Qn. The positive electrode of the diode D is connected to the collector of the PNP transistor Qp and the base of the NPN transistor Qn. The drain of the NMOS tube Mn, the negative electrode of the diode D, and the emitter of the PNP transistor Qp are connected to the anode. The gate and source of the NMOS tube Mn and the emitter of the NPN transistor Qn are connected to the cathode.

[0049] In the above-mentioned ESD protection device, when the anode is subjected to ESD stress, the diode D is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The holes move toward the cathode, and the generated hole current forms a voltage drop, causing the NPN transistor Qn in the SCR to turn on. The collector current of the NPN transistor Qn produces a voltage drop, causing the PNP transistor Qp in the SCR to turn on, and the SCR turns on. In addition, the GGNMOS will also turn on, forming another path for discharging current. In this way, the trigger voltage of the entire ESD protection device can be reduced, and the secondary breakdown current can be increased, which can greatly improve the robustness of the ESD protection device.

[0050] In one embodiment of the present application, a first voltage divider unit is connected between the anode and the base of the PNP transistor Qp, and a second voltage divider unit is connected between the cathode and the positive electrode of the diode D. The first voltage divider unit and the second voltage divider unit are used to form a voltage drop when current flows. Figure 4 In the illustrated embodiment, the first voltage dividing unit is a resistor Rnw, and the second voltage dividing unit is a resistor Rpw.

[0051] Figure 5 FIG. 1 is a circuit diagram of an ESD protection device in another embodiment of the present application. In this embodiment, the ESD protection device includes a thyristor, a diode D and a PMOS transistor Mp. The thyristor includes a PNP transistor Qp and an NPN transistor Qn. The PMOS transistor Mp is a GDPMOS (the gate is connected to V DD The base of the PNP transistor Qp is connected to the collector of the NPN transistor Qn, and the collector of the PNP transistor Qp is connected to the base of the NPN transistor Qn. The anode of the diode D is connected to the collector of the PNP transistor Qp and the base of the NPN transistor Qn. The gate and source of the PMOS tube, the cathode of the diode D, and the emitter of the PNP transistor Qp are connected to the anode. The drain of the PMOS tube and the emitter of the NPN transistor Qn are connected to the cathode.

[0052] In the above-mentioned ESD protection device, when the anode is subjected to ESD stress, the diode D is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The holes move toward the cathode, and the generated hole current forms a voltage drop, causing the NPN transistor Qn in the SCR to turn on. The collector current of the NPN transistor Qn produces a voltage drop, causing the PNP transistor Qp in the SCR to turn on, and the SCR turns on. In addition, the GDPMOS will also turn on, forming another path for the discharge current. In this way, the trigger voltage of the entire ESD protection device can be reduced, and the secondary breakdown current can be increased, which can greatly improve the robustness of the ESD protection device.

[0053] In one embodiment of the present application, a first voltage divider unit is connected between the anode and the base of the PNP transistor Qp, and a second voltage divider unit is connected between the cathode and the positive electrode of the diode D. The first voltage divider unit and the second voltage divider unit are used to form a voltage drop when current flows. Figure 5 In the illustrated embodiment, the first voltage dividing unit is a resistor Rnw, and the second voltage dividing unit is a resistor Rpw.

[0054] Figure 6 : This is a circuit schematic diagram of an ESD protection device in another embodiment of the present application. In this embodiment, the ESD protection device includes a thyristor, a diode D, an NMOS tube Mn and a PMOS tube Mp. The thyristor includes a PNP transistor Qp and an NPN transistor Qn, the NMOS tube Mn is a GGNMOS, and the PMOS tube Mp is a GDPMOS. The base of the PNP transistor Qp is connected to the collector of the NPN transistor Qn, and the collector of the PNP transistor Qp is connected to the base of the NPN transistor Qn. The positive electrode of the diode D is connected to the collector of the PNP transistor Qp and the base of the NPN transistor Qn. The drain of the NMOS tube Mn, the gate and source of the PMOS tube, the negative electrode of the diode D, and the emitter of the PNP transistor Qp are connected to the anode. The gate and source of the NMOS tube Mn, the drain of the PMOS tube, and the emitter of the NPN transistor Qn are connected to the cathode.

[0055] In the above-mentioned ESD protection device, when the anode is subjected to ESD stress, the diode D is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. The holes move toward the cathode, and the generated hole current forms a voltage drop, which makes the NPN transistor Qn in the SCR turn on. The collector current of the NPN transistor Qn produces a voltage drop, which makes the PNP transistor Qp in the SCR turn on, and the SCR turns on. In addition, the GGNMOS and GDPMOS will also turn on, forming two other discharge current paths. In this way, the trigger voltage of the entire ESD protection device can be reduced, and the secondary breakdown current can be increased, which can greatly improve the robustness of the ESD protection device.

[0056] In one embodiment of the present application, a first voltage divider unit is connected between the anode and the base of the PNP transistor Qp, and a second voltage divider unit is connected between the cathode and the positive electrode of the diode D. The first voltage divider unit and the second voltage divider unit are used to form a voltage drop when current flows. Figure 6 In the illustrated embodiment, the first voltage dividing unit is a resistor Rnw, and the second voltage dividing unit is a resistor Rpw.

[0057] Figure 7 is a layout diagram of an ESD protection device in an embodiment of the present application, Figure 8 is along Figure 7 The cross-sectional view of the A-A' line, Fig. 9 is along Figure 7 The ESD protection device includes an N-well 122, a P-well 124, a first P-type region 132, a second P-type region 134, a third P-type region 136, a first N-type region 142, a second N-type region 144, a first gate 152, and a second gate 154. The first P-type region 132 and the second P-type region 134 are located in the N-well 122. The first gate 152 is located above the N-well 122 between the first P-type region 132 and the second P-type region 134. The first N-type region 142 and the second N-type region 144 are located in the P-well 124. The second gate 154 is located above the P-well 124 between the first N-type region 142 and the second N-type region 144. The third P-type region 136 is located between the N-well 122 and the P-well 124, and is connected to the N-well 122 and the P-well 124. The second P-type region 134 , the N-well 122 , the first gate 152 and the second N-type region 144 are connected to the anode, and the first P-type region 132 , the P-well 124 , the first N-type region 142 and the second gate 154 are connected to the cathode. Figure 7 The circuit schematic diagram of the ESD protection device shown can be referred to Figure 6 .

[0058] In the above-mentioned ESD protection device, the first P-type region 132, the second P-type region 134, the N-well 122 and the first gate 152 constitute GDPMOS, the first N-type region 142, the second N-type region 144, the P-well 124 and the second gate 154 constitute GGNMOS, the second P-type region 134, the N-well 122, the P-well 124, the first N-type region 142 constitute an SCR structure, and the third P-type region 136 and the N-well 124 constitute a diode D. When the anode is subjected to ESD stress, the diode D is reverse biased, and avalanche breakdown will occur first, generating a large number of holes and electrons. Among them, the holes move toward the cathode, and the generated hole current forms a voltage drop on the parasitic resistance Rpw formed by the P-well 124, so that the NPN transistor Qn in the SCR is turned on. The collector current of the NPN transistor Qn flows through the parasitic resistance Rnw formed by the N-well 122 to generate a voltage drop, so that the PNP transistor Qp in the SCR is turned on, and the SCR is turned on. In addition, GGNMOS and GDPMOS will also be turned on, forming two other discharge current paths. In this way, the avalanche breakdown of diode D can be used to reduce the trigger voltage of the entire ESD protection device, and at the same time, the SCR and GGNMOS / GDPMOS are effectively combined to increase the secondary breakdown current and the discharge current capacity per unit area of ​​the ESD protection device, which can greatly improve the robustness of the ESD protection device.

[0059] exist Figure 7In the illustrated embodiment, the ESD protection device further includes an N-well lead-out region 146 and a P-well lead-out region 138. The N-well lead-out region 146 is in direct contact with the N-well 122, and the N-well lead-out region 146 has an N-type doping and a doping concentration greater than that of the N-well 122, and the N-well 122 is connected to the anode through the N-well lead-out region 146. The P-well lead-out region 138 is in direct contact with the P-well 124, and the P-well lead-out region 138 has a P-type doping and a doping concentration greater than that of the P-well 124, and the P-well 124 is connected to the cathode through the P-well lead-out region 138.

[0060] In one embodiment of the present application, the first gate 152 and the second gate 154 are made of polysilicon material. In other embodiments, metal, metal nitride, metal silicide or other similar compounds can also be used as the material of the first gate 152 and the second gate 154. A gate dielectric layer is also provided below the first gate 152 and the second gate 154. In one embodiment of the present application, the gate dielectric layer may include a conventional dielectric material such as silicon oxide, nitride and oxynitride with a dielectric constant from about 4 to about 20 (measured in vacuum), or the gate dielectric layer may include a generally higher dielectric constant dielectric material with a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials may include, but are not limited to, hafnium oxide, hafnium silicate, titanium oxide, barium strontium titanate (BSTs) and lead zirconate titanate (PZTs).

[0061] In one embodiment of the present application, the third P-type region 136 is in direct contact with the N-well 122 and also in direct contact with the P-well 124 .

[0062] In one embodiment of the present application, the third P-type region 136 is located between the N-well lead-out region 146 and the P-well lead-out region 138. The third P-type region 136 is separated from the N-well lead-out region 146 by the N-well 122, and the third P-type region 136 is separated from the P-well lead-out region 138 by the P-well 124.

[0063] In one embodiment of the present application, the doping concentration of the first P-type region 132 and the second P-type region 134 is greater than the doping concentration of the P-well 124. In one embodiment of the present application, the doping concentration of the third P-type region 136 is greater than the doping concentration of the P-well 124, so that the reverse breakdown voltage of the diode D is lower than the PN junction formed by the N-well 122 and the P-well 124. In one embodiment of the present application, the doping concentration of the first N-type region 142 is greater than the doping concentration of the N-well 122. In one embodiment of the present application, the doping concentration of the second N-type region 144 is greater than the doping concentration of the N-well 122. Figure 7In the illustrated embodiment, the first P-type region 132 , the second P-type region 134 , the third P-type region 136 , and the P-well lead region 138 are P+ regions, and the first N-type region 142 , the second N-type region 144 , and the N-well lead region 146 are N+ regions.

[0064] In one embodiment of the present application, the N-well 122 is in direct contact with the side surface and the bottom surface of the third P-type region 136 , and the P-well 124 is in direct contact with the side surface and the bottom surface of the third P-type region 136 .

[0065] In one embodiment of the present application, the N-well lead-out region 146 is surrounded by the N-well 122 in a cross section. A portion of the second P-type region 134 is located between the first N-well and the N-well lead-out region 146, and a portion is located on both sides of the N-well 122 surrounding the N-well lead-out region 146 in the channel width direction, wherein the first N-well is the N-well 122 below the first gate 152, and the channel width direction is Figure 8 The Y-axis direction in the channel length direction is Figure 8 In the X-axis direction. Figure 8 In the illustrated embodiment, the N-well lead-out region 146 is separated from the second P-type region 134 by the N-well 122 .

[0066] In one embodiment of the present application, the P-well lead-out region 138 is surrounded by the P-well 124 in a cross section. A portion of the first N-type region 142 is located between the first P-well and the P-well lead-out region 138, and a portion is located on both sides of the P-well 124 surrounding the P-well lead-out region 138 in the channel width direction, wherein the first P-well is the P-well 122 below the second gate 154. Figure 8 In the illustrated embodiment, the P-well lead-out region 138 is separated from the first N-type region 142 by the P-well 124 .

[0067] In one embodiment of the present application, the ESD protection device further includes a floating gate structure 156. The floating gate structure 156 is located above the N-well 122 surrounding the N-well lead-out region 146, above the P-well 124 surrounding the P-well lead-out region 138, and above the N-well 122 between the second P-type region 134 and the first N-type region 142 (and above the P-well 124 between the second P-type region 134 and the first N-type region 142). The floating gate structure 156 specifically includes a dielectric layer and a gate on the dielectric layer.

[0068] In one embodiment of the present application, the ESD protection device is a silicon-on-insulator (SOI) device including bottom silicon, a buried oxide layer on the bottom silicon, and top silicon 110 on the buried oxide layer, wherein the N well 122 and the P well 124 are located in the top silicon 110 on the buried oxide layer.

[0069] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0070] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0071] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. An ESD protection device, characterized in that: include: N-well; P well; A first P-type region, located in the N-well; A second P-type region, located in the N-well; a first gate, located above the N-well between the first P-type region and the second P-type region; A first N-type region, located in the P-well; A second N-type region, located in the P-well; a second gate located above the P-well between the first N-type region and the second N-type region; a third P-type region, located between the N-well and the P-well, and connected to the N-well and the P-well; The second P-type region, N-well, first gate and second N-type region are used to connect to the anode, and the first P-type region, P-well, first N-type region and second gate are used to connect to the cathode.

2. The ESD protection device according to claim 1, characterized in that: Also includes: an N-well lead-out region, the N-well lead-out region being in direct contact with the N-well and having N-type doping and a doping concentration greater than that of the N-well, the N-well being connected to the anode through the N-well lead-out region; A P-well lead-out region, the P-well lead-out region is in direct contact with the P-well, has P-type doping and a doping concentration greater than that of the P-well, and the P-well is connected to the cathode through the P-well lead-out region.

3. The ESD protection device according to claim 2, characterized in that: The third P-type region is in direct contact with the N-well and the P-well.

4. The ESD protection device according to claim 2, characterized in that: The third P-type region is located between the N-well lead-out region and the P-well lead-out region.

5. The ESD protection device according to claim 2, characterized in that: The N-well lead-out region is surrounded by the N-well in a cross section; a portion of the second P-type region is located between the first N-well and the N-well lead-out region, and a portion of the second P-type region is located on both sides of the N-well surrounding the N-well lead-out region in a channel width direction, and the first N-well is the N-well below the first gate; The P-well lead-out region is surrounded by the P-well in a cross section; a portion of the first N-type region is located between the first P-well and the P-well lead-out region, and a portion is located on both sides of the P-well surrounding the P-well lead-out region in a channel width direction, and the first P-well is the P-well below the second gate.

6. The ESD protection device according to any one of claims 1 to 5, characterized in that: The ESD protection device is a silicon-on-insulator device, comprising bottom silicon and a buried oxide layer on the bottom silicon, and the N-well and the P-well are located above the buried oxide layer.

7. An ESD protection device, characterized in that: include: The thyristor comprises a PNP transistor and an NPN transistor, wherein the base of the PNP transistor is connected to the collector of the NPN transistor, and the collector of the PNP transistor is connected to the base of the NPN transistor; A diode, the positive electrode of which is connected to the collector of the PNP transistor and the base of the NPN transistor; NMOS tube; Among them, the drain of the NMOS tube, the cathode of the diode, and the emitter of the PNP transistor are used to connect to the anode, and the gate and source of the NMOS tube and the emitter of the NPN transistor are used to connect to the cathode.

8. The ESD protection device according to claim 7, characterized in that: Also includes: a first resistor, one end of which is used to connect to the anode, and the other end of which is connected to the base of the PNP transistor and the collector of the NPN transistor; A second resistor, one end of the second resistor is connected to the anode of the diode and the base of the NPN transistor, and the other end of the first resistor is used to connect to the cathode.

9. The ESD protection device according to claim 7 or 8, characterized in that: A PMOS tube is also included, wherein the gate and source of the PMOS tube are used to connect to the anode, and the drain of the PMOS tube is used to connect to the cathode.

10. An ESD protection device, characterized in that: include: The thyristor comprises a PNP transistor and an NPN transistor, wherein the base of the PNP transistor is connected to the collector of the NPN transistor, and the collector of the PNP transistor is connected to the base of the NPN transistor; A diode, the positive electrode of which is connected to the collector of the PNP transistor and the base of the NPN transistor; PMOS tube; Among them, the cathode of the diode, the emitter of the PNP transistor, the gate and source of the PMOS tube are used to connect to the anode, and the emitter of the NPN transistor and the drain of the PMOS tube are used to connect to the cathode.

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