Heterojunction battery structure and preparation method thereof

Abstract

The invention relates to a heterojunction cell structure and a preparation method thereof. The heterojunction cell structure comprises an intermediate cell structure which is N-type monocrystalline silicon; the front cell structure comprises a front intrinsic amorphous silicon film and N-type amorphous silicon, the front intrinsic amorphous silicon film is stacked on one side of the middle cell structure, and the N-type amorphous silicon is stacked on one side, away from the middle cell structure, of the front intrinsic amorphous silicon film; the back cell structure comprises a back intrinsic amorphous silicon film and P-type amorphous silicon, the back intrinsic amorphous silicon film is stacked on the other side of the middle cell structure, and the P-type amorphous silicon is stacked on the side, away from the middle cell structure, of the back intrinsic amorphous silicon film; the thickness of the front intrinsic amorphous silicon film and the thickness of the back intrinsic amorphous silicon film are 5-10 nm, the thickness of the N-type amorphous silicon and the thickness of the p-type amorphous silicon are 15-20 nm, and the technical problem that the production cost is increased when a PECVD film making machine and vacuum equipment are used is solved.

Description

Technical Field

[0001] The invention belongs to the technical field of batteries and relates to a heterojunction battery structure and a preparation method thereof. Background Art

[0002] Heterojunction cells use N-type monocrystalline silicon as the substrate light absorption area, and deposit silicon-based thin film layers with different characteristics on the front and back surfaces to form a heterojunction structure; after the heterojunction structure is formed, a transparent conductive film layer is deposited and a metal electrode is attached. Heterojunction cell process technology combines traditional crystalline silicon cell technology with nano-scale coating technology used in the semiconductor field to form an emerging solar cell technology.

[0003] The raw material of P-type cells is P-type silicon wafers, and the raw material of N-type cells is N-type silicon wafers. P-type cells include BSF cells and PERC cells, and N-type cells include heterojunction cells and TOPCon cells. P-type monocrystalline and polycrystalline cells use aluminum back field technology. PERC technology is the current mainstream P-type monocrystalline cell technology. It has a simple manufacturing process and low cost, and can be superimposed with SE selective emission technology to improve cell conversion efficiency. N-type cells have the advantages of high conversion efficiency, high bifaciality, low temperature coefficient, no light decay, good weak light effect, and longer carrier lifetime.

[0004] Heterojunction cells have high yield and high theoretical efficiency limit, and are favored by investors and the industrial chain. However, the heterojunction process route is not as interoperable as PERC and cannot be extended. It can only be newly put into production. In addition, the heterojunction cell production equipment is incompatible with the PERC production equipment. The introduction of PECVD film making machines and vacuum equipment has increased the production cost of heterojunction cells. In addition, since the amorphous silicon film of heterojunction cells has a high hydrogen content, low-temperature silver paste must be used in the screen printing process, but the localization rate of low-temperature silver paste is low and the consumption is large, which leads to the cost of heterojunction cells being much higher than the cost of PERC. Summary of the invention

[0005] The present invention overcomes the deficiencies of the above-mentioned prior art and provides a heterojunction battery structure and a preparation method thereof. The structural intermediate layer of the heterojunction battery is N-type single crystal silicon (n type c-Si); after texturing and cleaning, an intrinsic amorphous silicon film (ia-Si:H) with a thickness of 5-10nm and an N-type amorphous silicon (na-Si:H) doped with 15-20nm are deposited on the front side of the N-type single crystal silicon in sequence; an intrinsic amorphous silicon film (ia-Si:H) with a thickness of 5-10nm and a P-type amorphous silicon (pa-Si:H) doped with 15-20nm are deposited on the back side of the N-type single crystal silicon to form a PN heterojunction; then a conductive oxide film (TCO) is deposited on both sides, and the conductive film can not only reduce the series resistance when collecting current, but also play an anti-reflection role like silicon nitride on a crystalline silicon battery; finally, metal is printed on the surfaces of both sides of the conductive oxide film through a screen to form a metal-based electrode.

[0006] In order to achieve the above object, the present invention adopts the following technical solution: The present invention provides a heterojunction battery structure, comprising: an intermediate battery structure, wherein the intermediate battery structure is N-type monocrystalline silicon; a front battery structure, wherein the front battery structure comprises a front intrinsic amorphous silicon film and N-type amorphous silicon, wherein the front intrinsic amorphous silicon film is stacked and arranged on one side of the intermediate battery structure, and the N-type amorphous silicon is stacked and arranged on a side of the front intrinsic amorphous silicon film away from the intermediate battery structure; a back battery structure, wherein the back battery structure comprises a back intrinsic amorphous silicon film and P-type amorphous silicon, wherein the back intrinsic amorphous silicon film is stacked and arranged on the other side of the intermediate battery structure, and the P-type amorphous silicon is stacked and arranged on a side of the back intrinsic amorphous silicon film away from the intermediate battery structure; the thickness of the front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film is 5-10nm, and the thickness of the N-type amorphous silicon and the p-type amorphous silicon is 15-20nm.

[0007] Furthermore, it also includes a conductive oxide film structure, which includes a front conductive oxide film and a back conductive oxide film; the front conductive oxide film is arranged on the side of the N-type amorphous silicon away from the front intrinsic amorphous silicon film, and the back conductive oxide film is arranged on the side of the P-type amorphous silicon away from the back intrinsic amorphous silicon film.

[0008] Furthermore, it also includes an electrode structure, which includes a front electrode and a back electrode; a plurality of the front electrodes are arranged on a side of the front conductive oxide film away from the N-type amorphous silicon, and the distance between two adjacent front electrodes is the same; a plurality of the back electrodes are arranged on a side of the back conductive oxide film away from the P-type amorphous silicon, and the distance between two adjacent back electrodes is the same.

[0009] Furthermore, the middle battery structure, the front battery structure, and the back battery structure form a PN heterojunction, and the PN heterojunction power temperature coefficient is -0.25-0.2%°C.

[0010] Furthermore, the front conductive oxide film and the back conductive oxide film are light-transmitting conductive oxide films, and the double-sidedness of the light-transmitting conductive oxide films is greater than or equal to 90%.

[0011] Furthermore, the thickness of the front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film is 7 nm, and the thickness of the N-type amorphous silicon and the p-type amorphous silicon is 17 nm.

[0012] Furthermore, the conductive oxide film structure adopts ITO, SCOT, IWO, ICO target materials.

[0013] The present invention also provides a method for preparing a heterojunction battery structure, comprising the following steps: Furthermore, the middle battery structure is cleaned; a front intrinsic amorphous silicon film and N-type amorphous silicon are deposited on one side of the middle battery structure, and a back intrinsic amorphous silicon film and P-type amorphous silicon are deposited on the other side of the middle battery structure to form a PN heterojunction; deposition is performed on the side where the N-type amorphous silicon and the P-type amorphous silicon are away from each other to form a front conductive oxide film and a back conductive oxide film.

[0014] Furthermore, the deposition is performed on the side where the N-type amorphous silicon and the P-type amorphous silicon are away from each other to form a front conductive oxide film and a back conductive oxide film, and screen printing is performed on the side where the front conductive oxide film and the back conductive oxide film are away from each other to form a front electrode and a back electrode.

[0015] Furthermore, the PN heterojunction temperature is less than or equal to 200°C.

[0016] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention discloses a heterojunction battery structure. A front intrinsic amorphous silicon film is deposited on the front side of N-type monocrystalline silicon, the N-type amorphous silicon forms an intrinsic layer and a doped layer, and a front conductive oxide film is deposited on the doped layer; a back intrinsic amorphous silicon film is deposited on the back side of N-type monocrystalline silicon, the P-type amorphous silicon forms an intrinsic layer and a doped layer, and a back conductive oxide film is deposited on the doped layer. The structure is symmetrical and the process is simple. The front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film are deposited by a PECVD method, and the front conductive oxide film and the back conductive oxide film are deposited by RPD and PVD. Currently, the PVD technology is mature and many manufacturers provide equipment.

[0017] The present invention provides a heterojunction battery structure, in which the intrinsic amorphous silicon film on the front side and the intrinsic amorphous silicon film on the back side form an intrinsic layer, which can effectively passivate the interface defects of crystalline silicon and doped amorphous silicon to form a higher open circuit voltage; in addition, the surface of the heterojunction battery is a front conductive oxide film and a back conductive oxide film, which is more conducive to the future superposition of perovskite and IBC to form a composite structure, and the efficiency of the composite structure can be increased to more than 30%.

[0018] The present invention discloses a heterojunction battery structure, wherein the surfaces of the heterojunction battery are a front conductive oxide film and a back conductive oxide film, and the electric charge will not generate polarization phenomenon and PID potential induced attenuation phenomenon on the front conductive oxide film and the back conductive oxide film. The heterojunction battery structure is N-type single crystal silicon, specifically phosphorus-doped, and does not have boron-oxygen compound, boron-iron compound, etc. in P-type crystalline silicon, and is immune to LID light-induced attenuation effect.

[0019] The present invention provides a heterojunction battery structure, the power temperature coefficient is usually -0.25-0.2%℃, which is lower than the -0.45-0.35%℃ of conventional and PERC passivated emitter and back cells. The heterojunction battery structure has higher power generation performance, can achieve power generation gain, and reduce the cost per kilowatt-hour.

[0020] The present invention discloses a heterojunction battery structure, which adopts a front-back symmetrical structure, and the front conductive oxide film and the back conductive oxide film are light-transmissive, forming a natural bifacial battery, and the bifaciality can reach more than 90%, with a maximum of 98%, while the bifaciality of the double-sided PERC passivated emitter and the back battery is only 75%. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural diagram of a heterojunction battery structure of the present invention. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0023] Example 1 The heterojunction battery structure of the present invention is as follows: Figure 1 As shown, it includes an intermediate cell structure, and the intermediate cell structure is N-type single crystal silicon; A front battery structure, wherein the front battery structure comprises a front intrinsic amorphous silicon film and N-type amorphous silicon, wherein the front intrinsic amorphous silicon film is stacked and arranged on one side of the middle battery structure, and the N-type amorphous silicon is stacked and arranged on a side of the front intrinsic amorphous silicon film away from the middle battery structure; A back battery structure, wherein the back battery structure comprises a back intrinsic amorphous silicon film and P-type amorphous silicon, wherein the back intrinsic amorphous silicon film is stacked and arranged on the other side of the middle battery structure, and the P-type amorphous silicon is stacked and arranged on the side of the back intrinsic amorphous silicon film away from the middle battery structure; The thickness of the front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film is 5-10 nm, and the thickness of the N-type amorphous silicon and the p-type amorphous silicon is 15-20 nm.

[0024] Specifically, the heterojunction cell structure is arranged into a front cell structure, a middle cell structure, and a back cell structure. The middle cell structure is N-type monocrystalline silicon, which uses N-type monocrystalline silicon as the core light absorption layer or substrate material. It is formed by doping silicon with pentavalent elements such as phosphorus to form a semiconductor material with excess free electrons, which becomes negatively charged and is beneficial to the photoelectric conversion process in the photovoltaic cell.

[0025] The front cell structure includes a front intrinsic amorphous silicon film and N-type amorphous silicon. The front intrinsic amorphous silicon film is stacked and arranged on one side of the middle cell structure. The N-type amorphous silicon is stacked and arranged on the side of the front intrinsic amorphous silicon film away from the middle cell structure. The front intrinsic amorphous silicon film constitutes an intrinsic layer, which can effectively passivate the interface defects of crystalline silicon and doped amorphous silicon. The N-type amorphous silicon is installed on the upper end of the front intrinsic amorphous silicon film to form a doping layer for collecting photogenerated electrons. The thickness of the front intrinsic amorphous silicon film is 5-10nm, and the thickness of the N-type amorphous silicon is 15-20nm.

[0026] The thickness of the front intrinsic amorphous silicon film is 5-10nm, which is based on comprehensive consideration of multiple factors such as material properties, battery performance and production process, including but not limited to material properties. The physical and chemical properties of non-silicon materials determine the selection range of its thickness; battery performance, battery conversion efficiency, stability and other performance indicators have requirements for film thickness; production process. The accuracy and stability of the production process will also affect the manufacturability range and consistency of the film thickness. In most cases, it is a relatively reasonable and effective choice.

[0027] The thickness of N-type amorphous silicon is 15-20 nm, which can reduce light absorption loss and increase the open circuit voltage of the battery. The specific thickness can be adjusted accordingly according to actual conditions.

[0028] The back battery structure includes a back intrinsic amorphous silicon film and P-type amorphous silicon. The back intrinsic amorphous silicon film is stacked on the other side of the middle battery structure, and the P-type amorphous silicon is stacked on the side of the back intrinsic amorphous silicon film away from the middle battery structure.

[0029] The thickness of the back intrinsic amorphous silicon film is 5-10 nm, and the thickness of the p-type amorphous silicon film is 15-20 nm.

[0030] In addition to the middle cell structure, the front cell structure, and the back cell structure, the heterojunction cell structure also includes a conductive oxide film structure and an electrode structure, wherein the conductive oxide film structure is prepared using ITO, SCOT, IWO, and ICO targets. ITO targets are indium tin oxide, a composite material composed of indium, tin, and oxygen, usually containing about 90% indium oxide and 10% tin oxide, with high strength, good electrical conductivity, thermal stability, and mechanical hardness.

[0031] IWO target is a composite material target composed of indium oxide and tungsten oxide. The density of IWO target is 6.5g / cm³~7.18g / cm³. Indium oxide, as the main component, provides the basic electrical and optical properties of the material; while tungsten oxide optimizes the conductivity and other physical properties of the target by adjusting its content. It is widely used in solar cells, display screens, coatings and other fields.

[0032] ICO targets are mainly composed of indium oxide and cerium oxide. They have high conductivity, visible light transmittance, mechanical hardness and good chemical stability. They are widely used in large-area coated glass in buildings / automobiles, thin-film photovoltaic solar energy, flat-panel displays, decorative / functional coatings, semiconductors and surface repair.

[0033] The conductive oxide film structure includes a front conductive oxide film and a back conductive oxide film. The front conductive oxide film is arranged on the upper end of the N-type amorphous silicon, and the back conductive oxide film is arranged on the lower end of the P-type amorphous silicon. The front conductive oxide film has excellent conductivity and can effectively collect and transmit photogenerated carriers. At the same time, the front conductive oxide film is transparent and will not significantly block the incident light, thus ensuring the light absorption efficiency of the heterojunction battery. Finally, it can also reduce optical reflection and improve the utilization rate of light. Because the heterojunction battery structure is a double-sided battery, the back conductive oxide film is installed on the back to collect and transmit photogenerated carriers to achieve double-sided power generation. The back conductive oxide film and the front conductive oxide film are symmetrical in structure, ensuring the overall performance and stability.

[0034] The electrode structure includes a front electrode and a back electrode. A plurality of the front electrodes are arranged on the side of the front conductive oxide film away from the N-type amorphous silicon, and the distance between two adjacent front electrodes is the same. A plurality of the back electrodes are arranged on the side of the back conductive oxide film away from the P-type amorphous silicon, and the distance between two adjacent back electrodes is the same. The front electrode is located on the light-receiving surface of the heterojunction battery and can directly receive sunlight. The back electrode is located on the back of the heterojunction battery, opposite to the front electrode.

[0035] The middle battery structure, the front battery structure, and the back battery structure constitute a PN heterojunction. The power temperature coefficient of the PN heterojunction is -0.25-0.2%℃. The power temperature coefficient describes the degree of power reduction of the heterojunction battery structure in a high temperature environment. The smaller the coefficient value, the smaller the power reduction of the battery at high temperature and the more stable the performance.

[0036] It should be noted that the front conductive oxide film and the back conductive oxide film are light-transmitting conductive oxide films. In this embodiment, the double-sidedness of the light-transmitting conductive oxide film is 98%.

[0037] Example 2 The invention discloses a method for preparing a heterojunction battery structure, comprising the following steps: cleaning an intermediate battery structure; depositing a front intrinsic amorphous silicon film and N-type amorphous silicon on one side of the intermediate battery structure, and depositing a back intrinsic amorphous silicon film and P-type amorphous silicon on the other side of the intermediate battery structure to form a PN heterojunction; and depositing on the side where the N-type amorphous silicon and the P-type amorphous silicon are far away from each other to form a front conductive oxide film and a back conductive oxide film.

[0038] Specifically, the surface of the intermediate battery structure may be contaminated by organic impurities, particles, metal ions, etc. during the early processing. The first step is to clean the intermediate battery structure. At the same time, in order to increase the energy absorption of light and improve the passivation effect, a pyramid morphology is etched on the surface of the silicon wafer as a flame structure. After that, the front intrinsic amorphous silicon film and N-type amorphous silicon are deposited on one side of the intermediate battery structure by chemical vapor deposition, and the back intrinsic amorphous silicon film and P-type amorphous silicon are deposited on the other side. The front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film determine the effectiveness of the passivation of the heterojunction battery, and the passivation effect is the guarantee of the improvement of conversion efficiency. After that, the physical vapor deposition method is used to bombard the cathode target material with argon ions generated by glow discharge, and the target material is sputtered and deposited to form a front conductive oxide film and a back conductive oxide film, which are used as an anti-reflection layer and a conductive layer for lateral transport of carriers to the electrode. The indicators of the front conductive oxide film and the back conductive oxide film are transmittance and resistivity. The higher the transmittance and the lower the resistivity, the better the utilization and conversion efficiency of the incident light. Finally, the process temperature of the PN heterojunction is limited to a low temperature environment within 200 degrees Celsius. The traditional high-temperature sintering production process is not suitable for the production of heterojunction battery structures. Therefore, in the preparation process of heterojunction batteries, the conductive paste is mainly applied on the solar cell through screen printing technology to form electrodes and wires.

[0039] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

Claims

1. A heterojunction battery structure, characterized in that: It includes an intermediate cell structure, wherein the intermediate cell structure is N-type single crystal silicon; A front battery structure, wherein the front battery structure comprises a front intrinsic amorphous silicon film and N-type amorphous silicon, wherein the front intrinsic amorphous silicon film is stacked and arranged on one side of the middle battery structure, and the N-type amorphous silicon is stacked and arranged on a side of the front intrinsic amorphous silicon film away from the middle battery structure; A back battery structure, wherein the back battery structure comprises a back intrinsic amorphous silicon film and P-type amorphous silicon, wherein the back intrinsic amorphous silicon film is stacked and arranged on the other side of the middle battery structure, and the P-type amorphous silicon is stacked and arranged on the side of the back intrinsic amorphous silicon film away from the middle battery structure; The thickness of the front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film is 5-10 nm, and the thickness of the N-type amorphous silicon and the p-type amorphous silicon is 15-20 nm.

2. The heterojunction battery structure according to claim 1, characterized in that: Also included is a conductive oxide film structure, wherein the conductive oxide film structure includes a front conductive oxide film and a back conductive oxide film; The front conductive oxide film is arranged on a side of the N-type amorphous silicon away from the front intrinsic amorphous silicon film, and the back conductive oxide film is arranged on a side of the P-type amorphous silicon away from the back intrinsic amorphous silicon film.

3. The heterojunction battery structure according to claim 2, characterized in that: Also included is an electrode structure, the electrode structure comprising a front electrode and a back electrode; The plurality of front electrodes are arranged on the side of the front conductive oxide film away from the N-type amorphous silicon, and the distance between two adjacent front electrodes is the same. The plurality of back electrodes are arranged on the side of the back conductive oxide film away from the P-type amorphous silicon, and the distance between two adjacent back electrodes is the same.

4. The heterojunction battery structure according to claim 2, characterized in that: The middle battery structure, the front battery structure and the back battery structure form a PN heterojunction, and the power temperature coefficient of the PN heterojunction is -0.25-0.2%°C.

5. The heterojunction battery structure according to claim 2, characterized in that: The front conductive oxide film and the back conductive oxide film are light-transmitting conductive oxide films, and the double-sidedness of the light-transmitting conductive oxide films is greater than or equal to 90%.

6. The heterojunction battery structure according to claim 1, characterized in that: The thickness of the front intrinsic amorphous silicon film and the back intrinsic amorphous silicon film is 7 nm, and the thickness of the N-type amorphous silicon and the p-type amorphous silicon is 17 nm.

7. The heterojunction battery structure according to claim 5, characterized in that: The conductive oxide film structure adopts ITO, SCOT, IWO and ICO target materials.

8. A method for preparing a heterojunction battery structure, characterized in that: The heterojunction battery structure according to any one of claims 1 to 7 comprises the following steps: Clean the middle battery structure; Depositing a front intrinsic amorphous silicon film and N-type amorphous silicon on one side of the middle battery structure, and depositing a back intrinsic amorphous silicon film and P-type amorphous silicon on the other side of the middle battery structure to form a PN heterojunction; Deposition is performed on the sides of the N-type amorphous silicon and the P-type amorphous silicon that are away from each other to form a front conductive oxide film and a back conductive oxide film.

9. The method for preparing a heterojunction battery structure according to claim 8, characterized in that: The method further comprises depositing on the side where the N-type amorphous silicon and the P-type amorphous silicon are far away from each other to form a front conductive oxide film and a back conductive oxide film, and screen printing on the side where the front conductive oxide film and the back conductive oxide film are far away from each other to form a front electrode and a back electrode.

10. The method for preparing a heterojunction battery structure according to claim 9, characterized in that The PN heterojunction temperature is less than or equal to 200°C.

Images